]>
Commit | Line | Data |
---|---|---|
1965aae3 PA |
1 | #ifndef _ASM_X86_IRQ_VECTORS_H |
2 | #define _ASM_X86_IRQ_VECTORS_H | |
9b7dc567 | 3 | |
9fc2e79d IM |
4 | /* |
5 | * Linux IRQ vector layout. | |
6 | * | |
7 | * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can | |
8 | * be defined by Linux. They are used as a jump table by the CPU when a | |
9 | * given vector is triggered - by a CPU-external, CPU-internal or | |
10 | * software-triggered event. | |
11 | * | |
12 | * Linux sets the kernel code address each entry jumps to early during | |
13 | * bootup, and never changes them. This is the general layout of the | |
14 | * IDT entries: | |
15 | * | |
16 | * Vectors 0 ... 31 : system traps and exceptions - hardcoded events | |
17 | * Vectors 32 ... 127 : device interrupts | |
18 | * Vector 128 : legacy int80 syscall interface | |
19 | * Vectors 129 ... 237 : device interrupts | |
20 | * Vectors 238 ... 255 : special interrupts | |
21 | * | |
22 | * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. | |
23 | * | |
24 | * This file enumerates the exact layout of them: | |
25 | */ | |
26 | ||
27 | #define NMI_VECTOR 0x02 | |
9b7dc567 TG |
28 | |
29 | /* | |
30 | * IDT vectors usable for external interrupt sources start | |
31 | * at 0x20: | |
32 | */ | |
9fc2e79d | 33 | #define FIRST_EXTERNAL_VECTOR 0x20 |
9b7dc567 TG |
34 | |
35 | #ifdef CONFIG_X86_32 | |
9fc2e79d | 36 | # define SYSCALL_VECTOR 0x80 |
9b7dc567 | 37 | #else |
9fc2e79d | 38 | # define IA32_SYSCALL_VECTOR 0x80 |
9b7dc567 TG |
39 | #endif |
40 | ||
41 | /* | |
9b7dc567 | 42 | * Reserve the lowest usable priority level 0x20 - 0x2f for triggering |
497c9a19 | 43 | * cleanup after irq migration. |
9b7dc567 | 44 | */ |
9fc2e79d | 45 | #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR |
9b7dc567 TG |
46 | |
47 | /* | |
497c9a19 | 48 | * Vectors 0x30-0x3f are used for ISA interrupts. |
9b7dc567 | 49 | */ |
9fc2e79d IM |
50 | #define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10) |
51 | ||
52 | #define IRQ1_VECTOR (IRQ0_VECTOR + 1) | |
53 | #define IRQ2_VECTOR (IRQ0_VECTOR + 2) | |
54 | #define IRQ3_VECTOR (IRQ0_VECTOR + 3) | |
55 | #define IRQ4_VECTOR (IRQ0_VECTOR + 4) | |
56 | #define IRQ5_VECTOR (IRQ0_VECTOR + 5) | |
57 | #define IRQ6_VECTOR (IRQ0_VECTOR + 6) | |
58 | #define IRQ7_VECTOR (IRQ0_VECTOR + 7) | |
59 | #define IRQ8_VECTOR (IRQ0_VECTOR + 8) | |
60 | #define IRQ9_VECTOR (IRQ0_VECTOR + 9) | |
61 | #define IRQ10_VECTOR (IRQ0_VECTOR + 10) | |
62 | #define IRQ11_VECTOR (IRQ0_VECTOR + 11) | |
63 | #define IRQ12_VECTOR (IRQ0_VECTOR + 12) | |
64 | #define IRQ13_VECTOR (IRQ0_VECTOR + 13) | |
65 | #define IRQ14_VECTOR (IRQ0_VECTOR + 14) | |
66 | #define IRQ15_VECTOR (IRQ0_VECTOR + 15) | |
9b7dc567 TG |
67 | |
68 | /* | |
69 | * Special IRQ vectors used by the SMP architecture, 0xf0-0xff | |
70 | * | |
71 | * some of the following vectors are 'rare', they are merged | |
72 | * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. | |
73 | * TLB, reschedule and local APIC vectors are performance-critical. | |
9b7dc567 | 74 | */ |
02cf94c3 | 75 | |
5da690d2 | 76 | #define SPURIOUS_APIC_VECTOR 0xff |
647ad94f IM |
77 | /* |
78 | * Sanity check | |
79 | */ | |
80 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
81 | # error SPURIOUS_APIC_VECTOR definition error | |
82 | #endif | |
83 | ||
5da690d2 IM |
84 | #define ERROR_APIC_VECTOR 0xfe |
85 | #define RESCHEDULE_VECTOR 0xfd | |
86 | #define CALL_FUNCTION_VECTOR 0xfc | |
87 | #define CALL_FUNCTION_SINGLE_VECTOR 0xfb | |
88 | #define THERMAL_APIC_VECTOR 0xfa | |
9b7dc567 | 89 | |
5da690d2 IM |
90 | #ifdef CONFIG_X86_32 |
91 | /* 0xf8 - 0xf9 : free */ | |
9b7dc567 | 92 | #else |
6dd01bed TH |
93 | # define THRESHOLD_APIC_VECTOR 0xf9 |
94 | # define UV_BAU_MESSAGE 0xf8 | |
5da690d2 | 95 | #endif |
9b7dc567 | 96 | |
5da690d2 IM |
97 | /* f0-f7 used for spreading out TLB flushes: */ |
98 | #define INVALIDATE_TLB_VECTOR_END 0xf7 | |
99 | #define INVALIDATE_TLB_VECTOR_START 0xf0 | |
9fc2e79d | 100 | #define NUM_INVALIDATE_TLB_VECTORS 8 |
9b7dc567 | 101 | |
9b7dc567 TG |
102 | /* |
103 | * Local APIC timer IRQ vector is on a different priority level, | |
104 | * to work around the 'lost local interrupt if more than 2 IRQ | |
105 | * sources per level' errata. | |
106 | */ | |
9fc2e79d | 107 | #define LOCAL_TIMER_VECTOR 0xef |
9b7dc567 | 108 | |
193c81b9 IM |
109 | /* |
110 | * Performance monitoring interrupt vector: | |
111 | */ | |
9fc2e79d | 112 | #define LOCAL_PERF_VECTOR 0xee |
193c81b9 | 113 | |
acaabe79 DS |
114 | /* |
115 | * Generic system vector for platform specific use | |
116 | */ | |
117 | #define GENERIC_INTERRUPT_VECTOR 0xed | |
118 | ||
9b7dc567 TG |
119 | /* |
120 | * First APIC vector available to drivers: (vectors 0x30-0xee) we | |
121 | * start at 0x31(0x41) to spread out vectors evenly between priority | |
122 | * levels. (0x80 is the syscall vector) | |
123 | */ | |
9fc2e79d | 124 | #define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2) |
9b7dc567 | 125 | |
9fc2e79d | 126 | #define NR_VECTORS 256 |
9b7dc567 | 127 | |
9fc2e79d | 128 | #define FPU_IRQ 13 |
9b7dc567 | 129 | |
9fc2e79d IM |
130 | #define FIRST_VM86_IRQ 3 |
131 | #define LAST_VM86_IRQ 15 | |
d8106d2e IM |
132 | |
133 | #ifndef __ASSEMBLY__ | |
134 | static inline int invalid_vm86_irq(int irq) | |
135 | { | |
57e37293 | 136 | return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; |
d8106d2e IM |
137 | } |
138 | #endif | |
9b7dc567 | 139 | |
009eb3fe IM |
140 | /* |
141 | * Size the maximum number of interrupts. | |
142 | * | |
143 | * If the irq_desc[] array has a sparse layout, we can size things | |
144 | * generously - it scales up linearly with the maximum number of CPUs, | |
145 | * and the maximum number of IO-APICs, whichever is higher. | |
146 | * | |
147 | * In other cases we size more conservatively, to not create too large | |
148 | * static arrays. | |
149 | */ | |
150 | ||
9fc2e79d | 151 | #define NR_IRQS_LEGACY 16 |
99d093d1 | 152 | |
009eb3fe IM |
153 | #define CPU_VECTOR_LIMIT ( 8 * NR_CPUS ) |
154 | #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) | |
155 | ||
3e92ab3d | 156 | #ifdef CONFIG_X86_IO_APIC |
009eb3fe IM |
157 | # ifdef CONFIG_SPARSE_IRQ |
158 | # define NR_IRQS \ | |
159 | (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ | |
160 | (NR_VECTORS + CPU_VECTOR_LIMIT) : \ | |
161 | (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) | |
162 | # else | |
c379698f | 163 | # if NR_CPUS < MAX_IO_APICS |
009eb3fe | 164 | # define NR_IRQS (NR_VECTORS + 4*CPU_VECTOR_LIMIT) |
c379698f | 165 | # else |
009eb3fe | 166 | # define NR_IRQS (NR_VECTORS + IO_APIC_VECTOR_LIMIT) |
c379698f | 167 | # endif |
c379698f | 168 | # endif |
3e92ab3d | 169 | #else /* !CONFIG_X86_IO_APIC: */ |
009eb3fe | 170 | # define NR_IRQS NR_IRQS_LEGACY |
1b489768 | 171 | #endif |
9b7dc567 | 172 | |
1965aae3 | 173 | #endif /* _ASM_X86_IRQ_VECTORS_H */ |