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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
34c16eec | 25 | |
50d0a0f9 | 26 | #include <asm/pvclock-abi.h> |
e01a1b57 | 27 | #include <asm/desc.h> |
0bed3b56 | 28 | #include <asm/mtrr.h> |
9962d032 | 29 | #include <asm/msr-index.h> |
e01a1b57 | 30 | |
8c3ba334 | 31 | #define KVM_MAX_VCPUS 254 |
a59cb29e | 32 | #define KVM_SOFT_MAX_VCPUS 160 |
69a9f69b AK |
33 | #define KVM_MEMORY_SLOTS 32 |
34 | /* memory slots that does not exposed to userspace */ | |
35 | #define KVM_PRIVATE_MEM_SLOTS 4 | |
93a5cef0 XG |
36 | #define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
37 | ||
cef4dea0 | 38 | #define KVM_MMIO_SIZE 16 |
69a9f69b AK |
39 | |
40 | #define KVM_PIO_PAGE_OFFSET 1 | |
542472b5 | 41 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
69a9f69b | 42 | |
cfec82cb JR |
43 | #define CR0_RESERVED_BITS \ |
44 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
45 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
46 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
47 | ||
cd6e8f87 ZX |
48 | #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) |
49 | #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) | |
7d76b4d3 JP |
50 | #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ |
51 | 0xFFFFFF0000000000ULL) | |
cfec82cb JR |
52 | #define CR4_RESERVED_BITS \ |
53 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
54 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
55 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
d9c3476d | 56 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \ |
cfec82cb JR |
57 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
58 | ||
59 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
60 | ||
61 | ||
cd6e8f87 | 62 | |
cd6e8f87 | 63 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
64 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
65 | ||
cd6e8f87 ZX |
66 | #define UNMAPPED_GVA (~(gpa_t)0) |
67 | ||
ec04b260 | 68 | /* KVM Hugepage definitions for x86 */ |
04326caa | 69 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
70 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
71 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
72 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
73 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
74 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 75 | |
cd6e8f87 | 76 | #define DE_VECTOR 0 |
19bd8afd | 77 | #define DB_VECTOR 1 |
77ab6db0 JK |
78 | #define BP_VECTOR 3 |
79 | #define OF_VECTOR 4 | |
80 | #define BR_VECTOR 5 | |
cd6e8f87 ZX |
81 | #define UD_VECTOR 6 |
82 | #define NM_VECTOR 7 | |
83 | #define DF_VECTOR 8 | |
84 | #define TS_VECTOR 10 | |
85 | #define NP_VECTOR 11 | |
86 | #define SS_VECTOR 12 | |
87 | #define GP_VECTOR 13 | |
88 | #define PF_VECTOR 14 | |
77ab6db0 | 89 | #define MF_VECTOR 16 |
53371b50 | 90 | #define MC_VECTOR 18 |
cd6e8f87 ZX |
91 | |
92 | #define SELECTOR_TI_MASK (1 << 2) | |
93 | #define SELECTOR_RPL_MASK 0x03 | |
94 | ||
95 | #define IOPL_SHIFT 12 | |
96 | ||
d657a98e ZX |
97 | #define KVM_PERMILLE_MMU_PAGES 20 |
98 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
99 | #define KVM_MMU_HASH_SHIFT 10 |
100 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
101 | #define KVM_MIN_FREE_MMU_PAGES 5 |
102 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 103 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 104 | #define KVM_NR_FIXED_MTRR_REGION 88 |
9ba075a6 | 105 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 106 | |
af585b92 GN |
107 | #define ASYNC_PF_PER_VCPU 64 |
108 | ||
e935b837 | 109 | extern raw_spinlock_t kvm_lock; |
e9b11c17 ZX |
110 | extern struct list_head vm_list; |
111 | ||
d657a98e ZX |
112 | struct kvm_vcpu; |
113 | struct kvm; | |
af585b92 | 114 | struct kvm_async_pf; |
d657a98e | 115 | |
5fdbf976 | 116 | enum kvm_reg { |
2b3ccfa0 ZX |
117 | VCPU_REGS_RAX = 0, |
118 | VCPU_REGS_RCX = 1, | |
119 | VCPU_REGS_RDX = 2, | |
120 | VCPU_REGS_RBX = 3, | |
121 | VCPU_REGS_RSP = 4, | |
122 | VCPU_REGS_RBP = 5, | |
123 | VCPU_REGS_RSI = 6, | |
124 | VCPU_REGS_RDI = 7, | |
125 | #ifdef CONFIG_X86_64 | |
126 | VCPU_REGS_R8 = 8, | |
127 | VCPU_REGS_R9 = 9, | |
128 | VCPU_REGS_R10 = 10, | |
129 | VCPU_REGS_R11 = 11, | |
130 | VCPU_REGS_R12 = 12, | |
131 | VCPU_REGS_R13 = 13, | |
132 | VCPU_REGS_R14 = 14, | |
133 | VCPU_REGS_R15 = 15, | |
134 | #endif | |
5fdbf976 | 135 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
136 | NR_VCPU_REGS |
137 | }; | |
138 | ||
6de4f3ad AK |
139 | enum kvm_reg_ex { |
140 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 141 | VCPU_EXREG_CR3, |
6de12732 | 142 | VCPU_EXREG_RFLAGS, |
69c73028 | 143 | VCPU_EXREG_CPL, |
2fb92db1 | 144 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
145 | }; |
146 | ||
2b3ccfa0 | 147 | enum { |
81609e3e | 148 | VCPU_SREG_ES, |
2b3ccfa0 | 149 | VCPU_SREG_CS, |
81609e3e | 150 | VCPU_SREG_SS, |
2b3ccfa0 | 151 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
152 | VCPU_SREG_FS, |
153 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
154 | VCPU_SREG_TR, |
155 | VCPU_SREG_LDTR, | |
156 | }; | |
157 | ||
56e82318 | 158 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 159 | |
d657a98e ZX |
160 | #define KVM_NR_MEM_OBJS 40 |
161 | ||
42dbaa5a JK |
162 | #define KVM_NR_DB_REGS 4 |
163 | ||
164 | #define DR6_BD (1 << 13) | |
165 | #define DR6_BS (1 << 14) | |
166 | #define DR6_FIXED_1 0xffff0ff0 | |
167 | #define DR6_VOLATILE 0x0000e00f | |
168 | ||
169 | #define DR7_BP_EN_MASK 0x000000ff | |
170 | #define DR7_GE (1 << 9) | |
171 | #define DR7_GD (1 << 13) | |
172 | #define DR7_FIXED_1 0x00000400 | |
173 | #define DR7_VOLATILE 0xffff23ff | |
174 | ||
d657a98e ZX |
175 | /* |
176 | * We don't want allocation failures within the mmu code, so we preallocate | |
177 | * enough memory for a single page fault in a cache. | |
178 | */ | |
179 | struct kvm_mmu_memory_cache { | |
180 | int nobjs; | |
181 | void *objects[KVM_NR_MEM_OBJS]; | |
182 | }; | |
183 | ||
d657a98e ZX |
184 | /* |
185 | * kvm_mmu_page_role, below, is defined as: | |
186 | * | |
187 | * bits 0:3 - total guest paging levels (2-4, or zero for real mode) | |
188 | * bits 4:7 - page table level for this shadow (1-4) | |
189 | * bits 8:9 - page table quadrant for 2-level guests | |
f6e2c02b AK |
190 | * bit 16 - direct mapping of virtual to physical mapping at gfn |
191 | * used for real mode and two-dimensional paging | |
d657a98e ZX |
192 | * bits 17:19 - common access permissions for all ptes in this shadow page |
193 | */ | |
194 | union kvm_mmu_page_role { | |
195 | unsigned word; | |
196 | struct { | |
7d76b4d3 | 197 | unsigned level:4; |
5b7e0102 | 198 | unsigned cr4_pae:1; |
7d76b4d3 JP |
199 | unsigned quadrant:2; |
200 | unsigned pad_for_nice_hex_output:6; | |
f6e2c02b | 201 | unsigned direct:1; |
7d76b4d3 | 202 | unsigned access:3; |
2e53d63a | 203 | unsigned invalid:1; |
9645bb56 | 204 | unsigned nxe:1; |
3dbe1415 | 205 | unsigned cr0_wp:1; |
411c588d | 206 | unsigned smep_andnot_wp:1; |
d657a98e ZX |
207 | }; |
208 | }; | |
209 | ||
210 | struct kvm_mmu_page { | |
211 | struct list_head link; | |
212 | struct hlist_node hash_link; | |
213 | ||
214 | /* | |
215 | * The following two entries are used to key the shadow page in the | |
216 | * hash table. | |
217 | */ | |
218 | gfn_t gfn; | |
219 | union kvm_mmu_page_role role; | |
220 | ||
221 | u64 *spt; | |
222 | /* hold the gfn of each spte inside spt */ | |
223 | gfn_t *gfns; | |
291f26bc SY |
224 | /* |
225 | * One bit set per slot which has memory | |
226 | * in this shadow page. | |
227 | */ | |
93a5cef0 | 228 | DECLARE_BITMAP(slot_bitmap, KVM_MEM_SLOTS_NUM); |
4731d4c7 | 229 | bool unsync; |
0571d366 | 230 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 231 | unsigned int unsync_children; |
67052b35 | 232 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
0074ff63 | 233 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
234 | |
235 | #ifdef CONFIG_X86_32 | |
236 | int clear_spte_count; | |
237 | #endif | |
238 | ||
a30f47cb XG |
239 | int write_flooding_count; |
240 | ||
c2a2ac2b | 241 | struct rcu_head rcu; |
d657a98e ZX |
242 | }; |
243 | ||
1c08364c AK |
244 | struct kvm_pio_request { |
245 | unsigned long count; | |
1c08364c AK |
246 | int in; |
247 | int port; | |
248 | int size; | |
1c08364c AK |
249 | }; |
250 | ||
d657a98e ZX |
251 | /* |
252 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
253 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
254 | * mode. | |
255 | */ | |
256 | struct kvm_mmu { | |
257 | void (*new_cr3)(struct kvm_vcpu *vcpu); | |
f43addd4 | 258 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 259 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 260 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
261 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
262 | bool prefault); | |
6389ee94 AK |
263 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
264 | struct x86_exception *fault); | |
d657a98e | 265 | void (*free)(struct kvm_vcpu *vcpu); |
1871c602 | 266 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 267 | struct x86_exception *exception); |
c30a358d | 268 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
e8bc217a | 269 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 270 | struct kvm_mmu_page *sp); |
a7052897 | 271 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 272 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 273 | u64 *spte, const void *pte); |
d657a98e ZX |
274 | hpa_t root_hpa; |
275 | int root_level; | |
276 | int shadow_root_level; | |
a770f6f2 | 277 | union kvm_mmu_page_role base_role; |
c5a78f2b | 278 | bool direct_map; |
d657a98e ZX |
279 | |
280 | u64 *pae_root; | |
81407ca5 | 281 | u64 *lm_root; |
82725b20 | 282 | u64 rsvd_bits_mask[2][4]; |
ff03a073 | 283 | |
2d48a985 JR |
284 | bool nx; |
285 | ||
ff03a073 | 286 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
287 | }; |
288 | ||
f5132b01 GN |
289 | enum pmc_type { |
290 | KVM_PMC_GP = 0, | |
291 | KVM_PMC_FIXED, | |
292 | }; | |
293 | ||
294 | struct kvm_pmc { | |
295 | enum pmc_type type; | |
296 | u8 idx; | |
297 | u64 counter; | |
298 | u64 eventsel; | |
299 | struct perf_event *perf_event; | |
300 | struct kvm_vcpu *vcpu; | |
301 | }; | |
302 | ||
303 | struct kvm_pmu { | |
304 | unsigned nr_arch_gp_counters; | |
305 | unsigned nr_arch_fixed_counters; | |
306 | unsigned available_event_types; | |
307 | u64 fixed_ctr_ctrl; | |
308 | u64 global_ctrl; | |
309 | u64 global_status; | |
310 | u64 global_ovf_ctrl; | |
311 | u64 counter_bitmask[2]; | |
312 | u64 global_ctrl_mask; | |
313 | u8 version; | |
314 | struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC]; | |
315 | struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED]; | |
316 | struct irq_work irq_work; | |
317 | u64 reprogram_pmi; | |
318 | }; | |
319 | ||
ad312c7c | 320 | struct kvm_vcpu_arch { |
5fdbf976 MT |
321 | /* |
322 | * rip and regs accesses must go through | |
323 | * kvm_{register,rip}_{read,write} functions. | |
324 | */ | |
325 | unsigned long regs[NR_VCPU_REGS]; | |
326 | u32 regs_avail; | |
327 | u32 regs_dirty; | |
34c16eec ZX |
328 | |
329 | unsigned long cr0; | |
e8467fda | 330 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
331 | unsigned long cr2; |
332 | unsigned long cr3; | |
333 | unsigned long cr4; | |
fc78f519 | 334 | unsigned long cr4_guest_owned_bits; |
34c16eec | 335 | unsigned long cr8; |
1371d904 | 336 | u32 hflags; |
f6801dff | 337 | u64 efer; |
34c16eec ZX |
338 | u64 apic_base; |
339 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
e1035715 | 340 | int32_t apic_arb_prio; |
34c16eec ZX |
341 | int mp_state; |
342 | int sipi_vector; | |
343 | u64 ia32_misc_enable_msr; | |
b209749f | 344 | bool tpr_access_reporting; |
34c16eec | 345 | |
14dfe855 JR |
346 | /* |
347 | * Paging state of the vcpu | |
348 | * | |
349 | * If the vcpu runs in guest mode with two level paging this still saves | |
350 | * the paging mode of the l1 guest. This context is always used to | |
351 | * handle faults. | |
352 | */ | |
34c16eec | 353 | struct kvm_mmu mmu; |
8df25a32 | 354 | |
6539e738 JR |
355 | /* |
356 | * Paging state of an L2 guest (used for nested npt) | |
357 | * | |
358 | * This context will save all necessary information to walk page tables | |
359 | * of the an L2 guest. This context is only initialized for page table | |
360 | * walking and not for faulting since we never handle l2 page faults on | |
361 | * the host. | |
362 | */ | |
363 | struct kvm_mmu nested_mmu; | |
364 | ||
14dfe855 JR |
365 | /* |
366 | * Pointer to the mmu context currently used for | |
367 | * gva_to_gpa translations. | |
368 | */ | |
369 | struct kvm_mmu *walk_mmu; | |
370 | ||
53c07b18 | 371 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
372 | struct kvm_mmu_memory_cache mmu_page_cache; |
373 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
374 | ||
98918833 | 375 | struct fpu guest_fpu; |
2acf923e | 376 | u64 xcr0; |
34c16eec | 377 | |
34c16eec ZX |
378 | struct kvm_pio_request pio; |
379 | void *pio_data; | |
380 | ||
66fd3f7f GN |
381 | u8 event_exit_inst_len; |
382 | ||
298101da AK |
383 | struct kvm_queued_exception { |
384 | bool pending; | |
385 | bool has_error_code; | |
ce7ddec4 | 386 | bool reinject; |
298101da AK |
387 | u8 nr; |
388 | u32 error_code; | |
389 | } exception; | |
390 | ||
937a7eae AK |
391 | struct kvm_queued_interrupt { |
392 | bool pending; | |
66fd3f7f | 393 | bool soft; |
937a7eae AK |
394 | u8 nr; |
395 | } interrupt; | |
396 | ||
34c16eec ZX |
397 | int halt_request; /* real mode on Intel only */ |
398 | ||
399 | int cpuid_nent; | |
07716717 | 400 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
34c16eec ZX |
401 | /* emulate context */ |
402 | ||
403 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
404 | bool emulate_regs_need_sync_to_vcpu; |
405 | bool emulate_regs_need_sync_from_vcpu; | |
18068523 GOC |
406 | |
407 | gpa_t time; | |
50d0a0f9 | 408 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 409 | unsigned int hw_tsc_khz; |
18068523 GOC |
410 | unsigned int time_offset; |
411 | struct page *time_page; | |
c9aaa895 GC |
412 | |
413 | struct { | |
414 | u64 msr_val; | |
415 | u64 last_steal; | |
416 | u64 accum_steal; | |
417 | struct gfn_to_hva_cache stime; | |
418 | struct kvm_steal_time steal; | |
419 | } st; | |
420 | ||
1d5f066e ZA |
421 | u64 last_guest_tsc; |
422 | u64 last_kernel_ns; | |
6f526ec5 | 423 | u64 last_host_tsc; |
0dd6a6ed | 424 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
425 | u64 this_tsc_nsec; |
426 | u64 this_tsc_write; | |
427 | u8 this_tsc_generation; | |
c285545f | 428 | bool tsc_catchup; |
cc578287 ZA |
429 | bool tsc_always_catchup; |
430 | s8 virtual_tsc_shift; | |
431 | u32 virtual_tsc_mult; | |
432 | u32 virtual_tsc_khz; | |
3419ffc8 | 433 | |
7460fb4a AK |
434 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
435 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
436 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
9ba075a6 | 437 | |
0bed3b56 SY |
438 | struct mtrr_state_type mtrr_state; |
439 | u32 pat; | |
42dbaa5a JK |
440 | |
441 | int switch_db_regs; | |
42dbaa5a JK |
442 | unsigned long db[KVM_NR_DB_REGS]; |
443 | unsigned long dr6; | |
444 | unsigned long dr7; | |
445 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
890ca9ae HY |
446 | |
447 | u64 mcg_cap; | |
448 | u64 mcg_status; | |
449 | u64 mcg_ctl; | |
450 | u64 *mce_banks; | |
94fe45da | 451 | |
bebb106a XG |
452 | /* Cache MMIO info */ |
453 | u64 mmio_gva; | |
454 | unsigned access; | |
455 | gfn_t mmio_gfn; | |
456 | ||
f5132b01 GN |
457 | struct kvm_pmu pmu; |
458 | ||
94fe45da | 459 | /* used for guest single stepping over the given code position */ |
94fe45da | 460 | unsigned long singlestep_rip; |
f92653ee | 461 | |
10388a07 GN |
462 | /* fields used by HYPER-V emulation */ |
463 | u64 hv_vapic; | |
f5f48ee1 SY |
464 | |
465 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 466 | |
1cb3f3ae XG |
467 | unsigned long last_retry_eip; |
468 | unsigned long last_retry_addr; | |
469 | ||
af585b92 GN |
470 | struct { |
471 | bool halted; | |
472 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
473 | struct gfn_to_hva_cache data; |
474 | u64 msr_val; | |
7c90705b | 475 | u32 id; |
6adba527 | 476 | bool send_user_only; |
af585b92 | 477 | } apf; |
2b036c6b BO |
478 | |
479 | /* OSVW MSRs (AMD only) */ | |
480 | struct { | |
481 | u64 length; | |
482 | u64 status; | |
483 | } osvw; | |
34c16eec ZX |
484 | }; |
485 | ||
db3fe4eb TY |
486 | struct kvm_lpage_info { |
487 | unsigned long rmap_pde; | |
488 | int write_count; | |
489 | }; | |
490 | ||
491 | struct kvm_arch_memory_slot { | |
492 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; | |
493 | }; | |
494 | ||
fef9cce0 | 495 | struct kvm_arch { |
49d5ca26 | 496 | unsigned int n_used_mmu_pages; |
f05e70ac | 497 | unsigned int n_requested_mmu_pages; |
39de71ec | 498 | unsigned int n_max_mmu_pages; |
332b207d | 499 | unsigned int indirect_shadow_pages; |
f05e70ac ZX |
500 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
501 | /* | |
502 | * Hash table of struct kvm_mmu_page. | |
503 | */ | |
504 | struct list_head active_mmu_pages; | |
4d5c5d0f | 505 | struct list_head assigned_dev_head; |
19de40a8 | 506 | struct iommu_domain *iommu_domain; |
522c68c4 | 507 | int iommu_flags; |
d7deeeb0 ZX |
508 | struct kvm_pic *vpic; |
509 | struct kvm_ioapic *vioapic; | |
7837699f | 510 | struct kvm_pit *vpit; |
cc6e462c | 511 | int vapics_in_nmi_mode; |
bfc6d222 | 512 | |
bfc6d222 ZX |
513 | unsigned int tss_addr; |
514 | struct page *apic_access_page; | |
18068523 GOC |
515 | |
516 | gpa_t wall_clock; | |
b7ebfb05 SY |
517 | |
518 | struct page *ept_identity_pagetable; | |
519 | bool ept_identity_pagetable_done; | |
b927a3ce | 520 | gpa_t ept_identity_map_addr; |
5550af4d SY |
521 | |
522 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 523 | s64 kvmclock_offset; |
038f8c11 | 524 | raw_spinlock_t tsc_write_lock; |
f38e098f | 525 | u64 last_tsc_nsec; |
f38e098f | 526 | u64 last_tsc_write; |
5d3cb0f6 | 527 | u32 last_tsc_khz; |
e26101b1 ZA |
528 | u64 cur_tsc_nsec; |
529 | u64 cur_tsc_write; | |
530 | u64 cur_tsc_offset; | |
531 | u8 cur_tsc_generation; | |
ffde22ac ES |
532 | |
533 | struct kvm_xen_hvm_config xen_hvm_config; | |
55cd8e5a GN |
534 | |
535 | /* fields used by HYPER-V emulation */ | |
536 | u64 hv_guest_os_id; | |
537 | u64 hv_hypercall; | |
b034cf01 | 538 | |
c2a2ac2b XG |
539 | atomic_t reader_counter; |
540 | ||
b034cf01 XG |
541 | #ifdef CONFIG_KVM_MMU_AUDIT |
542 | int audit_point; | |
543 | #endif | |
d69fb81f ZX |
544 | }; |
545 | ||
0711456c ZX |
546 | struct kvm_vm_stat { |
547 | u32 mmu_shadow_zapped; | |
548 | u32 mmu_pte_write; | |
549 | u32 mmu_pte_updated; | |
550 | u32 mmu_pde_zapped; | |
551 | u32 mmu_flooded; | |
552 | u32 mmu_recycled; | |
dfc5aa00 | 553 | u32 mmu_cache_miss; |
4731d4c7 | 554 | u32 mmu_unsync; |
0711456c | 555 | u32 remote_tlb_flush; |
05da4558 | 556 | u32 lpages; |
0711456c ZX |
557 | }; |
558 | ||
77b4c255 ZX |
559 | struct kvm_vcpu_stat { |
560 | u32 pf_fixed; | |
561 | u32 pf_guest; | |
562 | u32 tlb_flush; | |
563 | u32 invlpg; | |
564 | ||
565 | u32 exits; | |
566 | u32 io_exits; | |
567 | u32 mmio_exits; | |
568 | u32 signal_exits; | |
569 | u32 irq_window_exits; | |
f08864b4 | 570 | u32 nmi_window_exits; |
77b4c255 ZX |
571 | u32 halt_exits; |
572 | u32 halt_wakeup; | |
573 | u32 request_irq_exits; | |
574 | u32 irq_exits; | |
575 | u32 host_state_reload; | |
576 | u32 efer_reload; | |
577 | u32 fpu_reload; | |
578 | u32 insn_emulation; | |
579 | u32 insn_emulation_fail; | |
f11c3a8d | 580 | u32 hypercalls; |
fa89a817 | 581 | u32 irq_injections; |
c4abb7c9 | 582 | u32 nmi_injections; |
77b4c255 | 583 | }; |
ad312c7c | 584 | |
8a76d7f2 JR |
585 | struct x86_instruction_info; |
586 | ||
ea4a5ff8 ZX |
587 | struct kvm_x86_ops { |
588 | int (*cpu_has_kvm_support)(void); /* __init */ | |
589 | int (*disabled_by_bios)(void); /* __init */ | |
10474ae8 | 590 | int (*hardware_enable)(void *dummy); |
ea4a5ff8 ZX |
591 | void (*hardware_disable)(void *dummy); |
592 | void (*check_processor_compatibility)(void *rtn); | |
593 | int (*hardware_setup)(void); /* __init */ | |
594 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 595 | bool (*cpu_has_accelerated_tpr)(void); |
0e851880 | 596 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
597 | |
598 | /* Create, but do not attach this VCPU */ | |
599 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
600 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
601 | int (*vcpu_reset)(struct kvm_vcpu *vcpu); | |
602 | ||
603 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
604 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
605 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 606 | |
355be0b9 JK |
607 | void (*set_guest_debug)(struct kvm_vcpu *vcpu, |
608 | struct kvm_guest_debug *dbg); | |
ea4a5ff8 ZX |
609 | int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata); |
610 | int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
611 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); | |
612 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
613 | struct kvm_segment *var, int seg); | |
2e4d2653 | 614 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
615 | void (*set_segment)(struct kvm_vcpu *vcpu, |
616 | struct kvm_segment *var, int seg); | |
617 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 618 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 619 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
620 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
621 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
622 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 623 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 624 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
625 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
626 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
627 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
628 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
020df079 | 629 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 630 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
631 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
632 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
6b52d186 | 633 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 634 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
635 | |
636 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 637 | |
851ba692 AK |
638 | void (*run)(struct kvm_vcpu *vcpu); |
639 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 640 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 GC |
641 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
642 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); | |
ea4a5ff8 ZX |
643 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
644 | unsigned char *hypercall_addr); | |
66fd3f7f | 645 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 646 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 647 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
648 | bool has_error_code, u32 error_code, |
649 | bool reinject); | |
b463a6f7 | 650 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 651 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 652 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
653 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
654 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
95ba8273 GN |
655 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
656 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
657 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); | |
ea4a5ff8 | 658 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 659 | int (*get_tdp_level)(void); |
4b12f0de | 660 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 661 | int (*get_lpage_level)(void); |
4e47c7a6 | 662 | bool (*rdtscp_supported)(void); |
f1e2b260 | 663 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 664 | |
1c97f0a0 JR |
665 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
666 | ||
d4330ef2 JR |
667 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
668 | ||
f5f48ee1 SY |
669 | bool (*has_wbinvd_exit)(void); |
670 | ||
cc578287 | 671 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
99e3e30a ZA |
672 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
673 | ||
857e4099 | 674 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
d5c1785d | 675 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu); |
857e4099 | 676 | |
586f9607 | 677 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
678 | |
679 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
680 | struct x86_instruction_info *info, | |
681 | enum x86_intercept_stage stage); | |
ea4a5ff8 ZX |
682 | }; |
683 | ||
af585b92 | 684 | struct kvm_arch_async_pf { |
7c90705b | 685 | u32 token; |
af585b92 | 686 | gfn_t gfn; |
fb67e14f | 687 | unsigned long cr3; |
c4806acd | 688 | bool direct_map; |
af585b92 GN |
689 | }; |
690 | ||
97896d04 ZX |
691 | extern struct kvm_x86_ops *kvm_x86_ops; |
692 | ||
f1e2b260 MT |
693 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
694 | s64 adjustment) | |
695 | { | |
696 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
697 | } | |
698 | ||
699 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
700 | { | |
701 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
702 | } | |
703 | ||
54f1585a ZX |
704 | int kvm_mmu_module_init(void); |
705 | void kvm_mmu_module_exit(void); | |
706 | ||
707 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
708 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
709 | int kvm_mmu_setup(struct kvm_vcpu *vcpu); | |
7b52345e | 710 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 711 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a ZX |
712 | |
713 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu); | |
714 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot); | |
5dc99b23 TY |
715 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
716 | struct kvm_memory_slot *slot, | |
717 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 718 | void kvm_mmu_zap_all(struct kvm *kvm); |
3ad82a7e | 719 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
720 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
721 | ||
ff03a073 | 722 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 723 | |
3200f405 | 724 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 725 | const void *val, int bytes); |
4b12f0de | 726 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); |
2f333bcb MT |
727 | |
728 | extern bool tdp_enabled; | |
9f811285 | 729 | |
a3e06bbe LJ |
730 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
731 | ||
92a1f12d JR |
732 | /* control of guest tsc rate supported? */ |
733 | extern bool kvm_has_tsc_control; | |
734 | /* minimum supported tsc_khz for guests */ | |
735 | extern u32 kvm_min_guest_tsc_khz; | |
736 | /* maximum supported tsc_khz for guests */ | |
737 | extern u32 kvm_max_guest_tsc_khz; | |
738 | ||
54f1585a ZX |
739 | enum emulation_result { |
740 | EMULATE_DONE, /* no further processing */ | |
741 | EMULATE_DO_MMIO, /* kvm_run filled with mmio request */ | |
742 | EMULATE_FAIL, /* can't emulate this instruction */ | |
743 | }; | |
744 | ||
571008da SY |
745 | #define EMULTYPE_NO_DECODE (1 << 0) |
746 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 747 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 748 | #define EMULTYPE_RETRY (1 << 3) |
dc25e89e AP |
749 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
750 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
751 | |
752 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
753 | int emulation_type) | |
754 | { | |
dc25e89e | 755 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
756 | } |
757 | ||
f2b4b7dd | 758 | void kvm_enable_efer_bits(u64); |
54f1585a ZX |
759 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); |
760 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
761 | ||
762 | struct x86_emulate_ctxt; | |
763 | ||
cf8f70bf | 764 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
765 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
766 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
f5f48ee1 | 767 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 768 | |
3e6e0aab | 769 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 770 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
3e6e0aab | 771 | |
7f3d35fd KW |
772 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
773 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 774 | |
49a9b07e | 775 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 776 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 777 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 778 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
779 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
780 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
781 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
782 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 783 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 784 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a ZX |
785 | |
786 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); | |
787 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
788 | ||
91586a3b JK |
789 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
790 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 791 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 792 | |
298101da AK |
793 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
794 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
795 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
796 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 797 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
798 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
799 | gfn_t gfn, void *data, int offset, int len, | |
800 | u32 access); | |
6389ee94 | 801 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
0a79b009 | 802 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
298101da | 803 | |
4925663a | 804 | int kvm_pic_set_irq(void *opaque, int irq, int level); |
3de42dc0 | 805 | |
3419ffc8 SY |
806 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
807 | ||
10ab25cd | 808 | int fx_init(struct kvm_vcpu *vcpu); |
54f1585a | 809 | |
d835dfec | 810 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); |
54f1585a | 811 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 812 | const u8 *new, int bytes); |
1cb3f3ae | 813 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
814 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
815 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
816 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
817 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 818 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
e459e322 | 819 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
ab9ae313 AK |
820 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
821 | struct x86_exception *exception); | |
822 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
823 | struct x86_exception *exception); | |
824 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
825 | struct x86_exception *exception); | |
826 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
827 | struct x86_exception *exception); | |
54f1585a ZX |
828 | |
829 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
830 | ||
dc25e89e AP |
831 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
832 | void *insn, int insn_len); | |
a7052897 | 833 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
34c16eec | 834 | |
18552672 | 835 | void kvm_enable_tdp(void); |
5f4cb662 | 836 | void kvm_disable_tdp(void); |
18552672 | 837 | |
de7d789a | 838 | int complete_pio(struct kvm_vcpu *vcpu); |
f850e2e6 | 839 | bool kvm_check_iopl(struct kvm_vcpu *vcpu); |
ec6d273d | 840 | |
e459e322 XG |
841 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
842 | { | |
843 | return gpa; | |
844 | } | |
845 | ||
ec6d273d ZX |
846 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
847 | { | |
848 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
849 | ||
850 | return (struct kvm_mmu_page *)page_private(page); | |
851 | } | |
852 | ||
d6e88aec | 853 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
854 | { |
855 | u16 ldt; | |
856 | asm("sldt %0" : "=g"(ldt)); | |
857 | return ldt; | |
858 | } | |
859 | ||
d6e88aec | 860 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
861 | { |
862 | asm("lldt %0" : : "rm"(sel)); | |
863 | } | |
ec6d273d | 864 | |
ec6d273d ZX |
865 | #ifdef CONFIG_X86_64 |
866 | static inline unsigned long read_msr(unsigned long msr) | |
867 | { | |
868 | u64 value; | |
869 | ||
870 | rdmsrl(msr, value); | |
871 | return value; | |
872 | } | |
873 | #endif | |
874 | ||
ec6d273d ZX |
875 | static inline u32 get_rdx_init_val(void) |
876 | { | |
877 | return 0x600; /* P6 family */ | |
878 | } | |
879 | ||
c1a5d4f9 AK |
880 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
881 | { | |
882 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
883 | } | |
884 | ||
ec6d273d ZX |
885 | #define TSS_IOPB_BASE_OFFSET 0x66 |
886 | #define TSS_BASE_SIZE 0x68 | |
887 | #define TSS_IOPB_SIZE (65536 / 8) | |
888 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
889 | #define RMODE_TSS_SIZE \ |
890 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 891 | |
37817f29 IE |
892 | enum { |
893 | TASK_SWITCH_CALL = 0, | |
894 | TASK_SWITCH_IRET = 1, | |
895 | TASK_SWITCH_JMP = 2, | |
896 | TASK_SWITCH_GATE = 3, | |
897 | }; | |
898 | ||
1371d904 | 899 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
900 | #define HF_HIF_MASK (1 << 1) |
901 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 902 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 903 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 904 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
1371d904 | 905 | |
4ecac3fd AK |
906 | /* |
907 | * Hardware virtualization extension instructions may fault if a | |
908 | * reboot turns off virtualization while processes are running. | |
909 | * Trap the fault and ignore the instruction if that happens. | |
910 | */ | |
b7c4145b AK |
911 | asmlinkage void kvm_spurious_fault(void); |
912 | extern bool kvm_rebooting; | |
4ecac3fd | 913 | |
5e520e62 | 914 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 915 | "666: " insn "\n\t" \ |
b7c4145b | 916 | "668: \n\t" \ |
18b13e54 | 917 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 918 | "667: \n\t" \ |
5e520e62 | 919 | cleanup_insn "\n\t" \ |
b7c4145b AK |
920 | "cmpb $0, kvm_rebooting \n\t" \ |
921 | "jne 668b \n\t" \ | |
8ceed347 | 922 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 923 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd AK |
924 | ".popsection \n\t" \ |
925 | ".pushsection __ex_table, \"a\" \n\t" \ | |
8ceed347 | 926 | _ASM_PTR " 666b, 667b \n\t" \ |
4ecac3fd AK |
927 | ".popsection" |
928 | ||
5e520e62 AK |
929 | #define __kvm_handle_fault_on_reboot(insn) \ |
930 | ____kvm_handle_fault_on_reboot(insn, "") | |
931 | ||
e930bffe AA |
932 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
933 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
934 | int kvm_age_hva(struct kvm *kvm, unsigned long hva); | |
8ee53820 | 935 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 936 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
82725b20 | 937 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu); |
a1b37100 GN |
938 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
939 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 940 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
e930bffe | 941 | |
18863bdd | 942 | void kvm_define_shared_msr(unsigned index, u32 msr); |
d5696725 | 943 | void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 944 | |
f92653ee JK |
945 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
946 | ||
af585b92 GN |
947 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
948 | struct kvm_async_pf *work); | |
949 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
950 | struct kvm_async_pf *work); | |
56028d08 GN |
951 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
952 | struct kvm_async_pf *work); | |
7c90705b | 953 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
954 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
955 | ||
db8fcefa AP |
956 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
957 | ||
f5132b01 GN |
958 | int kvm_is_in_guest(void); |
959 | ||
960 | void kvm_pmu_init(struct kvm_vcpu *vcpu); | |
961 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu); | |
962 | void kvm_pmu_reset(struct kvm_vcpu *vcpu); | |
963 | void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu); | |
964 | bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr); | |
965 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
966 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
967 | int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); | |
968 | void kvm_handle_pmu_event(struct kvm_vcpu *vcpu); | |
969 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu); | |
970 | ||
1965aae3 | 971 | #endif /* _ASM_X86_KVM_HOST_H */ |