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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
87276880 | 27 | #include <linux/irqbypass.h> |
5c919412 | 28 | #include <linux/hyperv.h> |
34c16eec | 29 | |
7d669f50 | 30 | #include <asm/apic.h> |
50d0a0f9 | 31 | #include <asm/pvclock-abi.h> |
e01a1b57 | 32 | #include <asm/desc.h> |
0bed3b56 | 33 | #include <asm/mtrr.h> |
9962d032 | 34 | #include <asm/msr-index.h> |
3ee89722 | 35 | #include <asm/asm.h> |
21ebbeda | 36 | #include <asm/kvm_page_track.h> |
e01a1b57 | 37 | |
682f732e | 38 | #define KVM_MAX_VCPUS 288 |
757883de | 39 | #define KVM_SOFT_MAX_VCPUS 240 |
af1bae54 | 40 | #define KVM_MAX_VCPU_ID 1023 |
1d4e7e3c | 41 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
42 | /* memory slots that are not exposed to userspace */ |
43 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 44 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 45 | |
69a9f69b | 46 | #define KVM_PIO_PAGE_OFFSET 1 |
542472b5 | 47 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
14ebda33 | 48 | #define KVM_HALT_POLL_NS_DEFAULT 400000 |
69a9f69b | 49 | |
8175e5b7 AG |
50 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
51 | ||
2860c4b1 PB |
52 | /* x86-specific vcpu->requests bit members */ |
53 | #define KVM_REQ_MIGRATE_TIMER 8 | |
54 | #define KVM_REQ_REPORT_TPR_ACCESS 9 | |
55 | #define KVM_REQ_TRIPLE_FAULT 10 | |
56 | #define KVM_REQ_MMU_SYNC 11 | |
57 | #define KVM_REQ_CLOCK_UPDATE 12 | |
58 | #define KVM_REQ_DEACTIVATE_FPU 13 | |
59 | #define KVM_REQ_EVENT 14 | |
60 | #define KVM_REQ_APF_HALT 15 | |
61 | #define KVM_REQ_STEAL_UPDATE 16 | |
62 | #define KVM_REQ_NMI 17 | |
63 | #define KVM_REQ_PMU 18 | |
64 | #define KVM_REQ_PMI 19 | |
65 | #define KVM_REQ_SMI 20 | |
66 | #define KVM_REQ_MASTERCLOCK_UPDATE 21 | |
67 | #define KVM_REQ_MCLOCK_INPROGRESS 22 | |
68 | #define KVM_REQ_SCAN_IOAPIC 23 | |
69 | #define KVM_REQ_GLOBAL_CLOCK_UPDATE 24 | |
70 | #define KVM_REQ_APIC_PAGE_RELOAD 25 | |
71 | #define KVM_REQ_HV_CRASH 26 | |
72 | #define KVM_REQ_IOAPIC_EOI_EXIT 27 | |
73 | #define KVM_REQ_HV_RESET 28 | |
74 | #define KVM_REQ_HV_EXIT 29 | |
75 | #define KVM_REQ_HV_STIMER 30 | |
76 | ||
cfec82cb JR |
77 | #define CR0_RESERVED_BITS \ |
78 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
79 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
80 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
81 | ||
346874c9 | 82 | #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL |
cfaa790a | 83 | #define CR3_PCID_INVD BIT_64(63) |
cfec82cb JR |
84 | #define CR4_RESERVED_BITS \ |
85 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
86 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 87 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 88 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
b9baba86 HH |
89 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP \ |
90 | | X86_CR4_PKE)) | |
cfec82cb JR |
91 | |
92 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
93 | ||
94 | ||
cd6e8f87 | 95 | |
cd6e8f87 | 96 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
97 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
98 | ||
cd6e8f87 ZX |
99 | #define UNMAPPED_GVA (~(gpa_t)0) |
100 | ||
ec04b260 | 101 | /* KVM Hugepage definitions for x86 */ |
04326caa | 102 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
103 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
104 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
105 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
106 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
107 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 108 | |
6d9d41e5 CD |
109 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
110 | { | |
111 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
112 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
113 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
114 | } | |
115 | ||
d657a98e ZX |
116 | #define KVM_PERMILLE_MMU_PAGES 20 |
117 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
114df303 | 118 | #define KVM_MMU_HASH_SHIFT 12 |
1ae0a13d | 119 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) |
d657a98e ZX |
120 | #define KVM_MIN_FREE_MMU_PAGES 5 |
121 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 122 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 123 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 124 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 125 | |
af585b92 GN |
126 | #define ASYNC_PF_PER_VCPU 64 |
127 | ||
5fdbf976 | 128 | enum kvm_reg { |
2b3ccfa0 ZX |
129 | VCPU_REGS_RAX = 0, |
130 | VCPU_REGS_RCX = 1, | |
131 | VCPU_REGS_RDX = 2, | |
132 | VCPU_REGS_RBX = 3, | |
133 | VCPU_REGS_RSP = 4, | |
134 | VCPU_REGS_RBP = 5, | |
135 | VCPU_REGS_RSI = 6, | |
136 | VCPU_REGS_RDI = 7, | |
137 | #ifdef CONFIG_X86_64 | |
138 | VCPU_REGS_R8 = 8, | |
139 | VCPU_REGS_R9 = 9, | |
140 | VCPU_REGS_R10 = 10, | |
141 | VCPU_REGS_R11 = 11, | |
142 | VCPU_REGS_R12 = 12, | |
143 | VCPU_REGS_R13 = 13, | |
144 | VCPU_REGS_R14 = 14, | |
145 | VCPU_REGS_R15 = 15, | |
146 | #endif | |
5fdbf976 | 147 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
148 | NR_VCPU_REGS |
149 | }; | |
150 | ||
6de4f3ad AK |
151 | enum kvm_reg_ex { |
152 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 153 | VCPU_EXREG_CR3, |
6de12732 | 154 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 155 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
156 | }; |
157 | ||
2b3ccfa0 | 158 | enum { |
81609e3e | 159 | VCPU_SREG_ES, |
2b3ccfa0 | 160 | VCPU_SREG_CS, |
81609e3e | 161 | VCPU_SREG_SS, |
2b3ccfa0 | 162 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
163 | VCPU_SREG_FS, |
164 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
165 | VCPU_SREG_TR, |
166 | VCPU_SREG_LDTR, | |
167 | }; | |
168 | ||
56e82318 | 169 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 170 | |
d657a98e ZX |
171 | #define KVM_NR_MEM_OBJS 40 |
172 | ||
42dbaa5a JK |
173 | #define KVM_NR_DB_REGS 4 |
174 | ||
175 | #define DR6_BD (1 << 13) | |
176 | #define DR6_BS (1 << 14) | |
6f43ed01 NA |
177 | #define DR6_RTM (1 << 16) |
178 | #define DR6_FIXED_1 0xfffe0ff0 | |
179 | #define DR6_INIT 0xffff0ff0 | |
180 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
181 | |
182 | #define DR7_BP_EN_MASK 0x000000ff | |
183 | #define DR7_GE (1 << 9) | |
184 | #define DR7_GD (1 << 13) | |
185 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 186 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 187 | |
c205fb7d NA |
188 | #define PFERR_PRESENT_BIT 0 |
189 | #define PFERR_WRITE_BIT 1 | |
190 | #define PFERR_USER_BIT 2 | |
191 | #define PFERR_RSVD_BIT 3 | |
192 | #define PFERR_FETCH_BIT 4 | |
be94f6b7 | 193 | #define PFERR_PK_BIT 5 |
14727754 TL |
194 | #define PFERR_GUEST_FINAL_BIT 32 |
195 | #define PFERR_GUEST_PAGE_BIT 33 | |
c205fb7d NA |
196 | |
197 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
198 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
199 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
200 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
201 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
be94f6b7 | 202 | #define PFERR_PK_MASK (1U << PFERR_PK_BIT) |
14727754 TL |
203 | #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) |
204 | #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) | |
205 | ||
206 | #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ | |
207 | PFERR_USER_MASK | \ | |
208 | PFERR_WRITE_MASK | \ | |
209 | PFERR_PRESENT_MASK) | |
c205fb7d | 210 | |
37f0e8fe JS |
211 | /* |
212 | * The mask used to denote special SPTEs, which can be either MMIO SPTEs or | |
213 | * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting | |
214 | * with the SVE bit in EPT PTEs. | |
215 | */ | |
216 | #define SPTE_SPECIAL_MASK (1ULL << 62) | |
217 | ||
41383771 GN |
218 | /* apic attention bits */ |
219 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
220 | /* |
221 | * The following bit is set with PV-EOI, unset on EOI. | |
222 | * We detect PV-EOI changes by guest by comparing | |
223 | * this bit with PV-EOI in guest memory. | |
224 | * See the implementation in apic_update_pv_eoi. | |
225 | */ | |
226 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 227 | |
d84f1e07 FW |
228 | struct kvm_kernel_irq_routing_entry; |
229 | ||
d657a98e ZX |
230 | /* |
231 | * We don't want allocation failures within the mmu code, so we preallocate | |
232 | * enough memory for a single page fault in a cache. | |
233 | */ | |
234 | struct kvm_mmu_memory_cache { | |
235 | int nobjs; | |
236 | void *objects[KVM_NR_MEM_OBJS]; | |
237 | }; | |
238 | ||
21ebbeda XG |
239 | /* |
240 | * the pages used as guest page table on soft mmu are tracked by | |
241 | * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used | |
242 | * by indirect shadow page can not be more than 15 bits. | |
243 | * | |
244 | * Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access, | |
245 | * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. | |
246 | */ | |
d657a98e ZX |
247 | union kvm_mmu_page_role { |
248 | unsigned word; | |
249 | struct { | |
7d76b4d3 | 250 | unsigned level:4; |
5b7e0102 | 251 | unsigned cr4_pae:1; |
7d76b4d3 | 252 | unsigned quadrant:2; |
f6e2c02b | 253 | unsigned direct:1; |
7d76b4d3 | 254 | unsigned access:3; |
2e53d63a | 255 | unsigned invalid:1; |
9645bb56 | 256 | unsigned nxe:1; |
3dbe1415 | 257 | unsigned cr0_wp:1; |
411c588d | 258 | unsigned smep_andnot_wp:1; |
0be0226f | 259 | unsigned smap_andnot_wp:1; |
699023e2 PB |
260 | unsigned :8; |
261 | ||
262 | /* | |
263 | * This is left at the top of the word so that | |
264 | * kvm_memslots_for_spte_role can extract it with a | |
265 | * simple shift. While there is room, give it a whole | |
266 | * byte so it is also faster to load it from memory. | |
267 | */ | |
268 | unsigned smm:8; | |
d657a98e ZX |
269 | }; |
270 | }; | |
271 | ||
018aabb5 TY |
272 | struct kvm_rmap_head { |
273 | unsigned long val; | |
274 | }; | |
275 | ||
d657a98e ZX |
276 | struct kvm_mmu_page { |
277 | struct list_head link; | |
278 | struct hlist_node hash_link; | |
279 | ||
280 | /* | |
281 | * The following two entries are used to key the shadow page in the | |
282 | * hash table. | |
283 | */ | |
284 | gfn_t gfn; | |
285 | union kvm_mmu_page_role role; | |
286 | ||
287 | u64 *spt; | |
288 | /* hold the gfn of each spte inside spt */ | |
289 | gfn_t *gfns; | |
4731d4c7 | 290 | bool unsync; |
0571d366 | 291 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 292 | unsigned int unsync_children; |
018aabb5 | 293 | struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ |
f6f8adee XG |
294 | |
295 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 296 | unsigned long mmu_valid_gen; |
f6f8adee | 297 | |
0074ff63 | 298 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
299 | |
300 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
301 | /* |
302 | * Used out of the mmu-lock to avoid reading spte values while an | |
303 | * update is in progress; see the comments in __get_spte_lockless(). | |
304 | */ | |
c2a2ac2b XG |
305 | int clear_spte_count; |
306 | #endif | |
307 | ||
0cbf8e43 | 308 | /* Number of writes since the last time traversal visited this page. */ |
e5691a81 | 309 | atomic_t write_flooding_count; |
d657a98e ZX |
310 | }; |
311 | ||
1c08364c AK |
312 | struct kvm_pio_request { |
313 | unsigned long count; | |
1c08364c AK |
314 | int in; |
315 | int port; | |
316 | int size; | |
1c08364c AK |
317 | }; |
318 | ||
a0a64f50 XG |
319 | struct rsvd_bits_validate { |
320 | u64 rsvd_bits_mask[2][4]; | |
321 | u64 bad_mt_xwr; | |
322 | }; | |
323 | ||
d657a98e ZX |
324 | /* |
325 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
326 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
327 | * mode. | |
328 | */ | |
329 | struct kvm_mmu { | |
f43addd4 | 330 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 331 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 332 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
333 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
334 | bool prefault); | |
6389ee94 AK |
335 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
336 | struct x86_exception *fault); | |
1871c602 | 337 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 338 | struct x86_exception *exception); |
54987b7a PB |
339 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
340 | struct x86_exception *exception); | |
e8bc217a | 341 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 342 | struct kvm_mmu_page *sp); |
a7052897 | 343 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 344 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 345 | u64 *spte, const void *pte); |
d657a98e ZX |
346 | hpa_t root_hpa; |
347 | int root_level; | |
348 | int shadow_root_level; | |
a770f6f2 | 349 | union kvm_mmu_page_role base_role; |
c5a78f2b | 350 | bool direct_map; |
d657a98e | 351 | |
97d64b78 AK |
352 | /* |
353 | * Bitmap; bit set = permission fault | |
354 | * Byte index: page fault error code [4:1] | |
355 | * Bit index: pte permissions in ACC_* format | |
356 | */ | |
357 | u8 permissions[16]; | |
358 | ||
2d344105 HH |
359 | /* |
360 | * The pkru_mask indicates if protection key checks are needed. It | |
361 | * consists of 16 domains indexed by page fault error code bits [4:1], | |
362 | * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. | |
363 | * Each domain has 2 bits which are ANDed with AD and WD from PKRU. | |
364 | */ | |
365 | u32 pkru_mask; | |
366 | ||
d657a98e | 367 | u64 *pae_root; |
81407ca5 | 368 | u64 *lm_root; |
c258b62b XG |
369 | |
370 | /* | |
371 | * check zero bits on shadow page table entries, these | |
372 | * bits include not only hardware reserved bits but also | |
373 | * the bits spte never used. | |
374 | */ | |
375 | struct rsvd_bits_validate shadow_zero_check; | |
376 | ||
a0a64f50 | 377 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 378 | |
6bb69c9b PB |
379 | /* Can have large pages at levels 2..last_nonleaf_level-1. */ |
380 | u8 last_nonleaf_level; | |
6fd01b71 | 381 | |
2d48a985 JR |
382 | bool nx; |
383 | ||
ff03a073 | 384 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
385 | }; |
386 | ||
f5132b01 GN |
387 | enum pmc_type { |
388 | KVM_PMC_GP = 0, | |
389 | KVM_PMC_FIXED, | |
390 | }; | |
391 | ||
392 | struct kvm_pmc { | |
393 | enum pmc_type type; | |
394 | u8 idx; | |
395 | u64 counter; | |
396 | u64 eventsel; | |
397 | struct perf_event *perf_event; | |
398 | struct kvm_vcpu *vcpu; | |
399 | }; | |
400 | ||
401 | struct kvm_pmu { | |
402 | unsigned nr_arch_gp_counters; | |
403 | unsigned nr_arch_fixed_counters; | |
404 | unsigned available_event_types; | |
405 | u64 fixed_ctr_ctrl; | |
406 | u64 global_ctrl; | |
407 | u64 global_status; | |
408 | u64 global_ovf_ctrl; | |
409 | u64 counter_bitmask[2]; | |
410 | u64 global_ctrl_mask; | |
103af0a9 | 411 | u64 reserved_bits; |
f5132b01 | 412 | u8 version; |
15c7ad51 RR |
413 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
414 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
415 | struct irq_work irq_work; |
416 | u64 reprogram_pmi; | |
417 | }; | |
418 | ||
25462f7f WH |
419 | struct kvm_pmu_ops; |
420 | ||
360b948d PB |
421 | enum { |
422 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 423 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 424 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
425 | }; |
426 | ||
86fd5270 XG |
427 | struct kvm_mtrr_range { |
428 | u64 base; | |
429 | u64 mask; | |
19efffa2 | 430 | struct list_head node; |
86fd5270 XG |
431 | }; |
432 | ||
70109e7d | 433 | struct kvm_mtrr { |
86fd5270 | 434 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 435 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 436 | u64 deftype; |
19efffa2 XG |
437 | |
438 | struct list_head head; | |
70109e7d XG |
439 | }; |
440 | ||
1f4b34f8 AS |
441 | /* Hyper-V SynIC timer */ |
442 | struct kvm_vcpu_hv_stimer { | |
443 | struct hrtimer timer; | |
444 | int index; | |
445 | u64 config; | |
446 | u64 count; | |
447 | u64 exp_time; | |
448 | struct hv_message msg; | |
449 | bool msg_pending; | |
450 | }; | |
451 | ||
5c919412 AS |
452 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
453 | struct kvm_vcpu_hv_synic { | |
454 | u64 version; | |
455 | u64 control; | |
456 | u64 msg_page; | |
457 | u64 evt_page; | |
458 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
459 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
460 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
461 | DECLARE_BITMAP(vec_bitmap, 256); | |
462 | bool active; | |
463 | }; | |
464 | ||
e83d5887 AS |
465 | /* Hyper-V per vcpu emulation context */ |
466 | struct kvm_vcpu_hv { | |
467 | u64 hv_vapic; | |
9eec50b8 | 468 | s64 runtime_offset; |
5c919412 | 469 | struct kvm_vcpu_hv_synic synic; |
db397571 | 470 | struct kvm_hyperv_exit exit; |
1f4b34f8 AS |
471 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; |
472 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
e83d5887 AS |
473 | }; |
474 | ||
ad312c7c | 475 | struct kvm_vcpu_arch { |
5fdbf976 MT |
476 | /* |
477 | * rip and regs accesses must go through | |
478 | * kvm_{register,rip}_{read,write} functions. | |
479 | */ | |
480 | unsigned long regs[NR_VCPU_REGS]; | |
481 | u32 regs_avail; | |
482 | u32 regs_dirty; | |
34c16eec ZX |
483 | |
484 | unsigned long cr0; | |
e8467fda | 485 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
486 | unsigned long cr2; |
487 | unsigned long cr3; | |
488 | unsigned long cr4; | |
fc78f519 | 489 | unsigned long cr4_guest_owned_bits; |
34c16eec | 490 | unsigned long cr8; |
1371d904 | 491 | u32 hflags; |
f6801dff | 492 | u64 efer; |
34c16eec ZX |
493 | u64 apic_base; |
494 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 495 | bool apicv_active; |
6308630b | 496 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 497 | unsigned long apic_attention; |
e1035715 | 498 | int32_t apic_arb_prio; |
34c16eec | 499 | int mp_state; |
34c16eec | 500 | u64 ia32_misc_enable_msr; |
64d60670 | 501 | u64 smbase; |
b209749f | 502 | bool tpr_access_reporting; |
20300099 | 503 | u64 ia32_xss; |
34c16eec | 504 | |
14dfe855 JR |
505 | /* |
506 | * Paging state of the vcpu | |
507 | * | |
508 | * If the vcpu runs in guest mode with two level paging this still saves | |
509 | * the paging mode of the l1 guest. This context is always used to | |
510 | * handle faults. | |
511 | */ | |
34c16eec | 512 | struct kvm_mmu mmu; |
8df25a32 | 513 | |
6539e738 JR |
514 | /* |
515 | * Paging state of an L2 guest (used for nested npt) | |
516 | * | |
517 | * This context will save all necessary information to walk page tables | |
518 | * of the an L2 guest. This context is only initialized for page table | |
519 | * walking and not for faulting since we never handle l2 page faults on | |
520 | * the host. | |
521 | */ | |
522 | struct kvm_mmu nested_mmu; | |
523 | ||
14dfe855 JR |
524 | /* |
525 | * Pointer to the mmu context currently used for | |
526 | * gva_to_gpa translations. | |
527 | */ | |
528 | struct kvm_mmu *walk_mmu; | |
529 | ||
53c07b18 | 530 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
531 | struct kvm_mmu_memory_cache mmu_page_cache; |
532 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
533 | ||
98918833 | 534 | struct fpu guest_fpu; |
2acf923e | 535 | u64 xcr0; |
d7876f1b | 536 | u64 guest_supported_xcr0; |
4344ee98 | 537 | u32 guest_xstate_size; |
34c16eec | 538 | |
34c16eec ZX |
539 | struct kvm_pio_request pio; |
540 | void *pio_data; | |
541 | ||
66fd3f7f GN |
542 | u8 event_exit_inst_len; |
543 | ||
298101da AK |
544 | struct kvm_queued_exception { |
545 | bool pending; | |
546 | bool has_error_code; | |
ce7ddec4 | 547 | bool reinject; |
298101da AK |
548 | u8 nr; |
549 | u32 error_code; | |
550 | } exception; | |
551 | ||
937a7eae AK |
552 | struct kvm_queued_interrupt { |
553 | bool pending; | |
66fd3f7f | 554 | bool soft; |
937a7eae AK |
555 | u8 nr; |
556 | } interrupt; | |
557 | ||
34c16eec ZX |
558 | int halt_request; /* real mode on Intel only */ |
559 | ||
560 | int cpuid_nent; | |
07716717 | 561 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
562 | |
563 | int maxphyaddr; | |
564 | ||
34c16eec ZX |
565 | /* emulate context */ |
566 | ||
567 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
568 | bool emulate_regs_need_sync_to_vcpu; |
569 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 570 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
571 | |
572 | gpa_t time; | |
50d0a0f9 | 573 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 574 | unsigned int hw_tsc_khz; |
0b79459b AH |
575 | struct gfn_to_hva_cache pv_time; |
576 | bool pv_time_enabled; | |
51d59c6b MT |
577 | /* set guest stopped flag in pvclock flags field */ |
578 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
579 | |
580 | struct { | |
581 | u64 msr_val; | |
582 | u64 last_steal; | |
c9aaa895 GC |
583 | struct gfn_to_hva_cache stime; |
584 | struct kvm_steal_time steal; | |
585 | } st; | |
586 | ||
a545ab6a | 587 | u64 tsc_offset; |
1d5f066e | 588 | u64 last_guest_tsc; |
6f526ec5 | 589 | u64 last_host_tsc; |
0dd6a6ed | 590 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
591 | u64 this_tsc_nsec; |
592 | u64 this_tsc_write; | |
0d3da0d2 | 593 | u64 this_tsc_generation; |
c285545f | 594 | bool tsc_catchup; |
cc578287 ZA |
595 | bool tsc_always_catchup; |
596 | s8 virtual_tsc_shift; | |
597 | u32 virtual_tsc_mult; | |
598 | u32 virtual_tsc_khz; | |
ba904635 | 599 | s64 ia32_tsc_adjust_msr; |
ad721883 | 600 | u64 tsc_scaling_ratio; |
3419ffc8 | 601 | |
7460fb4a AK |
602 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
603 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
604 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 605 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 606 | |
70109e7d | 607 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 608 | u64 pat; |
42dbaa5a | 609 | |
360b948d | 610 | unsigned switch_db_regs; |
42dbaa5a JK |
611 | unsigned long db[KVM_NR_DB_REGS]; |
612 | unsigned long dr6; | |
613 | unsigned long dr7; | |
614 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 615 | unsigned long guest_debug_dr7; |
890ca9ae HY |
616 | |
617 | u64 mcg_cap; | |
618 | u64 mcg_status; | |
619 | u64 mcg_ctl; | |
c45dcc71 | 620 | u64 mcg_ext_ctl; |
890ca9ae | 621 | u64 *mce_banks; |
94fe45da | 622 | |
bebb106a XG |
623 | /* Cache MMIO info */ |
624 | u64 mmio_gva; | |
625 | unsigned access; | |
626 | gfn_t mmio_gfn; | |
56f17dd3 | 627 | u64 mmio_gen; |
bebb106a | 628 | |
f5132b01 GN |
629 | struct kvm_pmu pmu; |
630 | ||
94fe45da | 631 | /* used for guest single stepping over the given code position */ |
94fe45da | 632 | unsigned long singlestep_rip; |
f92653ee | 633 | |
e83d5887 | 634 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
635 | |
636 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 637 | |
1cb3f3ae XG |
638 | unsigned long last_retry_eip; |
639 | unsigned long last_retry_addr; | |
640 | ||
af585b92 GN |
641 | struct { |
642 | bool halted; | |
643 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
644 | struct gfn_to_hva_cache data; |
645 | u64 msr_val; | |
7c90705b | 646 | u32 id; |
6adba527 | 647 | bool send_user_only; |
af585b92 | 648 | } apf; |
2b036c6b BO |
649 | |
650 | /* OSVW MSRs (AMD only) */ | |
651 | struct { | |
652 | u64 length; | |
653 | u64 status; | |
654 | } osvw; | |
ae7a2a3f MT |
655 | |
656 | struct { | |
657 | u64 msr_val; | |
658 | struct gfn_to_hva_cache data; | |
659 | } pv_eoi; | |
93c05d3e XG |
660 | |
661 | /* | |
662 | * Indicate whether the access faults on its page table in guest | |
663 | * which is set when fix page fault and used to detect unhandeable | |
664 | * instruction. | |
665 | */ | |
666 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
667 | |
668 | /* set at EPT violation at this point */ | |
669 | unsigned long exit_qualification; | |
6aef266c SV |
670 | |
671 | /* pv related host specific info */ | |
672 | struct { | |
673 | bool pv_unhalted; | |
674 | } pv; | |
7543a635 SR |
675 | |
676 | int pending_ioapic_eoi; | |
1c1a9ce9 | 677 | int pending_external_vector; |
34c16eec ZX |
678 | }; |
679 | ||
db3fe4eb | 680 | struct kvm_lpage_info { |
92f94f1e | 681 | int disallow_lpage; |
db3fe4eb TY |
682 | }; |
683 | ||
684 | struct kvm_arch_memory_slot { | |
018aabb5 | 685 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb | 686 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
21ebbeda | 687 | unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; |
db3fe4eb TY |
688 | }; |
689 | ||
3548a259 RK |
690 | /* |
691 | * We use as the mode the number of bits allocated in the LDR for the | |
692 | * logical processor ID. It happens that these are all powers of two. | |
693 | * This makes it is very easy to detect cases where the APICs are | |
694 | * configured for multiple modes; in that case, we cannot use the map and | |
695 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
696 | */ | |
697 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
698 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
699 | #define KVM_APIC_MODE_X2APIC 16 | |
700 | ||
1e08ec4a GN |
701 | struct kvm_apic_map { |
702 | struct rcu_head rcu; | |
3548a259 | 703 | u8 mode; |
0ca52e7b | 704 | u32 max_apic_id; |
e45115b6 RK |
705 | union { |
706 | struct kvm_lapic *xapic_flat_map[8]; | |
707 | struct kvm_lapic *xapic_cluster_map[16][4]; | |
708 | }; | |
0ca52e7b | 709 | struct kvm_lapic *phys_map[]; |
1e08ec4a GN |
710 | }; |
711 | ||
e83d5887 AS |
712 | /* Hyper-V emulation context */ |
713 | struct kvm_hv { | |
3f5ad8be | 714 | struct mutex hv_lock; |
e83d5887 AS |
715 | u64 hv_guest_os_id; |
716 | u64 hv_hypercall; | |
717 | u64 hv_tsc_page; | |
e7d9513b AS |
718 | |
719 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
720 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
721 | u64 hv_crash_ctl; | |
095cf55d PB |
722 | |
723 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
e83d5887 AS |
724 | }; |
725 | ||
49776faf RK |
726 | enum kvm_irqchip_mode { |
727 | KVM_IRQCHIP_NONE, | |
728 | KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ | |
729 | KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ | |
730 | }; | |
731 | ||
fef9cce0 | 732 | struct kvm_arch { |
49d5ca26 | 733 | unsigned int n_used_mmu_pages; |
f05e70ac | 734 | unsigned int n_requested_mmu_pages; |
39de71ec | 735 | unsigned int n_max_mmu_pages; |
332b207d | 736 | unsigned int indirect_shadow_pages; |
5304b8d3 | 737 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
738 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
739 | /* | |
740 | * Hash table of struct kvm_mmu_page. | |
741 | */ | |
742 | struct list_head active_mmu_pages; | |
365c8868 | 743 | struct list_head zapped_obsolete_pages; |
13d268ca | 744 | struct kvm_page_track_notifier_node mmu_sp_tracker; |
0eb05bf2 | 745 | struct kvm_page_track_notifier_head track_notifier_head; |
365c8868 | 746 | |
4d5c5d0f | 747 | struct list_head assigned_dev_head; |
19de40a8 | 748 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 749 | bool iommu_noncoherent; |
e0f0bbc5 AW |
750 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
751 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
752 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
753 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
754 | struct kvm_pic *vpic; |
755 | struct kvm_ioapic *vioapic; | |
7837699f | 756 | struct kvm_pit *vpit; |
42720138 | 757 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
758 | struct mutex apic_map_lock; |
759 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 760 | |
bfc6d222 | 761 | unsigned int tss_addr; |
c24ae0dc | 762 | bool apic_access_page_done; |
18068523 GOC |
763 | |
764 | gpa_t wall_clock; | |
b7ebfb05 | 765 | |
b7ebfb05 | 766 | bool ept_identity_pagetable_done; |
b927a3ce | 767 | gpa_t ept_identity_map_addr; |
5550af4d SY |
768 | |
769 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 770 | s64 kvmclock_offset; |
038f8c11 | 771 | raw_spinlock_t tsc_write_lock; |
f38e098f | 772 | u64 last_tsc_nsec; |
f38e098f | 773 | u64 last_tsc_write; |
5d3cb0f6 | 774 | u32 last_tsc_khz; |
e26101b1 ZA |
775 | u64 cur_tsc_nsec; |
776 | u64 cur_tsc_write; | |
777 | u64 cur_tsc_offset; | |
0d3da0d2 | 778 | u64 cur_tsc_generation; |
b48aa97e | 779 | int nr_vcpus_matched_tsc; |
ffde22ac | 780 | |
d828199e MT |
781 | spinlock_t pvclock_gtod_sync_lock; |
782 | bool use_master_clock; | |
783 | u64 master_kernel_ns; | |
a5a1d1c2 | 784 | u64 master_cycle_now; |
7e44e449 | 785 | struct delayed_work kvmclock_update_work; |
332967a3 | 786 | struct delayed_work kvmclock_sync_work; |
d828199e | 787 | |
ffde22ac | 788 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 789 | |
6ef768fa PB |
790 | /* reads protected by irq_srcu, writes by irq_lock */ |
791 | struct hlist_head mask_notifier_list; | |
792 | ||
e83d5887 | 793 | struct kvm_hv hyperv; |
b034cf01 XG |
794 | |
795 | #ifdef CONFIG_KVM_MMU_AUDIT | |
796 | int audit_point; | |
797 | #endif | |
54750f2c MT |
798 | |
799 | bool boot_vcpu_runs_old_kvmclock; | |
d71ba788 | 800 | u32 bsp_vcpu_id; |
90de4a18 NA |
801 | |
802 | u64 disabled_quirks; | |
49df6397 | 803 | |
49776faf | 804 | enum kvm_irqchip_mode irqchip_mode; |
b053b2ae | 805 | u8 nr_reserved_ioapic_pins; |
52004014 FW |
806 | |
807 | bool disabled_lapic_found; | |
44a95dae SS |
808 | |
809 | /* Struct members for AVIC */ | |
5ea11f2b | 810 | u32 avic_vm_id; |
18f40c53 | 811 | u32 ldr_mode; |
44a95dae SS |
812 | struct page *avic_logical_id_table_page; |
813 | struct page *avic_physical_id_table_page; | |
5881f737 | 814 | struct hlist_node hnode; |
37131313 RK |
815 | |
816 | bool x2apic_format; | |
c519265f | 817 | bool x2apic_broadcast_quirk_disabled; |
d69fb81f ZX |
818 | }; |
819 | ||
0711456c | 820 | struct kvm_vm_stat { |
8a7e75d4 SJS |
821 | ulong mmu_shadow_zapped; |
822 | ulong mmu_pte_write; | |
823 | ulong mmu_pte_updated; | |
824 | ulong mmu_pde_zapped; | |
825 | ulong mmu_flooded; | |
826 | ulong mmu_recycled; | |
827 | ulong mmu_cache_miss; | |
828 | ulong mmu_unsync; | |
829 | ulong remote_tlb_flush; | |
830 | ulong lpages; | |
f3414bc7 | 831 | ulong max_mmu_page_hash_collisions; |
0711456c ZX |
832 | }; |
833 | ||
77b4c255 | 834 | struct kvm_vcpu_stat { |
8a7e75d4 SJS |
835 | u64 pf_fixed; |
836 | u64 pf_guest; | |
837 | u64 tlb_flush; | |
838 | u64 invlpg; | |
839 | ||
840 | u64 exits; | |
841 | u64 io_exits; | |
842 | u64 mmio_exits; | |
843 | u64 signal_exits; | |
844 | u64 irq_window_exits; | |
845 | u64 nmi_window_exits; | |
846 | u64 halt_exits; | |
847 | u64 halt_successful_poll; | |
848 | u64 halt_attempted_poll; | |
849 | u64 halt_poll_invalid; | |
850 | u64 halt_wakeup; | |
851 | u64 request_irq_exits; | |
852 | u64 irq_exits; | |
853 | u64 host_state_reload; | |
854 | u64 efer_reload; | |
855 | u64 fpu_reload; | |
856 | u64 insn_emulation; | |
857 | u64 insn_emulation_fail; | |
858 | u64 hypercalls; | |
859 | u64 irq_injections; | |
860 | u64 nmi_injections; | |
77b4c255 | 861 | }; |
ad312c7c | 862 | |
8a76d7f2 JR |
863 | struct x86_instruction_info; |
864 | ||
8fe8ab46 WA |
865 | struct msr_data { |
866 | bool host_initiated; | |
867 | u32 index; | |
868 | u64 data; | |
869 | }; | |
870 | ||
cb5281a5 PB |
871 | struct kvm_lapic_irq { |
872 | u32 vector; | |
b7cb2231 PB |
873 | u16 delivery_mode; |
874 | u16 dest_mode; | |
875 | bool level; | |
876 | u16 trig_mode; | |
cb5281a5 PB |
877 | u32 shorthand; |
878 | u32 dest_id; | |
93bbf0b8 | 879 | bool msi_redir_hint; |
cb5281a5 PB |
880 | }; |
881 | ||
ea4a5ff8 ZX |
882 | struct kvm_x86_ops { |
883 | int (*cpu_has_kvm_support)(void); /* __init */ | |
884 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
885 | int (*hardware_enable)(void); |
886 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
887 | void (*check_processor_compatibility)(void *rtn); |
888 | int (*hardware_setup)(void); /* __init */ | |
889 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 890 | bool (*cpu_has_accelerated_tpr)(void); |
6d396b55 | 891 | bool (*cpu_has_high_real_mode_segbase)(void); |
0e851880 | 892 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 893 | |
03543133 SS |
894 | int (*vm_init)(struct kvm *kvm); |
895 | void (*vm_destroy)(struct kvm *kvm); | |
896 | ||
ea4a5ff8 ZX |
897 | /* Create, but do not attach this VCPU */ |
898 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
899 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 900 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
901 | |
902 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
903 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
904 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 905 | |
a96036b8 | 906 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 907 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 908 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
909 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
910 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
911 | struct kvm_segment *var, int seg); | |
2e4d2653 | 912 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
913 | void (*set_segment)(struct kvm_vcpu *vcpu, |
914 | struct kvm_segment *var, int seg); | |
915 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 916 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 917 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
918 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
919 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
920 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 921 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 922 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
923 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
924 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
925 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
926 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
927 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
928 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 929 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 930 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 931 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
932 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
933 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
be94f6b7 | 934 | u32 (*get_pkru)(struct kvm_vcpu *vcpu); |
0fdd74f7 | 935 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 936 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
937 | |
938 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 939 | |
851ba692 AK |
940 | void (*run)(struct kvm_vcpu *vcpu); |
941 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 942 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 943 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 944 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
945 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
946 | unsigned char *hypercall_addr); | |
66fd3f7f | 947 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 948 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 949 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
950 | bool has_error_code, u32 error_code, |
951 | bool reinject); | |
b463a6f7 | 952 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 953 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 954 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
955 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
956 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
957 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
958 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 959 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
d62caabb AS |
960 | bool (*get_enable_apicv)(void); |
961 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); | |
c7c9c56c | 962 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
67c9dddc | 963 | void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); |
6308630b | 964 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d14695f | 965 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
4256f43f | 966 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d YZ |
967 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
968 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 969 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 970 | int (*get_tdp_level)(void); |
4b12f0de | 971 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 972 | int (*get_lpage_level)(void); |
4e47c7a6 | 973 | bool (*rdtscp_supported)(void); |
ad756a16 | 974 | bool (*invpcid_supported)(void); |
344f414f | 975 | |
1c97f0a0 JR |
976 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
977 | ||
d4330ef2 JR |
978 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
979 | ||
f5f48ee1 SY |
980 | bool (*has_wbinvd_exit)(void); |
981 | ||
99e3e30a ZA |
982 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
983 | ||
586f9607 | 984 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
985 | |
986 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
987 | struct x86_instruction_info *info, | |
988 | enum x86_intercept_stage stage); | |
a547c6db | 989 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 990 | bool (*mpx_supported)(void); |
55412b2e | 991 | bool (*xsaves_supported)(void); |
b6b8a145 JK |
992 | |
993 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ae97a3b8 RK |
994 | |
995 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
996 | |
997 | /* | |
998 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
999 | * be valid if the specific arch has hardware-accelerated dirty logging | |
1000 | * mechanism. Currently only for PML on VMX. | |
1001 | * | |
1002 | * - slot_enable_log_dirty: | |
1003 | * called when enabling log dirty mode for the slot. | |
1004 | * - slot_disable_log_dirty: | |
1005 | * called when disabling log dirty mode for the slot. | |
1006 | * also called when slot is created with log dirty disabled. | |
1007 | * - flush_log_dirty: | |
1008 | * called before reporting dirty_bitmap to userspace. | |
1009 | * - enable_log_dirty_pt_masked: | |
1010 | * called when reenabling log dirty for the GFNs in the mask after | |
1011 | * corresponding bits are cleared in slot->dirty_bitmap. | |
1012 | */ | |
1013 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
1014 | struct kvm_memory_slot *slot); | |
1015 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
1016 | struct kvm_memory_slot *slot); | |
1017 | void (*flush_log_dirty)(struct kvm *kvm); | |
1018 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
1019 | struct kvm_memory_slot *slot, | |
1020 | gfn_t offset, unsigned long mask); | |
25462f7f WH |
1021 | /* pmu operations of sub-arch */ |
1022 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 | 1023 | |
bf9f6ac8 FW |
1024 | /* |
1025 | * Architecture specific hooks for vCPU blocking due to | |
1026 | * HLT instruction. | |
1027 | * Returns for .pre_block(): | |
1028 | * - 0 means continue to block the vCPU. | |
1029 | * - 1 means we cannot block the vCPU since some event | |
1030 | * happens during this period, such as, 'ON' bit in | |
1031 | * posted-interrupts descriptor is set. | |
1032 | */ | |
1033 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
1034 | void (*post_block)(struct kvm_vcpu *vcpu); | |
d1ed092f SS |
1035 | |
1036 | void (*vcpu_blocking)(struct kvm_vcpu *vcpu); | |
1037 | void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); | |
1038 | ||
efc64404 FW |
1039 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
1040 | uint32_t guest_irq, bool set); | |
be8ca170 | 1041 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); |
ce7a058a YJ |
1042 | |
1043 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc); | |
1044 | void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); | |
c45dcc71 AR |
1045 | |
1046 | void (*setup_mce)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 ZX |
1047 | }; |
1048 | ||
af585b92 | 1049 | struct kvm_arch_async_pf { |
7c90705b | 1050 | u32 token; |
af585b92 | 1051 | gfn_t gfn; |
fb67e14f | 1052 | unsigned long cr3; |
c4806acd | 1053 | bool direct_map; |
af585b92 GN |
1054 | }; |
1055 | ||
97896d04 ZX |
1056 | extern struct kvm_x86_ops *kvm_x86_ops; |
1057 | ||
54f1585a ZX |
1058 | int kvm_mmu_module_init(void); |
1059 | void kvm_mmu_module_exit(void); | |
1060 | ||
1061 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
1062 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 1063 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
13d268ca XG |
1064 | void kvm_mmu_init_vm(struct kvm *kvm); |
1065 | void kvm_mmu_uninit_vm(struct kvm *kvm); | |
7b52345e | 1066 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
ffb128c8 | 1067 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask); |
54f1585a | 1068 | |
8a3c1a33 | 1069 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
1070 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
1071 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 1072 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 1073 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
1074 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
1075 | struct kvm_memory_slot *memslot); | |
1076 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
1077 | struct kvm_memory_slot *memslot); | |
1078 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
1079 | struct kvm_memory_slot *memslot); | |
1080 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1081 | struct kvm_memory_slot *slot, | |
1082 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 1083 | void kvm_mmu_zap_all(struct kvm *kvm); |
54bf36aa | 1084 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); |
3ad82a7e | 1085 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
1086 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
1087 | ||
ff03a073 | 1088 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
9ed38ffa | 1089 | bool pdptrs_changed(struct kvm_vcpu *vcpu); |
cc4b6871 | 1090 | |
3200f405 | 1091 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 1092 | const void *val, int bytes); |
2f333bcb | 1093 | |
6ef768fa PB |
1094 | struct kvm_irq_mask_notifier { |
1095 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
1096 | int irq; | |
1097 | struct hlist_node link; | |
1098 | }; | |
1099 | ||
1100 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1101 | struct kvm_irq_mask_notifier *kimn); | |
1102 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1103 | struct kvm_irq_mask_notifier *kimn); | |
1104 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1105 | bool mask); | |
1106 | ||
2f333bcb | 1107 | extern bool tdp_enabled; |
9f811285 | 1108 | |
a3e06bbe LJ |
1109 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
1110 | ||
92a1f12d JR |
1111 | /* control of guest tsc rate supported? */ |
1112 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
1113 | /* maximum supported tsc_khz for guests */ |
1114 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
1115 | /* number of bits of the fractional part of the TSC scaling ratio */ |
1116 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1117 | /* maximum allowed value of TSC scaling ratio */ | |
1118 | extern u64 kvm_max_tsc_scaling_ratio; | |
64672c95 YJ |
1119 | /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ |
1120 | extern u64 kvm_default_tsc_scaling_ratio; | |
92a1f12d | 1121 | |
c45dcc71 | 1122 | extern u64 kvm_mce_cap_supported; |
92a1f12d | 1123 | |
54f1585a | 1124 | enum emulation_result { |
ac0a48c3 PB |
1125 | EMULATE_DONE, /* no further processing */ |
1126 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
1127 | EMULATE_FAIL, /* can't emulate this instruction */ |
1128 | }; | |
1129 | ||
571008da SY |
1130 | #define EMULTYPE_NO_DECODE (1 << 0) |
1131 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1132 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 1133 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 1134 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
1135 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
1136 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
1137 | |
1138 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
1139 | int emulation_type) | |
1140 | { | |
dc25e89e | 1141 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
1142 | } |
1143 | ||
f2b4b7dd | 1144 | void kvm_enable_efer_bits(u64); |
384bb783 | 1145 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 1146 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1147 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
1148 | |
1149 | struct x86_emulate_ctxt; | |
1150 | ||
cf8f70bf | 1151 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
8370c3d0 | 1152 | int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port); |
6a908b62 | 1153 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
54f1585a | 1154 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); |
5cb56059 | 1155 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1156 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1157 | |
3e6e0aab | 1158 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1159 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1160 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1161 | |
7f3d35fd KW |
1162 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1163 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1164 | |
49a9b07e | 1165 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1166 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1167 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1168 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1169 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1170 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1171 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1172 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1173 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1174 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1175 | |
609e36d3 | 1176 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1177 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1178 | |
91586a3b JK |
1179 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1180 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1181 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1182 | |
298101da AK |
1183 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1184 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1185 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1186 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1187 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1188 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1189 | gfn_t gfn, void *data, int offset, int len, | |
1190 | u32 access); | |
0a79b009 | 1191 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1192 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1193 | |
1a577b72 MT |
1194 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1195 | int irq_source_id, int level) | |
1196 | { | |
1197 | /* Logical OR for level trig interrupt */ | |
1198 | if (level) | |
1199 | __set_bit(irq_source_id, irq_state); | |
1200 | else | |
1201 | __clear_bit(irq_source_id, irq_state); | |
1202 | ||
1203 | return !!(*irq_state); | |
1204 | } | |
1205 | ||
1206 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1207 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1208 | |
3419ffc8 SY |
1209 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1210 | ||
1cb3f3ae | 1211 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1212 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1213 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1214 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1215 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1216 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
54987b7a PB |
1217 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1218 | struct x86_exception *exception); | |
ab9ae313 AK |
1219 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1220 | struct x86_exception *exception); | |
1221 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1222 | struct x86_exception *exception); | |
1223 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1224 | struct x86_exception *exception); | |
1225 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1226 | struct x86_exception *exception); | |
54f1585a | 1227 | |
d62caabb AS |
1228 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); |
1229 | ||
54f1585a ZX |
1230 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1231 | ||
14727754 | 1232 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, |
dc25e89e | 1233 | void *insn, int insn_len); |
a7052897 | 1234 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 1235 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 1236 | |
18552672 | 1237 | void kvm_enable_tdp(void); |
5f4cb662 | 1238 | void kvm_disable_tdp(void); |
18552672 | 1239 | |
54987b7a PB |
1240 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1241 | struct x86_exception *exception) | |
e459e322 XG |
1242 | { |
1243 | return gpa; | |
1244 | } | |
1245 | ||
ec6d273d ZX |
1246 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1247 | { | |
1248 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1249 | ||
1250 | return (struct kvm_mmu_page *)page_private(page); | |
1251 | } | |
1252 | ||
d6e88aec | 1253 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1254 | { |
1255 | u16 ldt; | |
1256 | asm("sldt %0" : "=g"(ldt)); | |
1257 | return ldt; | |
1258 | } | |
1259 | ||
d6e88aec | 1260 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1261 | { |
1262 | asm("lldt %0" : : "rm"(sel)); | |
1263 | } | |
ec6d273d | 1264 | |
ec6d273d ZX |
1265 | #ifdef CONFIG_X86_64 |
1266 | static inline unsigned long read_msr(unsigned long msr) | |
1267 | { | |
1268 | u64 value; | |
1269 | ||
1270 | rdmsrl(msr, value); | |
1271 | return value; | |
1272 | } | |
1273 | #endif | |
1274 | ||
ec6d273d ZX |
1275 | static inline u32 get_rdx_init_val(void) |
1276 | { | |
1277 | return 0x600; /* P6 family */ | |
1278 | } | |
1279 | ||
c1a5d4f9 AK |
1280 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1281 | { | |
1282 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1283 | } | |
1284 | ||
854e8bb1 NA |
1285 | static inline u64 get_canonical(u64 la) |
1286 | { | |
1287 | return ((int64_t)la << 16) >> 16; | |
1288 | } | |
1289 | ||
1290 | static inline bool is_noncanonical_address(u64 la) | |
1291 | { | |
1292 | #ifdef CONFIG_X86_64 | |
1293 | return get_canonical(la) != la; | |
1294 | #else | |
1295 | return false; | |
1296 | #endif | |
1297 | } | |
1298 | ||
ec6d273d ZX |
1299 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1300 | #define TSS_BASE_SIZE 0x68 | |
1301 | #define TSS_IOPB_SIZE (65536 / 8) | |
1302 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1303 | #define RMODE_TSS_SIZE \ |
1304 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1305 | |
37817f29 IE |
1306 | enum { |
1307 | TASK_SWITCH_CALL = 0, | |
1308 | TASK_SWITCH_IRET = 1, | |
1309 | TASK_SWITCH_JMP = 2, | |
1310 | TASK_SWITCH_GATE = 3, | |
1311 | }; | |
1312 | ||
1371d904 | 1313 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1314 | #define HF_HIF_MASK (1 << 1) |
1315 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1316 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1317 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1318 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1319 | #define HF_SMM_MASK (1 << 6) |
1320 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1321 | |
699023e2 PB |
1322 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1323 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1324 | ||
1325 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1326 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1327 | |
4ecac3fd AK |
1328 | /* |
1329 | * Hardware virtualization extension instructions may fault if a | |
1330 | * reboot turns off virtualization while processes are running. | |
1331 | * Trap the fault and ignore the instruction if that happens. | |
1332 | */ | |
b7c4145b | 1333 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1334 | |
5e520e62 | 1335 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1336 | "666: " insn "\n\t" \ |
b7c4145b | 1337 | "668: \n\t" \ |
18b13e54 | 1338 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1339 | "667: \n\t" \ |
5e520e62 | 1340 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1341 | "cmpb $0, kvm_rebooting \n\t" \ |
1342 | "jne 668b \n\t" \ | |
8ceed347 | 1343 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1344 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1345 | ".popsection \n\t" \ |
3ee89722 | 1346 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1347 | |
5e520e62 AK |
1348 | #define __kvm_handle_fault_on_reboot(insn) \ |
1349 | ____kvm_handle_fault_on_reboot(insn, "") | |
1350 | ||
e930bffe AA |
1351 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1352 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1353 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1354 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1355 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1356 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1357 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1358 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1359 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1360 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1361 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1362 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
fe71557a TC |
1363 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
1364 | unsigned long address); | |
e930bffe | 1365 | |
18863bdd | 1366 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1367 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1368 | |
35181e86 | 1369 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1370 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1371 | |
82b32774 | 1372 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1373 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1374 | ||
2860c4b1 PB |
1375 | void kvm_make_mclock_inprogress_request(struct kvm *kvm); |
1376 | void kvm_make_scan_ioapic_request(struct kvm *kvm); | |
1377 | ||
af585b92 GN |
1378 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1379 | struct kvm_async_pf *work); | |
1380 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1381 | struct kvm_async_pf *work); | |
56028d08 GN |
1382 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1383 | struct kvm_async_pf *work); | |
7c90705b | 1384 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1385 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1386 | ||
6affcbed KH |
1387 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); |
1388 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); | |
db8fcefa | 1389 | |
f5132b01 GN |
1390 | int kvm_is_in_guest(void); |
1391 | ||
1d8007bd PB |
1392 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); |
1393 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
d71ba788 PB |
1394 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1395 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1396 | |
8feb4a04 FW |
1397 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1398 | struct kvm_vcpu **dest_vcpu); | |
1399 | ||
37131313 | 1400 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 1401 | struct kvm_lapic_irq *irq); |
197a4f4b | 1402 | |
d1ed092f SS |
1403 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) |
1404 | { | |
1405 | if (kvm_x86_ops->vcpu_blocking) | |
1406 | kvm_x86_ops->vcpu_blocking(vcpu); | |
1407 | } | |
1408 | ||
1409 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1410 | { | |
1411 | if (kvm_x86_ops->vcpu_unblocking) | |
1412 | kvm_x86_ops->vcpu_unblocking(vcpu); | |
1413 | } | |
1414 | ||
3491caf2 | 1415 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
3217f7c2 | 1416 | |
7d669f50 SS |
1417 | static inline int kvm_cpu_get_apicid(int mps_cpu) |
1418 | { | |
1419 | #ifdef CONFIG_X86_LOCAL_APIC | |
1420 | return __default_cpu_present_to_apicid(mps_cpu); | |
1421 | #else | |
1422 | WARN_ON_ONCE(1); | |
1423 | return BAD_APICID; | |
1424 | #endif | |
1425 | } | |
1426 | ||
1965aae3 | 1427 | #endif /* _ASM_X86_KVM_HOST_H */ |