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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
34c16eec | 27 | |
50d0a0f9 | 28 | #include <asm/pvclock-abi.h> |
e01a1b57 | 29 | #include <asm/desc.h> |
0bed3b56 | 30 | #include <asm/mtrr.h> |
9962d032 | 31 | #include <asm/msr-index.h> |
3ee89722 | 32 | #include <asm/asm.h> |
e01a1b57 | 33 | |
cbf64358 | 34 | #define KVM_MAX_VCPUS 255 |
a59cb29e | 35 | #define KVM_SOFT_MAX_VCPUS 160 |
0f888f5a | 36 | #define KVM_USER_MEM_SLOTS 125 |
0743247f AW |
37 | /* memory slots that are not exposed to userspace */ |
38 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 39 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 40 | |
cef4dea0 | 41 | #define KVM_MMIO_SIZE 16 |
69a9f69b AK |
42 | |
43 | #define KVM_PIO_PAGE_OFFSET 1 | |
542472b5 | 44 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
69a9f69b | 45 | |
8175e5b7 AG |
46 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
47 | ||
cfec82cb JR |
48 | #define CR0_RESERVED_BITS \ |
49 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
50 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
51 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
52 | ||
cd6e8f87 ZX |
53 | #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) |
54 | #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) | |
ad756a16 | 55 | #define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL |
7d76b4d3 JP |
56 | #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ |
57 | 0xFFFFFF0000000000ULL) | |
cfec82cb JR |
58 | #define CR4_RESERVED_BITS \ |
59 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
60 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 61 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 62 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
cfec82cb JR |
63 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
64 | ||
65 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
66 | ||
67 | ||
cd6e8f87 | 68 | |
cd6e8f87 | 69 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
70 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
71 | ||
cd6e8f87 ZX |
72 | #define UNMAPPED_GVA (~(gpa_t)0) |
73 | ||
ec04b260 | 74 | /* KVM Hugepage definitions for x86 */ |
04326caa | 75 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
76 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
77 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
78 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
79 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
80 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 81 | |
6d9d41e5 CD |
82 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
83 | { | |
84 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
85 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
86 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
87 | } | |
88 | ||
cd6e8f87 ZX |
89 | #define SELECTOR_TI_MASK (1 << 2) |
90 | #define SELECTOR_RPL_MASK 0x03 | |
91 | ||
92 | #define IOPL_SHIFT 12 | |
93 | ||
d657a98e ZX |
94 | #define KVM_PERMILLE_MMU_PAGES 20 |
95 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
96 | #define KVM_MMU_HASH_SHIFT 10 |
97 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
98 | #define KVM_MIN_FREE_MMU_PAGES 5 |
99 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 100 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 101 | #define KVM_NR_FIXED_MTRR_REGION 88 |
9ba075a6 | 102 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 103 | |
af585b92 GN |
104 | #define ASYNC_PF_PER_VCPU 64 |
105 | ||
d657a98e ZX |
106 | struct kvm_vcpu; |
107 | struct kvm; | |
af585b92 | 108 | struct kvm_async_pf; |
d657a98e | 109 | |
5fdbf976 | 110 | enum kvm_reg { |
2b3ccfa0 ZX |
111 | VCPU_REGS_RAX = 0, |
112 | VCPU_REGS_RCX = 1, | |
113 | VCPU_REGS_RDX = 2, | |
114 | VCPU_REGS_RBX = 3, | |
115 | VCPU_REGS_RSP = 4, | |
116 | VCPU_REGS_RBP = 5, | |
117 | VCPU_REGS_RSI = 6, | |
118 | VCPU_REGS_RDI = 7, | |
119 | #ifdef CONFIG_X86_64 | |
120 | VCPU_REGS_R8 = 8, | |
121 | VCPU_REGS_R9 = 9, | |
122 | VCPU_REGS_R10 = 10, | |
123 | VCPU_REGS_R11 = 11, | |
124 | VCPU_REGS_R12 = 12, | |
125 | VCPU_REGS_R13 = 13, | |
126 | VCPU_REGS_R14 = 14, | |
127 | VCPU_REGS_R15 = 15, | |
128 | #endif | |
5fdbf976 | 129 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
130 | NR_VCPU_REGS |
131 | }; | |
132 | ||
6de4f3ad AK |
133 | enum kvm_reg_ex { |
134 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 135 | VCPU_EXREG_CR3, |
6de12732 | 136 | VCPU_EXREG_RFLAGS, |
69c73028 | 137 | VCPU_EXREG_CPL, |
2fb92db1 | 138 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
139 | }; |
140 | ||
2b3ccfa0 | 141 | enum { |
81609e3e | 142 | VCPU_SREG_ES, |
2b3ccfa0 | 143 | VCPU_SREG_CS, |
81609e3e | 144 | VCPU_SREG_SS, |
2b3ccfa0 | 145 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
146 | VCPU_SREG_FS, |
147 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
148 | VCPU_SREG_TR, |
149 | VCPU_SREG_LDTR, | |
150 | }; | |
151 | ||
56e82318 | 152 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 153 | |
d657a98e ZX |
154 | #define KVM_NR_MEM_OBJS 40 |
155 | ||
42dbaa5a JK |
156 | #define KVM_NR_DB_REGS 4 |
157 | ||
158 | #define DR6_BD (1 << 13) | |
159 | #define DR6_BS (1 << 14) | |
160 | #define DR6_FIXED_1 0xffff0ff0 | |
161 | #define DR6_VOLATILE 0x0000e00f | |
162 | ||
163 | #define DR7_BP_EN_MASK 0x000000ff | |
164 | #define DR7_GE (1 << 9) | |
165 | #define DR7_GD (1 << 13) | |
166 | #define DR7_FIXED_1 0x00000400 | |
167 | #define DR7_VOLATILE 0xffff23ff | |
168 | ||
41383771 GN |
169 | /* apic attention bits */ |
170 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
171 | /* |
172 | * The following bit is set with PV-EOI, unset on EOI. | |
173 | * We detect PV-EOI changes by guest by comparing | |
174 | * this bit with PV-EOI in guest memory. | |
175 | * See the implementation in apic_update_pv_eoi. | |
176 | */ | |
177 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 178 | |
d657a98e ZX |
179 | /* |
180 | * We don't want allocation failures within the mmu code, so we preallocate | |
181 | * enough memory for a single page fault in a cache. | |
182 | */ | |
183 | struct kvm_mmu_memory_cache { | |
184 | int nobjs; | |
185 | void *objects[KVM_NR_MEM_OBJS]; | |
186 | }; | |
187 | ||
d657a98e ZX |
188 | /* |
189 | * kvm_mmu_page_role, below, is defined as: | |
190 | * | |
191 | * bits 0:3 - total guest paging levels (2-4, or zero for real mode) | |
192 | * bits 4:7 - page table level for this shadow (1-4) | |
193 | * bits 8:9 - page table quadrant for 2-level guests | |
f6e2c02b AK |
194 | * bit 16 - direct mapping of virtual to physical mapping at gfn |
195 | * used for real mode and two-dimensional paging | |
d657a98e ZX |
196 | * bits 17:19 - common access permissions for all ptes in this shadow page |
197 | */ | |
198 | union kvm_mmu_page_role { | |
199 | unsigned word; | |
200 | struct { | |
7d76b4d3 | 201 | unsigned level:4; |
5b7e0102 | 202 | unsigned cr4_pae:1; |
7d76b4d3 JP |
203 | unsigned quadrant:2; |
204 | unsigned pad_for_nice_hex_output:6; | |
f6e2c02b | 205 | unsigned direct:1; |
7d76b4d3 | 206 | unsigned access:3; |
2e53d63a | 207 | unsigned invalid:1; |
9645bb56 | 208 | unsigned nxe:1; |
3dbe1415 | 209 | unsigned cr0_wp:1; |
411c588d | 210 | unsigned smep_andnot_wp:1; |
d657a98e ZX |
211 | }; |
212 | }; | |
213 | ||
214 | struct kvm_mmu_page { | |
215 | struct list_head link; | |
216 | struct hlist_node hash_link; | |
217 | ||
218 | /* | |
219 | * The following two entries are used to key the shadow page in the | |
220 | * hash table. | |
221 | */ | |
222 | gfn_t gfn; | |
223 | union kvm_mmu_page_role role; | |
224 | ||
225 | u64 *spt; | |
226 | /* hold the gfn of each spte inside spt */ | |
227 | gfn_t *gfns; | |
4731d4c7 | 228 | bool unsync; |
0571d366 | 229 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 230 | unsigned int unsync_children; |
67052b35 | 231 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
f6f8adee XG |
232 | |
233 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 234 | unsigned long mmu_valid_gen; |
f6f8adee | 235 | |
0074ff63 | 236 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
237 | |
238 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
239 | /* |
240 | * Used out of the mmu-lock to avoid reading spte values while an | |
241 | * update is in progress; see the comments in __get_spte_lockless(). | |
242 | */ | |
c2a2ac2b XG |
243 | int clear_spte_count; |
244 | #endif | |
245 | ||
0cbf8e43 | 246 | /* Number of writes since the last time traversal visited this page. */ |
a30f47cb | 247 | int write_flooding_count; |
d657a98e ZX |
248 | }; |
249 | ||
1c08364c AK |
250 | struct kvm_pio_request { |
251 | unsigned long count; | |
1c08364c AK |
252 | int in; |
253 | int port; | |
254 | int size; | |
1c08364c AK |
255 | }; |
256 | ||
d657a98e ZX |
257 | /* |
258 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
259 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
260 | * mode. | |
261 | */ | |
262 | struct kvm_mmu { | |
f43addd4 | 263 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 264 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 265 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
266 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
267 | bool prefault); | |
6389ee94 AK |
268 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
269 | struct x86_exception *fault); | |
1871c602 | 270 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 271 | struct x86_exception *exception); |
c30a358d | 272 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
e8bc217a | 273 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 274 | struct kvm_mmu_page *sp); |
a7052897 | 275 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 276 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 277 | u64 *spte, const void *pte); |
d657a98e ZX |
278 | hpa_t root_hpa; |
279 | int root_level; | |
280 | int shadow_root_level; | |
a770f6f2 | 281 | union kvm_mmu_page_role base_role; |
c5a78f2b | 282 | bool direct_map; |
d657a98e | 283 | |
97d64b78 AK |
284 | /* |
285 | * Bitmap; bit set = permission fault | |
286 | * Byte index: page fault error code [4:1] | |
287 | * Bit index: pte permissions in ACC_* format | |
288 | */ | |
289 | u8 permissions[16]; | |
290 | ||
d657a98e | 291 | u64 *pae_root; |
81407ca5 | 292 | u64 *lm_root; |
82725b20 | 293 | u64 rsvd_bits_mask[2][4]; |
25d92081 | 294 | u64 bad_mt_xwr; |
ff03a073 | 295 | |
6fd01b71 AK |
296 | /* |
297 | * Bitmap: bit set = last pte in walk | |
298 | * index[0:1]: level (zero-based) | |
299 | * index[2]: pte.ps | |
300 | */ | |
301 | u8 last_pte_bitmap; | |
302 | ||
2d48a985 JR |
303 | bool nx; |
304 | ||
ff03a073 | 305 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
306 | }; |
307 | ||
f5132b01 GN |
308 | enum pmc_type { |
309 | KVM_PMC_GP = 0, | |
310 | KVM_PMC_FIXED, | |
311 | }; | |
312 | ||
313 | struct kvm_pmc { | |
314 | enum pmc_type type; | |
315 | u8 idx; | |
316 | u64 counter; | |
317 | u64 eventsel; | |
318 | struct perf_event *perf_event; | |
319 | struct kvm_vcpu *vcpu; | |
320 | }; | |
321 | ||
322 | struct kvm_pmu { | |
323 | unsigned nr_arch_gp_counters; | |
324 | unsigned nr_arch_fixed_counters; | |
325 | unsigned available_event_types; | |
326 | u64 fixed_ctr_ctrl; | |
327 | u64 global_ctrl; | |
328 | u64 global_status; | |
329 | u64 global_ovf_ctrl; | |
330 | u64 counter_bitmask[2]; | |
331 | u64 global_ctrl_mask; | |
103af0a9 | 332 | u64 reserved_bits; |
f5132b01 | 333 | u8 version; |
15c7ad51 RR |
334 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
335 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
336 | struct irq_work irq_work; |
337 | u64 reprogram_pmi; | |
338 | }; | |
339 | ||
360b948d PB |
340 | enum { |
341 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 342 | KVM_DEBUGREG_WONT_EXIT = 2, |
360b948d PB |
343 | }; |
344 | ||
ad312c7c | 345 | struct kvm_vcpu_arch { |
5fdbf976 MT |
346 | /* |
347 | * rip and regs accesses must go through | |
348 | * kvm_{register,rip}_{read,write} functions. | |
349 | */ | |
350 | unsigned long regs[NR_VCPU_REGS]; | |
351 | u32 regs_avail; | |
352 | u32 regs_dirty; | |
34c16eec ZX |
353 | |
354 | unsigned long cr0; | |
e8467fda | 355 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
356 | unsigned long cr2; |
357 | unsigned long cr3; | |
358 | unsigned long cr4; | |
fc78f519 | 359 | unsigned long cr4_guest_owned_bits; |
34c16eec | 360 | unsigned long cr8; |
1371d904 | 361 | u32 hflags; |
f6801dff | 362 | u64 efer; |
34c16eec ZX |
363 | u64 apic_base; |
364 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
41383771 | 365 | unsigned long apic_attention; |
e1035715 | 366 | int32_t apic_arb_prio; |
34c16eec | 367 | int mp_state; |
34c16eec | 368 | u64 ia32_misc_enable_msr; |
b209749f | 369 | bool tpr_access_reporting; |
34c16eec | 370 | |
14dfe855 JR |
371 | /* |
372 | * Paging state of the vcpu | |
373 | * | |
374 | * If the vcpu runs in guest mode with two level paging this still saves | |
375 | * the paging mode of the l1 guest. This context is always used to | |
376 | * handle faults. | |
377 | */ | |
34c16eec | 378 | struct kvm_mmu mmu; |
8df25a32 | 379 | |
6539e738 JR |
380 | /* |
381 | * Paging state of an L2 guest (used for nested npt) | |
382 | * | |
383 | * This context will save all necessary information to walk page tables | |
384 | * of the an L2 guest. This context is only initialized for page table | |
385 | * walking and not for faulting since we never handle l2 page faults on | |
386 | * the host. | |
387 | */ | |
388 | struct kvm_mmu nested_mmu; | |
389 | ||
14dfe855 JR |
390 | /* |
391 | * Pointer to the mmu context currently used for | |
392 | * gva_to_gpa translations. | |
393 | */ | |
394 | struct kvm_mmu *walk_mmu; | |
395 | ||
53c07b18 | 396 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
397 | struct kvm_mmu_memory_cache mmu_page_cache; |
398 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
399 | ||
98918833 | 400 | struct fpu guest_fpu; |
2acf923e | 401 | u64 xcr0; |
d7876f1b | 402 | u64 guest_supported_xcr0; |
4344ee98 | 403 | u32 guest_xstate_size; |
34c16eec | 404 | |
34c16eec ZX |
405 | struct kvm_pio_request pio; |
406 | void *pio_data; | |
407 | ||
66fd3f7f GN |
408 | u8 event_exit_inst_len; |
409 | ||
298101da AK |
410 | struct kvm_queued_exception { |
411 | bool pending; | |
412 | bool has_error_code; | |
ce7ddec4 | 413 | bool reinject; |
298101da AK |
414 | u8 nr; |
415 | u32 error_code; | |
416 | } exception; | |
417 | ||
937a7eae AK |
418 | struct kvm_queued_interrupt { |
419 | bool pending; | |
66fd3f7f | 420 | bool soft; |
937a7eae AK |
421 | u8 nr; |
422 | } interrupt; | |
423 | ||
34c16eec ZX |
424 | int halt_request; /* real mode on Intel only */ |
425 | ||
426 | int cpuid_nent; | |
07716717 | 427 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
34c16eec ZX |
428 | /* emulate context */ |
429 | ||
430 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
431 | bool emulate_regs_need_sync_to_vcpu; |
432 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 433 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
434 | |
435 | gpa_t time; | |
50d0a0f9 | 436 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 437 | unsigned int hw_tsc_khz; |
0b79459b AH |
438 | struct gfn_to_hva_cache pv_time; |
439 | bool pv_time_enabled; | |
51d59c6b MT |
440 | /* set guest stopped flag in pvclock flags field */ |
441 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
442 | |
443 | struct { | |
444 | u64 msr_val; | |
445 | u64 last_steal; | |
446 | u64 accum_steal; | |
447 | struct gfn_to_hva_cache stime; | |
448 | struct kvm_steal_time steal; | |
449 | } st; | |
450 | ||
1d5f066e | 451 | u64 last_guest_tsc; |
6f526ec5 | 452 | u64 last_host_tsc; |
0dd6a6ed | 453 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
454 | u64 this_tsc_nsec; |
455 | u64 this_tsc_write; | |
456 | u8 this_tsc_generation; | |
c285545f | 457 | bool tsc_catchup; |
cc578287 ZA |
458 | bool tsc_always_catchup; |
459 | s8 virtual_tsc_shift; | |
460 | u32 virtual_tsc_mult; | |
461 | u32 virtual_tsc_khz; | |
ba904635 | 462 | s64 ia32_tsc_adjust_msr; |
3419ffc8 | 463 | |
7460fb4a AK |
464 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
465 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
466 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
9ba075a6 | 467 | |
0bed3b56 SY |
468 | struct mtrr_state_type mtrr_state; |
469 | u32 pat; | |
42dbaa5a | 470 | |
360b948d | 471 | unsigned switch_db_regs; |
42dbaa5a JK |
472 | unsigned long db[KVM_NR_DB_REGS]; |
473 | unsigned long dr6; | |
474 | unsigned long dr7; | |
475 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 476 | unsigned long guest_debug_dr7; |
890ca9ae HY |
477 | |
478 | u64 mcg_cap; | |
479 | u64 mcg_status; | |
480 | u64 mcg_ctl; | |
481 | u64 *mce_banks; | |
94fe45da | 482 | |
bebb106a XG |
483 | /* Cache MMIO info */ |
484 | u64 mmio_gva; | |
485 | unsigned access; | |
486 | gfn_t mmio_gfn; | |
487 | ||
f5132b01 GN |
488 | struct kvm_pmu pmu; |
489 | ||
94fe45da | 490 | /* used for guest single stepping over the given code position */ |
94fe45da | 491 | unsigned long singlestep_rip; |
f92653ee | 492 | |
10388a07 GN |
493 | /* fields used by HYPER-V emulation */ |
494 | u64 hv_vapic; | |
f5f48ee1 SY |
495 | |
496 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 497 | |
1cb3f3ae XG |
498 | unsigned long last_retry_eip; |
499 | unsigned long last_retry_addr; | |
500 | ||
af585b92 GN |
501 | struct { |
502 | bool halted; | |
503 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
504 | struct gfn_to_hva_cache data; |
505 | u64 msr_val; | |
7c90705b | 506 | u32 id; |
6adba527 | 507 | bool send_user_only; |
af585b92 | 508 | } apf; |
2b036c6b BO |
509 | |
510 | /* OSVW MSRs (AMD only) */ | |
511 | struct { | |
512 | u64 length; | |
513 | u64 status; | |
514 | } osvw; | |
ae7a2a3f MT |
515 | |
516 | struct { | |
517 | u64 msr_val; | |
518 | struct gfn_to_hva_cache data; | |
519 | } pv_eoi; | |
93c05d3e XG |
520 | |
521 | /* | |
522 | * Indicate whether the access faults on its page table in guest | |
523 | * which is set when fix page fault and used to detect unhandeable | |
524 | * instruction. | |
525 | */ | |
526 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
527 | |
528 | /* set at EPT violation at this point */ | |
529 | unsigned long exit_qualification; | |
6aef266c SV |
530 | |
531 | /* pv related host specific info */ | |
532 | struct { | |
533 | bool pv_unhalted; | |
534 | } pv; | |
34c16eec ZX |
535 | }; |
536 | ||
db3fe4eb | 537 | struct kvm_lpage_info { |
db3fe4eb TY |
538 | int write_count; |
539 | }; | |
540 | ||
541 | struct kvm_arch_memory_slot { | |
d89cc617 | 542 | unsigned long *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
543 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
544 | }; | |
545 | ||
1e08ec4a GN |
546 | struct kvm_apic_map { |
547 | struct rcu_head rcu; | |
548 | u8 ldr_bits; | |
549 | /* fields bellow are used to decode ldr values in different modes */ | |
550 | u32 cid_shift, cid_mask, lid_mask; | |
551 | struct kvm_lapic *phys_map[256]; | |
552 | /* first index is cluster id second is cpu id in a cluster */ | |
553 | struct kvm_lapic *logical_map[16][16]; | |
554 | }; | |
555 | ||
fef9cce0 | 556 | struct kvm_arch { |
49d5ca26 | 557 | unsigned int n_used_mmu_pages; |
f05e70ac | 558 | unsigned int n_requested_mmu_pages; |
39de71ec | 559 | unsigned int n_max_mmu_pages; |
332b207d | 560 | unsigned int indirect_shadow_pages; |
5304b8d3 | 561 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
562 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
563 | /* | |
564 | * Hash table of struct kvm_mmu_page. | |
565 | */ | |
566 | struct list_head active_mmu_pages; | |
365c8868 XG |
567 | struct list_head zapped_obsolete_pages; |
568 | ||
4d5c5d0f | 569 | struct list_head assigned_dev_head; |
19de40a8 | 570 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 571 | bool iommu_noncoherent; |
e0f0bbc5 AW |
572 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
573 | atomic_t noncoherent_dma_count; | |
d7deeeb0 ZX |
574 | struct kvm_pic *vpic; |
575 | struct kvm_ioapic *vioapic; | |
7837699f | 576 | struct kvm_pit *vpit; |
cc6e462c | 577 | int vapics_in_nmi_mode; |
1e08ec4a GN |
578 | struct mutex apic_map_lock; |
579 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 580 | |
bfc6d222 ZX |
581 | unsigned int tss_addr; |
582 | struct page *apic_access_page; | |
18068523 GOC |
583 | |
584 | gpa_t wall_clock; | |
b7ebfb05 SY |
585 | |
586 | struct page *ept_identity_pagetable; | |
587 | bool ept_identity_pagetable_done; | |
b927a3ce | 588 | gpa_t ept_identity_map_addr; |
5550af4d SY |
589 | |
590 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 591 | s64 kvmclock_offset; |
038f8c11 | 592 | raw_spinlock_t tsc_write_lock; |
f38e098f | 593 | u64 last_tsc_nsec; |
f38e098f | 594 | u64 last_tsc_write; |
5d3cb0f6 | 595 | u32 last_tsc_khz; |
e26101b1 ZA |
596 | u64 cur_tsc_nsec; |
597 | u64 cur_tsc_write; | |
598 | u64 cur_tsc_offset; | |
599 | u8 cur_tsc_generation; | |
b48aa97e | 600 | int nr_vcpus_matched_tsc; |
ffde22ac | 601 | |
d828199e MT |
602 | spinlock_t pvclock_gtod_sync_lock; |
603 | bool use_master_clock; | |
604 | u64 master_kernel_ns; | |
605 | cycle_t master_cycle_now; | |
7e44e449 | 606 | struct delayed_work kvmclock_update_work; |
332967a3 | 607 | struct delayed_work kvmclock_sync_work; |
d828199e | 608 | |
ffde22ac | 609 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a GN |
610 | |
611 | /* fields used by HYPER-V emulation */ | |
612 | u64 hv_guest_os_id; | |
613 | u64 hv_hypercall; | |
e984097b | 614 | u64 hv_tsc_page; |
b034cf01 XG |
615 | |
616 | #ifdef CONFIG_KVM_MMU_AUDIT | |
617 | int audit_point; | |
618 | #endif | |
d69fb81f ZX |
619 | }; |
620 | ||
0711456c ZX |
621 | struct kvm_vm_stat { |
622 | u32 mmu_shadow_zapped; | |
623 | u32 mmu_pte_write; | |
624 | u32 mmu_pte_updated; | |
625 | u32 mmu_pde_zapped; | |
626 | u32 mmu_flooded; | |
627 | u32 mmu_recycled; | |
dfc5aa00 | 628 | u32 mmu_cache_miss; |
4731d4c7 | 629 | u32 mmu_unsync; |
0711456c | 630 | u32 remote_tlb_flush; |
05da4558 | 631 | u32 lpages; |
0711456c ZX |
632 | }; |
633 | ||
77b4c255 ZX |
634 | struct kvm_vcpu_stat { |
635 | u32 pf_fixed; | |
636 | u32 pf_guest; | |
637 | u32 tlb_flush; | |
638 | u32 invlpg; | |
639 | ||
640 | u32 exits; | |
641 | u32 io_exits; | |
642 | u32 mmio_exits; | |
643 | u32 signal_exits; | |
644 | u32 irq_window_exits; | |
f08864b4 | 645 | u32 nmi_window_exits; |
77b4c255 ZX |
646 | u32 halt_exits; |
647 | u32 halt_wakeup; | |
648 | u32 request_irq_exits; | |
649 | u32 irq_exits; | |
650 | u32 host_state_reload; | |
651 | u32 efer_reload; | |
652 | u32 fpu_reload; | |
653 | u32 insn_emulation; | |
654 | u32 insn_emulation_fail; | |
f11c3a8d | 655 | u32 hypercalls; |
fa89a817 | 656 | u32 irq_injections; |
c4abb7c9 | 657 | u32 nmi_injections; |
77b4c255 | 658 | }; |
ad312c7c | 659 | |
8a76d7f2 JR |
660 | struct x86_instruction_info; |
661 | ||
8fe8ab46 WA |
662 | struct msr_data { |
663 | bool host_initiated; | |
664 | u32 index; | |
665 | u64 data; | |
666 | }; | |
667 | ||
ea4a5ff8 ZX |
668 | struct kvm_x86_ops { |
669 | int (*cpu_has_kvm_support)(void); /* __init */ | |
670 | int (*disabled_by_bios)(void); /* __init */ | |
10474ae8 | 671 | int (*hardware_enable)(void *dummy); |
ea4a5ff8 ZX |
672 | void (*hardware_disable)(void *dummy); |
673 | void (*check_processor_compatibility)(void *rtn); | |
674 | int (*hardware_setup)(void); /* __init */ | |
675 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 676 | bool (*cpu_has_accelerated_tpr)(void); |
0e851880 | 677 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
678 | |
679 | /* Create, but do not attach this VCPU */ | |
680 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
681 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
57f252f2 | 682 | void (*vcpu_reset)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
683 | |
684 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
685 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
686 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 687 | |
c8639010 | 688 | void (*update_db_bp_intercept)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 689 | int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata); |
8fe8ab46 | 690 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
691 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
692 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
693 | struct kvm_segment *var, int seg); | |
2e4d2653 | 694 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
695 | void (*set_segment)(struct kvm_vcpu *vcpu, |
696 | struct kvm_segment *var, int seg); | |
697 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 698 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 699 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
700 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
701 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
702 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 703 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 704 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
705 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
706 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
707 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
708 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
709 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
710 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 711 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 712 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 713 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
714 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
715 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
6b52d186 | 716 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 717 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
718 | |
719 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 720 | |
851ba692 AK |
721 | void (*run)(struct kvm_vcpu *vcpu); |
722 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 723 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 GC |
724 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
725 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); | |
ea4a5ff8 ZX |
726 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
727 | unsigned char *hypercall_addr); | |
66fd3f7f | 728 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 729 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 730 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
731 | bool has_error_code, u32 error_code, |
732 | bool reinject); | |
b463a6f7 | 733 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 734 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 735 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
736 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
737 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
738 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
739 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 740 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
c7c9c56c YZ |
741 | int (*vm_has_apicv)(struct kvm *kvm); |
742 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); | |
743 | void (*hwapic_isr_update)(struct kvm *kvm, int isr); | |
744 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); | |
8d14695f | 745 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
a20ed54d YZ |
746 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
747 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 748 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 749 | int (*get_tdp_level)(void); |
4b12f0de | 750 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 751 | int (*get_lpage_level)(void); |
4e47c7a6 | 752 | bool (*rdtscp_supported)(void); |
ad756a16 | 753 | bool (*invpcid_supported)(void); |
f1e2b260 | 754 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 755 | |
1c97f0a0 JR |
756 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
757 | ||
d4330ef2 JR |
758 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
759 | ||
f5f48ee1 SY |
760 | bool (*has_wbinvd_exit)(void); |
761 | ||
cc578287 | 762 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
ba904635 | 763 | u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
764 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
765 | ||
857e4099 | 766 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
886b470c | 767 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc); |
857e4099 | 768 | |
586f9607 | 769 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
770 | |
771 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
772 | struct x86_instruction_info *info, | |
773 | enum x86_intercept_stage stage); | |
a547c6db | 774 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 775 | bool (*mpx_supported)(void); |
b6b8a145 JK |
776 | |
777 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ea4a5ff8 ZX |
778 | }; |
779 | ||
af585b92 | 780 | struct kvm_arch_async_pf { |
7c90705b | 781 | u32 token; |
af585b92 | 782 | gfn_t gfn; |
fb67e14f | 783 | unsigned long cr3; |
c4806acd | 784 | bool direct_map; |
af585b92 GN |
785 | }; |
786 | ||
97896d04 ZX |
787 | extern struct kvm_x86_ops *kvm_x86_ops; |
788 | ||
f1e2b260 MT |
789 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
790 | s64 adjustment) | |
791 | { | |
792 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
793 | } | |
794 | ||
795 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
796 | { | |
797 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
798 | } | |
799 | ||
54f1585a ZX |
800 | int kvm_mmu_module_init(void); |
801 | void kvm_mmu_module_exit(void); | |
802 | ||
803 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
804 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 805 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
7b52345e | 806 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 807 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a | 808 | |
8a3c1a33 | 809 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
54f1585a | 810 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot); |
5dc99b23 TY |
811 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
812 | struct kvm_memory_slot *slot, | |
813 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 814 | void kvm_mmu_zap_all(struct kvm *kvm); |
f8f55942 | 815 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm); |
3ad82a7e | 816 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
817 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
818 | ||
ff03a073 | 819 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 820 | |
3200f405 | 821 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 822 | const void *val, int bytes); |
4b12f0de | 823 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); |
2f333bcb MT |
824 | |
825 | extern bool tdp_enabled; | |
9f811285 | 826 | |
a3e06bbe LJ |
827 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
828 | ||
92a1f12d JR |
829 | /* control of guest tsc rate supported? */ |
830 | extern bool kvm_has_tsc_control; | |
831 | /* minimum supported tsc_khz for guests */ | |
832 | extern u32 kvm_min_guest_tsc_khz; | |
833 | /* maximum supported tsc_khz for guests */ | |
834 | extern u32 kvm_max_guest_tsc_khz; | |
835 | ||
54f1585a | 836 | enum emulation_result { |
ac0a48c3 PB |
837 | EMULATE_DONE, /* no further processing */ |
838 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
839 | EMULATE_FAIL, /* can't emulate this instruction */ |
840 | }; | |
841 | ||
571008da SY |
842 | #define EMULTYPE_NO_DECODE (1 << 0) |
843 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 844 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 845 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 846 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
847 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
848 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
849 | |
850 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
851 | int emulation_type) | |
852 | { | |
dc25e89e | 853 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
854 | } |
855 | ||
f2b4b7dd | 856 | void kvm_enable_efer_bits(u64); |
384bb783 | 857 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
54f1585a | 858 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); |
8fe8ab46 | 859 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
860 | |
861 | struct x86_emulate_ctxt; | |
862 | ||
cf8f70bf | 863 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
864 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
865 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
f5f48ee1 | 866 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 867 | |
3e6e0aab | 868 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 869 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
66450a21 | 870 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector); |
3e6e0aab | 871 | |
7f3d35fd KW |
872 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
873 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 874 | |
49a9b07e | 875 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 876 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 877 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 878 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
879 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
880 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
881 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
882 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 883 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 884 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a ZX |
885 | |
886 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); | |
8fe8ab46 | 887 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 888 | |
91586a3b JK |
889 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
890 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 891 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 892 | |
298101da AK |
893 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
894 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
895 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
896 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 897 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
898 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
899 | gfn_t gfn, void *data, int offset, int len, | |
900 | u32 access); | |
6389ee94 | 901 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
0a79b009 | 902 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
298101da | 903 | |
1a577b72 MT |
904 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
905 | int irq_source_id, int level) | |
906 | { | |
907 | /* Logical OR for level trig interrupt */ | |
908 | if (level) | |
909 | __set_bit(irq_source_id, irq_state); | |
910 | else | |
911 | __clear_bit(irq_source_id, irq_state); | |
912 | ||
913 | return !!(*irq_state); | |
914 | } | |
915 | ||
916 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
917 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 918 | |
3419ffc8 SY |
919 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
920 | ||
10ab25cd | 921 | int fx_init(struct kvm_vcpu *vcpu); |
54f1585a | 922 | |
d835dfec | 923 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); |
54f1585a | 924 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 925 | const u8 *new, int bytes); |
1cb3f3ae | 926 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
927 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
928 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
929 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
930 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 931 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
e459e322 | 932 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
ab9ae313 AK |
933 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
934 | struct x86_exception *exception); | |
935 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
936 | struct x86_exception *exception); | |
937 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
938 | struct x86_exception *exception); | |
939 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
940 | struct x86_exception *exception); | |
54f1585a ZX |
941 | |
942 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
943 | ||
dc25e89e AP |
944 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
945 | void *insn, int insn_len); | |
a7052897 | 946 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 947 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 948 | |
18552672 | 949 | void kvm_enable_tdp(void); |
5f4cb662 | 950 | void kvm_disable_tdp(void); |
18552672 | 951 | |
e459e322 XG |
952 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
953 | { | |
954 | return gpa; | |
955 | } | |
956 | ||
ec6d273d ZX |
957 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
958 | { | |
959 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
960 | ||
961 | return (struct kvm_mmu_page *)page_private(page); | |
962 | } | |
963 | ||
d6e88aec | 964 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
965 | { |
966 | u16 ldt; | |
967 | asm("sldt %0" : "=g"(ldt)); | |
968 | return ldt; | |
969 | } | |
970 | ||
d6e88aec | 971 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
972 | { |
973 | asm("lldt %0" : : "rm"(sel)); | |
974 | } | |
ec6d273d | 975 | |
ec6d273d ZX |
976 | #ifdef CONFIG_X86_64 |
977 | static inline unsigned long read_msr(unsigned long msr) | |
978 | { | |
979 | u64 value; | |
980 | ||
981 | rdmsrl(msr, value); | |
982 | return value; | |
983 | } | |
984 | #endif | |
985 | ||
ec6d273d ZX |
986 | static inline u32 get_rdx_init_val(void) |
987 | { | |
988 | return 0x600; /* P6 family */ | |
989 | } | |
990 | ||
c1a5d4f9 AK |
991 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
992 | { | |
993 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
994 | } | |
995 | ||
ec6d273d ZX |
996 | #define TSS_IOPB_BASE_OFFSET 0x66 |
997 | #define TSS_BASE_SIZE 0x68 | |
998 | #define TSS_IOPB_SIZE (65536 / 8) | |
999 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1000 | #define RMODE_TSS_SIZE \ |
1001 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1002 | |
37817f29 IE |
1003 | enum { |
1004 | TASK_SWITCH_CALL = 0, | |
1005 | TASK_SWITCH_IRET = 1, | |
1006 | TASK_SWITCH_JMP = 2, | |
1007 | TASK_SWITCH_GATE = 3, | |
1008 | }; | |
1009 | ||
1371d904 | 1010 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1011 | #define HF_HIF_MASK (1 << 1) |
1012 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1013 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1014 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1015 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
1371d904 | 1016 | |
4ecac3fd AK |
1017 | /* |
1018 | * Hardware virtualization extension instructions may fault if a | |
1019 | * reboot turns off virtualization while processes are running. | |
1020 | * Trap the fault and ignore the instruction if that happens. | |
1021 | */ | |
b7c4145b | 1022 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1023 | |
5e520e62 | 1024 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1025 | "666: " insn "\n\t" \ |
b7c4145b | 1026 | "668: \n\t" \ |
18b13e54 | 1027 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1028 | "667: \n\t" \ |
5e520e62 | 1029 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1030 | "cmpb $0, kvm_rebooting \n\t" \ |
1031 | "jne 668b \n\t" \ | |
8ceed347 | 1032 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1033 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1034 | ".popsection \n\t" \ |
3ee89722 | 1035 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1036 | |
5e520e62 AK |
1037 | #define __kvm_handle_fault_on_reboot(insn) \ |
1038 | ____kvm_handle_fault_on_reboot(insn, "") | |
1039 | ||
e930bffe AA |
1040 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1041 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1042 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
e930bffe | 1043 | int kvm_age_hva(struct kvm *kvm, unsigned long hva); |
8ee53820 | 1044 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1045 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
82725b20 | 1046 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu); |
c7c9c56c | 1047 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1048 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1049 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1050 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
66450a21 | 1051 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu); |
e930bffe | 1052 | |
18863bdd | 1053 | void kvm_define_shared_msr(unsigned index, u32 msr); |
d5696725 | 1054 | void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1055 | |
f92653ee JK |
1056 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1057 | ||
af585b92 GN |
1058 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1059 | struct kvm_async_pf *work); | |
1060 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1061 | struct kvm_async_pf *work); | |
56028d08 GN |
1062 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1063 | struct kvm_async_pf *work); | |
7c90705b | 1064 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1065 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1066 | ||
db8fcefa AP |
1067 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
1068 | ||
f5132b01 GN |
1069 | int kvm_is_in_guest(void); |
1070 | ||
1071 | void kvm_pmu_init(struct kvm_vcpu *vcpu); | |
1072 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu); | |
1073 | void kvm_pmu_reset(struct kvm_vcpu *vcpu); | |
1074 | void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu); | |
1075 | bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr); | |
1076 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
afd80d85 | 1077 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
f5132b01 GN |
1078 | int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); |
1079 | void kvm_handle_pmu_event(struct kvm_vcpu *vcpu); | |
1080 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu); | |
1081 | ||
1965aae3 | 1082 | #endif /* _ASM_X86_KVM_HOST_H */ |