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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
87276880 | 27 | #include <linux/irqbypass.h> |
5c919412 | 28 | #include <linux/hyperv.h> |
34c16eec | 29 | |
50d0a0f9 | 30 | #include <asm/pvclock-abi.h> |
e01a1b57 | 31 | #include <asm/desc.h> |
0bed3b56 | 32 | #include <asm/mtrr.h> |
9962d032 | 33 | #include <asm/msr-index.h> |
3ee89722 | 34 | #include <asm/asm.h> |
e01a1b57 | 35 | |
cbf64358 | 36 | #define KVM_MAX_VCPUS 255 |
a59cb29e | 37 | #define KVM_SOFT_MAX_VCPUS 160 |
1d4e7e3c | 38 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
39 | /* memory slots that are not exposed to userspace */ |
40 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 41 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 42 | |
69a9f69b | 43 | #define KVM_PIO_PAGE_OFFSET 1 |
542472b5 | 44 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
920552b2 | 45 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
69a9f69b | 46 | |
8175e5b7 AG |
47 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
48 | ||
cfec82cb JR |
49 | #define CR0_RESERVED_BITS \ |
50 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
51 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
52 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
53 | ||
346874c9 | 54 | #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL |
cfaa790a | 55 | #define CR3_PCID_INVD BIT_64(63) |
cfec82cb JR |
56 | #define CR4_RESERVED_BITS \ |
57 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
58 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 59 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 60 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
56d6efc2 | 61 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP)) |
cfec82cb JR |
62 | |
63 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
64 | ||
65 | ||
cd6e8f87 | 66 | |
cd6e8f87 | 67 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
68 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
69 | ||
cd6e8f87 ZX |
70 | #define UNMAPPED_GVA (~(gpa_t)0) |
71 | ||
ec04b260 | 72 | /* KVM Hugepage definitions for x86 */ |
04326caa | 73 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
74 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
75 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
76 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
77 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
78 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 79 | |
6d9d41e5 CD |
80 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
81 | { | |
82 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
83 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
84 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
85 | } | |
86 | ||
d657a98e ZX |
87 | #define KVM_PERMILLE_MMU_PAGES 20 |
88 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
89 | #define KVM_MMU_HASH_SHIFT 10 |
90 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
91 | #define KVM_MIN_FREE_MMU_PAGES 5 |
92 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 93 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 94 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 95 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 96 | |
af585b92 GN |
97 | #define ASYNC_PF_PER_VCPU 64 |
98 | ||
5fdbf976 | 99 | enum kvm_reg { |
2b3ccfa0 ZX |
100 | VCPU_REGS_RAX = 0, |
101 | VCPU_REGS_RCX = 1, | |
102 | VCPU_REGS_RDX = 2, | |
103 | VCPU_REGS_RBX = 3, | |
104 | VCPU_REGS_RSP = 4, | |
105 | VCPU_REGS_RBP = 5, | |
106 | VCPU_REGS_RSI = 6, | |
107 | VCPU_REGS_RDI = 7, | |
108 | #ifdef CONFIG_X86_64 | |
109 | VCPU_REGS_R8 = 8, | |
110 | VCPU_REGS_R9 = 9, | |
111 | VCPU_REGS_R10 = 10, | |
112 | VCPU_REGS_R11 = 11, | |
113 | VCPU_REGS_R12 = 12, | |
114 | VCPU_REGS_R13 = 13, | |
115 | VCPU_REGS_R14 = 14, | |
116 | VCPU_REGS_R15 = 15, | |
117 | #endif | |
5fdbf976 | 118 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
119 | NR_VCPU_REGS |
120 | }; | |
121 | ||
6de4f3ad AK |
122 | enum kvm_reg_ex { |
123 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 124 | VCPU_EXREG_CR3, |
6de12732 | 125 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 126 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
127 | }; |
128 | ||
2b3ccfa0 | 129 | enum { |
81609e3e | 130 | VCPU_SREG_ES, |
2b3ccfa0 | 131 | VCPU_SREG_CS, |
81609e3e | 132 | VCPU_SREG_SS, |
2b3ccfa0 | 133 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
134 | VCPU_SREG_FS, |
135 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
136 | VCPU_SREG_TR, |
137 | VCPU_SREG_LDTR, | |
138 | }; | |
139 | ||
56e82318 | 140 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 141 | |
d657a98e ZX |
142 | #define KVM_NR_MEM_OBJS 40 |
143 | ||
42dbaa5a JK |
144 | #define KVM_NR_DB_REGS 4 |
145 | ||
146 | #define DR6_BD (1 << 13) | |
147 | #define DR6_BS (1 << 14) | |
6f43ed01 NA |
148 | #define DR6_RTM (1 << 16) |
149 | #define DR6_FIXED_1 0xfffe0ff0 | |
150 | #define DR6_INIT 0xffff0ff0 | |
151 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
152 | |
153 | #define DR7_BP_EN_MASK 0x000000ff | |
154 | #define DR7_GE (1 << 9) | |
155 | #define DR7_GD (1 << 13) | |
156 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 157 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 158 | |
c205fb7d NA |
159 | #define PFERR_PRESENT_BIT 0 |
160 | #define PFERR_WRITE_BIT 1 | |
161 | #define PFERR_USER_BIT 2 | |
162 | #define PFERR_RSVD_BIT 3 | |
163 | #define PFERR_FETCH_BIT 4 | |
164 | ||
165 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
166 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
167 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
168 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
169 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
170 | ||
41383771 GN |
171 | /* apic attention bits */ |
172 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
173 | /* |
174 | * The following bit is set with PV-EOI, unset on EOI. | |
175 | * We detect PV-EOI changes by guest by comparing | |
176 | * this bit with PV-EOI in guest memory. | |
177 | * See the implementation in apic_update_pv_eoi. | |
178 | */ | |
179 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 180 | |
d84f1e07 FW |
181 | struct kvm_kernel_irq_routing_entry; |
182 | ||
d657a98e ZX |
183 | /* |
184 | * We don't want allocation failures within the mmu code, so we preallocate | |
185 | * enough memory for a single page fault in a cache. | |
186 | */ | |
187 | struct kvm_mmu_memory_cache { | |
188 | int nobjs; | |
189 | void *objects[KVM_NR_MEM_OBJS]; | |
190 | }; | |
191 | ||
d657a98e ZX |
192 | union kvm_mmu_page_role { |
193 | unsigned word; | |
194 | struct { | |
7d76b4d3 | 195 | unsigned level:4; |
5b7e0102 | 196 | unsigned cr4_pae:1; |
7d76b4d3 | 197 | unsigned quadrant:2; |
f6e2c02b | 198 | unsigned direct:1; |
7d76b4d3 | 199 | unsigned access:3; |
2e53d63a | 200 | unsigned invalid:1; |
9645bb56 | 201 | unsigned nxe:1; |
3dbe1415 | 202 | unsigned cr0_wp:1; |
411c588d | 203 | unsigned smep_andnot_wp:1; |
0be0226f | 204 | unsigned smap_andnot_wp:1; |
699023e2 PB |
205 | unsigned :8; |
206 | ||
207 | /* | |
208 | * This is left at the top of the word so that | |
209 | * kvm_memslots_for_spte_role can extract it with a | |
210 | * simple shift. While there is room, give it a whole | |
211 | * byte so it is also faster to load it from memory. | |
212 | */ | |
213 | unsigned smm:8; | |
d657a98e ZX |
214 | }; |
215 | }; | |
216 | ||
217 | struct kvm_mmu_page { | |
218 | struct list_head link; | |
219 | struct hlist_node hash_link; | |
220 | ||
221 | /* | |
222 | * The following two entries are used to key the shadow page in the | |
223 | * hash table. | |
224 | */ | |
225 | gfn_t gfn; | |
226 | union kvm_mmu_page_role role; | |
227 | ||
228 | u64 *spt; | |
229 | /* hold the gfn of each spte inside spt */ | |
230 | gfn_t *gfns; | |
4731d4c7 | 231 | bool unsync; |
0571d366 | 232 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 233 | unsigned int unsync_children; |
67052b35 | 234 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
f6f8adee XG |
235 | |
236 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 237 | unsigned long mmu_valid_gen; |
f6f8adee | 238 | |
0074ff63 | 239 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
240 | |
241 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
242 | /* |
243 | * Used out of the mmu-lock to avoid reading spte values while an | |
244 | * update is in progress; see the comments in __get_spte_lockless(). | |
245 | */ | |
c2a2ac2b XG |
246 | int clear_spte_count; |
247 | #endif | |
248 | ||
0cbf8e43 | 249 | /* Number of writes since the last time traversal visited this page. */ |
a30f47cb | 250 | int write_flooding_count; |
d657a98e ZX |
251 | }; |
252 | ||
1c08364c AK |
253 | struct kvm_pio_request { |
254 | unsigned long count; | |
1c08364c AK |
255 | int in; |
256 | int port; | |
257 | int size; | |
1c08364c AK |
258 | }; |
259 | ||
a0a64f50 XG |
260 | struct rsvd_bits_validate { |
261 | u64 rsvd_bits_mask[2][4]; | |
262 | u64 bad_mt_xwr; | |
263 | }; | |
264 | ||
d657a98e ZX |
265 | /* |
266 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
267 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
268 | * mode. | |
269 | */ | |
270 | struct kvm_mmu { | |
f43addd4 | 271 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 272 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 273 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
274 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
275 | bool prefault); | |
6389ee94 AK |
276 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
277 | struct x86_exception *fault); | |
1871c602 | 278 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 279 | struct x86_exception *exception); |
54987b7a PB |
280 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
281 | struct x86_exception *exception); | |
e8bc217a | 282 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 283 | struct kvm_mmu_page *sp); |
a7052897 | 284 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 285 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 286 | u64 *spte, const void *pte); |
d657a98e ZX |
287 | hpa_t root_hpa; |
288 | int root_level; | |
289 | int shadow_root_level; | |
a770f6f2 | 290 | union kvm_mmu_page_role base_role; |
c5a78f2b | 291 | bool direct_map; |
d657a98e | 292 | |
97d64b78 AK |
293 | /* |
294 | * Bitmap; bit set = permission fault | |
295 | * Byte index: page fault error code [4:1] | |
296 | * Bit index: pte permissions in ACC_* format | |
297 | */ | |
298 | u8 permissions[16]; | |
299 | ||
d657a98e | 300 | u64 *pae_root; |
81407ca5 | 301 | u64 *lm_root; |
c258b62b XG |
302 | |
303 | /* | |
304 | * check zero bits on shadow page table entries, these | |
305 | * bits include not only hardware reserved bits but also | |
306 | * the bits spte never used. | |
307 | */ | |
308 | struct rsvd_bits_validate shadow_zero_check; | |
309 | ||
a0a64f50 | 310 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 311 | |
6fd01b71 AK |
312 | /* |
313 | * Bitmap: bit set = last pte in walk | |
314 | * index[0:1]: level (zero-based) | |
315 | * index[2]: pte.ps | |
316 | */ | |
317 | u8 last_pte_bitmap; | |
318 | ||
2d48a985 JR |
319 | bool nx; |
320 | ||
ff03a073 | 321 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
322 | }; |
323 | ||
f5132b01 GN |
324 | enum pmc_type { |
325 | KVM_PMC_GP = 0, | |
326 | KVM_PMC_FIXED, | |
327 | }; | |
328 | ||
329 | struct kvm_pmc { | |
330 | enum pmc_type type; | |
331 | u8 idx; | |
332 | u64 counter; | |
333 | u64 eventsel; | |
334 | struct perf_event *perf_event; | |
335 | struct kvm_vcpu *vcpu; | |
336 | }; | |
337 | ||
338 | struct kvm_pmu { | |
339 | unsigned nr_arch_gp_counters; | |
340 | unsigned nr_arch_fixed_counters; | |
341 | unsigned available_event_types; | |
342 | u64 fixed_ctr_ctrl; | |
343 | u64 global_ctrl; | |
344 | u64 global_status; | |
345 | u64 global_ovf_ctrl; | |
346 | u64 counter_bitmask[2]; | |
347 | u64 global_ctrl_mask; | |
103af0a9 | 348 | u64 reserved_bits; |
f5132b01 | 349 | u8 version; |
15c7ad51 RR |
350 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
351 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
352 | struct irq_work irq_work; |
353 | u64 reprogram_pmi; | |
354 | }; | |
355 | ||
25462f7f WH |
356 | struct kvm_pmu_ops; |
357 | ||
360b948d PB |
358 | enum { |
359 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 360 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 361 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
362 | }; |
363 | ||
86fd5270 XG |
364 | struct kvm_mtrr_range { |
365 | u64 base; | |
366 | u64 mask; | |
19efffa2 | 367 | struct list_head node; |
86fd5270 XG |
368 | }; |
369 | ||
70109e7d | 370 | struct kvm_mtrr { |
86fd5270 | 371 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 372 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 373 | u64 deftype; |
19efffa2 XG |
374 | |
375 | struct list_head head; | |
70109e7d XG |
376 | }; |
377 | ||
5c919412 AS |
378 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
379 | struct kvm_vcpu_hv_synic { | |
380 | u64 version; | |
381 | u64 control; | |
382 | u64 msg_page; | |
383 | u64 evt_page; | |
384 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
385 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
386 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
387 | DECLARE_BITMAP(vec_bitmap, 256); | |
388 | bool active; | |
389 | }; | |
390 | ||
e83d5887 AS |
391 | /* Hyper-V per vcpu emulation context */ |
392 | struct kvm_vcpu_hv { | |
393 | u64 hv_vapic; | |
9eec50b8 | 394 | s64 runtime_offset; |
5c919412 | 395 | struct kvm_vcpu_hv_synic synic; |
e83d5887 AS |
396 | }; |
397 | ||
ad312c7c | 398 | struct kvm_vcpu_arch { |
5fdbf976 MT |
399 | /* |
400 | * rip and regs accesses must go through | |
401 | * kvm_{register,rip}_{read,write} functions. | |
402 | */ | |
403 | unsigned long regs[NR_VCPU_REGS]; | |
404 | u32 regs_avail; | |
405 | u32 regs_dirty; | |
34c16eec ZX |
406 | |
407 | unsigned long cr0; | |
e8467fda | 408 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
409 | unsigned long cr2; |
410 | unsigned long cr3; | |
411 | unsigned long cr4; | |
fc78f519 | 412 | unsigned long cr4_guest_owned_bits; |
34c16eec | 413 | unsigned long cr8; |
1371d904 | 414 | u32 hflags; |
f6801dff | 415 | u64 efer; |
34c16eec ZX |
416 | u64 apic_base; |
417 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 418 | bool apicv_active; |
6308630b | 419 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 420 | unsigned long apic_attention; |
e1035715 | 421 | int32_t apic_arb_prio; |
34c16eec | 422 | int mp_state; |
34c16eec | 423 | u64 ia32_misc_enable_msr; |
64d60670 | 424 | u64 smbase; |
b209749f | 425 | bool tpr_access_reporting; |
20300099 | 426 | u64 ia32_xss; |
34c16eec | 427 | |
14dfe855 JR |
428 | /* |
429 | * Paging state of the vcpu | |
430 | * | |
431 | * If the vcpu runs in guest mode with two level paging this still saves | |
432 | * the paging mode of the l1 guest. This context is always used to | |
433 | * handle faults. | |
434 | */ | |
34c16eec | 435 | struct kvm_mmu mmu; |
8df25a32 | 436 | |
6539e738 JR |
437 | /* |
438 | * Paging state of an L2 guest (used for nested npt) | |
439 | * | |
440 | * This context will save all necessary information to walk page tables | |
441 | * of the an L2 guest. This context is only initialized for page table | |
442 | * walking and not for faulting since we never handle l2 page faults on | |
443 | * the host. | |
444 | */ | |
445 | struct kvm_mmu nested_mmu; | |
446 | ||
14dfe855 JR |
447 | /* |
448 | * Pointer to the mmu context currently used for | |
449 | * gva_to_gpa translations. | |
450 | */ | |
451 | struct kvm_mmu *walk_mmu; | |
452 | ||
53c07b18 | 453 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
454 | struct kvm_mmu_memory_cache mmu_page_cache; |
455 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
456 | ||
98918833 | 457 | struct fpu guest_fpu; |
c447e76b | 458 | bool eager_fpu; |
2acf923e | 459 | u64 xcr0; |
d7876f1b | 460 | u64 guest_supported_xcr0; |
4344ee98 | 461 | u32 guest_xstate_size; |
34c16eec | 462 | |
34c16eec ZX |
463 | struct kvm_pio_request pio; |
464 | void *pio_data; | |
465 | ||
66fd3f7f GN |
466 | u8 event_exit_inst_len; |
467 | ||
298101da AK |
468 | struct kvm_queued_exception { |
469 | bool pending; | |
470 | bool has_error_code; | |
ce7ddec4 | 471 | bool reinject; |
298101da AK |
472 | u8 nr; |
473 | u32 error_code; | |
474 | } exception; | |
475 | ||
937a7eae AK |
476 | struct kvm_queued_interrupt { |
477 | bool pending; | |
66fd3f7f | 478 | bool soft; |
937a7eae AK |
479 | u8 nr; |
480 | } interrupt; | |
481 | ||
34c16eec ZX |
482 | int halt_request; /* real mode on Intel only */ |
483 | ||
484 | int cpuid_nent; | |
07716717 | 485 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
486 | |
487 | int maxphyaddr; | |
488 | ||
34c16eec ZX |
489 | /* emulate context */ |
490 | ||
491 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
492 | bool emulate_regs_need_sync_to_vcpu; |
493 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 494 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
495 | |
496 | gpa_t time; | |
50d0a0f9 | 497 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 498 | unsigned int hw_tsc_khz; |
0b79459b AH |
499 | struct gfn_to_hva_cache pv_time; |
500 | bool pv_time_enabled; | |
51d59c6b MT |
501 | /* set guest stopped flag in pvclock flags field */ |
502 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
503 | |
504 | struct { | |
505 | u64 msr_val; | |
506 | u64 last_steal; | |
507 | u64 accum_steal; | |
508 | struct gfn_to_hva_cache stime; | |
509 | struct kvm_steal_time steal; | |
510 | } st; | |
511 | ||
1d5f066e | 512 | u64 last_guest_tsc; |
6f526ec5 | 513 | u64 last_host_tsc; |
0dd6a6ed | 514 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
515 | u64 this_tsc_nsec; |
516 | u64 this_tsc_write; | |
0d3da0d2 | 517 | u64 this_tsc_generation; |
c285545f | 518 | bool tsc_catchup; |
cc578287 ZA |
519 | bool tsc_always_catchup; |
520 | s8 virtual_tsc_shift; | |
521 | u32 virtual_tsc_mult; | |
522 | u32 virtual_tsc_khz; | |
ba904635 | 523 | s64 ia32_tsc_adjust_msr; |
ad721883 | 524 | u64 tsc_scaling_ratio; |
3419ffc8 | 525 | |
7460fb4a AK |
526 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
527 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
528 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 529 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 530 | |
70109e7d | 531 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 532 | u64 pat; |
42dbaa5a | 533 | |
360b948d | 534 | unsigned switch_db_regs; |
42dbaa5a JK |
535 | unsigned long db[KVM_NR_DB_REGS]; |
536 | unsigned long dr6; | |
537 | unsigned long dr7; | |
538 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 539 | unsigned long guest_debug_dr7; |
890ca9ae HY |
540 | |
541 | u64 mcg_cap; | |
542 | u64 mcg_status; | |
543 | u64 mcg_ctl; | |
544 | u64 *mce_banks; | |
94fe45da | 545 | |
bebb106a XG |
546 | /* Cache MMIO info */ |
547 | u64 mmio_gva; | |
548 | unsigned access; | |
549 | gfn_t mmio_gfn; | |
56f17dd3 | 550 | u64 mmio_gen; |
bebb106a | 551 | |
f5132b01 GN |
552 | struct kvm_pmu pmu; |
553 | ||
94fe45da | 554 | /* used for guest single stepping over the given code position */ |
94fe45da | 555 | unsigned long singlestep_rip; |
f92653ee | 556 | |
e83d5887 | 557 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
558 | |
559 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 560 | |
1cb3f3ae XG |
561 | unsigned long last_retry_eip; |
562 | unsigned long last_retry_addr; | |
563 | ||
af585b92 GN |
564 | struct { |
565 | bool halted; | |
566 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
567 | struct gfn_to_hva_cache data; |
568 | u64 msr_val; | |
7c90705b | 569 | u32 id; |
6adba527 | 570 | bool send_user_only; |
af585b92 | 571 | } apf; |
2b036c6b BO |
572 | |
573 | /* OSVW MSRs (AMD only) */ | |
574 | struct { | |
575 | u64 length; | |
576 | u64 status; | |
577 | } osvw; | |
ae7a2a3f MT |
578 | |
579 | struct { | |
580 | u64 msr_val; | |
581 | struct gfn_to_hva_cache data; | |
582 | } pv_eoi; | |
93c05d3e XG |
583 | |
584 | /* | |
585 | * Indicate whether the access faults on its page table in guest | |
586 | * which is set when fix page fault and used to detect unhandeable | |
587 | * instruction. | |
588 | */ | |
589 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
590 | |
591 | /* set at EPT violation at this point */ | |
592 | unsigned long exit_qualification; | |
6aef266c SV |
593 | |
594 | /* pv related host specific info */ | |
595 | struct { | |
596 | bool pv_unhalted; | |
597 | } pv; | |
7543a635 SR |
598 | |
599 | int pending_ioapic_eoi; | |
1c1a9ce9 | 600 | int pending_external_vector; |
34c16eec ZX |
601 | }; |
602 | ||
db3fe4eb | 603 | struct kvm_lpage_info { |
db3fe4eb TY |
604 | int write_count; |
605 | }; | |
606 | ||
607 | struct kvm_arch_memory_slot { | |
d89cc617 | 608 | unsigned long *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
609 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
610 | }; | |
611 | ||
3548a259 RK |
612 | /* |
613 | * We use as the mode the number of bits allocated in the LDR for the | |
614 | * logical processor ID. It happens that these are all powers of two. | |
615 | * This makes it is very easy to detect cases where the APICs are | |
616 | * configured for multiple modes; in that case, we cannot use the map and | |
617 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
618 | */ | |
619 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
620 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
621 | #define KVM_APIC_MODE_X2APIC 16 | |
622 | ||
1e08ec4a GN |
623 | struct kvm_apic_map { |
624 | struct rcu_head rcu; | |
3548a259 | 625 | u8 mode; |
1e08ec4a GN |
626 | struct kvm_lapic *phys_map[256]; |
627 | /* first index is cluster id second is cpu id in a cluster */ | |
628 | struct kvm_lapic *logical_map[16][16]; | |
629 | }; | |
630 | ||
e83d5887 AS |
631 | /* Hyper-V emulation context */ |
632 | struct kvm_hv { | |
633 | u64 hv_guest_os_id; | |
634 | u64 hv_hypercall; | |
635 | u64 hv_tsc_page; | |
e7d9513b AS |
636 | |
637 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
638 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
639 | u64 hv_crash_ctl; | |
e83d5887 AS |
640 | }; |
641 | ||
fef9cce0 | 642 | struct kvm_arch { |
49d5ca26 | 643 | unsigned int n_used_mmu_pages; |
f05e70ac | 644 | unsigned int n_requested_mmu_pages; |
39de71ec | 645 | unsigned int n_max_mmu_pages; |
332b207d | 646 | unsigned int indirect_shadow_pages; |
5304b8d3 | 647 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
648 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
649 | /* | |
650 | * Hash table of struct kvm_mmu_page. | |
651 | */ | |
652 | struct list_head active_mmu_pages; | |
365c8868 XG |
653 | struct list_head zapped_obsolete_pages; |
654 | ||
4d5c5d0f | 655 | struct list_head assigned_dev_head; |
19de40a8 | 656 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 657 | bool iommu_noncoherent; |
e0f0bbc5 AW |
658 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
659 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
660 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
661 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
662 | struct kvm_pic *vpic; |
663 | struct kvm_ioapic *vioapic; | |
7837699f | 664 | struct kvm_pit *vpit; |
42720138 | 665 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
666 | struct mutex apic_map_lock; |
667 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 668 | |
bfc6d222 | 669 | unsigned int tss_addr; |
c24ae0dc | 670 | bool apic_access_page_done; |
18068523 GOC |
671 | |
672 | gpa_t wall_clock; | |
b7ebfb05 | 673 | |
b7ebfb05 | 674 | bool ept_identity_pagetable_done; |
b927a3ce | 675 | gpa_t ept_identity_map_addr; |
5550af4d SY |
676 | |
677 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 678 | s64 kvmclock_offset; |
038f8c11 | 679 | raw_spinlock_t tsc_write_lock; |
f38e098f | 680 | u64 last_tsc_nsec; |
f38e098f | 681 | u64 last_tsc_write; |
5d3cb0f6 | 682 | u32 last_tsc_khz; |
e26101b1 ZA |
683 | u64 cur_tsc_nsec; |
684 | u64 cur_tsc_write; | |
685 | u64 cur_tsc_offset; | |
0d3da0d2 | 686 | u64 cur_tsc_generation; |
b48aa97e | 687 | int nr_vcpus_matched_tsc; |
ffde22ac | 688 | |
d828199e MT |
689 | spinlock_t pvclock_gtod_sync_lock; |
690 | bool use_master_clock; | |
691 | u64 master_kernel_ns; | |
692 | cycle_t master_cycle_now; | |
7e44e449 | 693 | struct delayed_work kvmclock_update_work; |
332967a3 | 694 | struct delayed_work kvmclock_sync_work; |
d828199e | 695 | |
ffde22ac | 696 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 697 | |
6ef768fa PB |
698 | /* reads protected by irq_srcu, writes by irq_lock */ |
699 | struct hlist_head mask_notifier_list; | |
700 | ||
e83d5887 | 701 | struct kvm_hv hyperv; |
b034cf01 XG |
702 | |
703 | #ifdef CONFIG_KVM_MMU_AUDIT | |
704 | int audit_point; | |
705 | #endif | |
54750f2c MT |
706 | |
707 | bool boot_vcpu_runs_old_kvmclock; | |
d71ba788 | 708 | u32 bsp_vcpu_id; |
90de4a18 NA |
709 | |
710 | u64 disabled_quirks; | |
49df6397 SR |
711 | |
712 | bool irqchip_split; | |
b053b2ae | 713 | u8 nr_reserved_ioapic_pins; |
d69fb81f ZX |
714 | }; |
715 | ||
0711456c ZX |
716 | struct kvm_vm_stat { |
717 | u32 mmu_shadow_zapped; | |
718 | u32 mmu_pte_write; | |
719 | u32 mmu_pte_updated; | |
720 | u32 mmu_pde_zapped; | |
721 | u32 mmu_flooded; | |
722 | u32 mmu_recycled; | |
dfc5aa00 | 723 | u32 mmu_cache_miss; |
4731d4c7 | 724 | u32 mmu_unsync; |
0711456c | 725 | u32 remote_tlb_flush; |
05da4558 | 726 | u32 lpages; |
0711456c ZX |
727 | }; |
728 | ||
77b4c255 ZX |
729 | struct kvm_vcpu_stat { |
730 | u32 pf_fixed; | |
731 | u32 pf_guest; | |
732 | u32 tlb_flush; | |
733 | u32 invlpg; | |
734 | ||
735 | u32 exits; | |
736 | u32 io_exits; | |
737 | u32 mmio_exits; | |
738 | u32 signal_exits; | |
739 | u32 irq_window_exits; | |
f08864b4 | 740 | u32 nmi_window_exits; |
77b4c255 | 741 | u32 halt_exits; |
f7819512 | 742 | u32 halt_successful_poll; |
62bea5bf | 743 | u32 halt_attempted_poll; |
77b4c255 ZX |
744 | u32 halt_wakeup; |
745 | u32 request_irq_exits; | |
746 | u32 irq_exits; | |
747 | u32 host_state_reload; | |
748 | u32 efer_reload; | |
749 | u32 fpu_reload; | |
750 | u32 insn_emulation; | |
751 | u32 insn_emulation_fail; | |
f11c3a8d | 752 | u32 hypercalls; |
fa89a817 | 753 | u32 irq_injections; |
c4abb7c9 | 754 | u32 nmi_injections; |
77b4c255 | 755 | }; |
ad312c7c | 756 | |
8a76d7f2 JR |
757 | struct x86_instruction_info; |
758 | ||
8fe8ab46 WA |
759 | struct msr_data { |
760 | bool host_initiated; | |
761 | u32 index; | |
762 | u64 data; | |
763 | }; | |
764 | ||
cb5281a5 PB |
765 | struct kvm_lapic_irq { |
766 | u32 vector; | |
b7cb2231 PB |
767 | u16 delivery_mode; |
768 | u16 dest_mode; | |
769 | bool level; | |
770 | u16 trig_mode; | |
cb5281a5 PB |
771 | u32 shorthand; |
772 | u32 dest_id; | |
93bbf0b8 | 773 | bool msi_redir_hint; |
cb5281a5 PB |
774 | }; |
775 | ||
ea4a5ff8 ZX |
776 | struct kvm_x86_ops { |
777 | int (*cpu_has_kvm_support)(void); /* __init */ | |
778 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
779 | int (*hardware_enable)(void); |
780 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
781 | void (*check_processor_compatibility)(void *rtn); |
782 | int (*hardware_setup)(void); /* __init */ | |
783 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 784 | bool (*cpu_has_accelerated_tpr)(void); |
6d396b55 | 785 | bool (*cpu_has_high_real_mode_segbase)(void); |
0e851880 | 786 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
787 | |
788 | /* Create, but do not attach this VCPU */ | |
789 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
790 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 791 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
792 | |
793 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
794 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
795 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 796 | |
a96036b8 | 797 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 798 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 799 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
800 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
801 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
802 | struct kvm_segment *var, int seg); | |
2e4d2653 | 803 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
804 | void (*set_segment)(struct kvm_vcpu *vcpu, |
805 | struct kvm_segment *var, int seg); | |
806 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 807 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 808 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
809 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
810 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
811 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 812 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 813 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
814 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
815 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
816 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
817 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
818 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
819 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 820 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 821 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 822 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
823 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
824 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
0fdd74f7 | 825 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 826 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
827 | |
828 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 829 | |
851ba692 AK |
830 | void (*run)(struct kvm_vcpu *vcpu); |
831 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 832 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 833 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 834 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
835 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
836 | unsigned char *hypercall_addr); | |
66fd3f7f | 837 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 838 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 839 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
840 | bool has_error_code, u32 error_code, |
841 | bool reinject); | |
b463a6f7 | 842 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 843 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 844 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
845 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
846 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
847 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
848 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 849 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
d62caabb AS |
850 | bool (*get_enable_apicv)(void); |
851 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); | |
c7c9c56c YZ |
852 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
853 | void (*hwapic_isr_update)(struct kvm *kvm, int isr); | |
6308630b | 854 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d14695f | 855 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
4256f43f | 856 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d YZ |
857 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
858 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 859 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 860 | int (*get_tdp_level)(void); |
4b12f0de | 861 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 862 | int (*get_lpage_level)(void); |
4e47c7a6 | 863 | bool (*rdtscp_supported)(void); |
ad756a16 | 864 | bool (*invpcid_supported)(void); |
58ea6767 | 865 | void (*adjust_tsc_offset_guest)(struct kvm_vcpu *vcpu, s64 adjustment); |
344f414f | 866 | |
1c97f0a0 JR |
867 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
868 | ||
d4330ef2 JR |
869 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
870 | ||
f5f48ee1 SY |
871 | bool (*has_wbinvd_exit)(void); |
872 | ||
ba904635 | 873 | u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
874 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
875 | ||
886b470c | 876 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc); |
857e4099 | 877 | |
586f9607 | 878 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
879 | |
880 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
881 | struct x86_instruction_info *info, | |
882 | enum x86_intercept_stage stage); | |
a547c6db | 883 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 884 | bool (*mpx_supported)(void); |
55412b2e | 885 | bool (*xsaves_supported)(void); |
b6b8a145 JK |
886 | |
887 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ae97a3b8 RK |
888 | |
889 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
890 | |
891 | /* | |
892 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
893 | * be valid if the specific arch has hardware-accelerated dirty logging | |
894 | * mechanism. Currently only for PML on VMX. | |
895 | * | |
896 | * - slot_enable_log_dirty: | |
897 | * called when enabling log dirty mode for the slot. | |
898 | * - slot_disable_log_dirty: | |
899 | * called when disabling log dirty mode for the slot. | |
900 | * also called when slot is created with log dirty disabled. | |
901 | * - flush_log_dirty: | |
902 | * called before reporting dirty_bitmap to userspace. | |
903 | * - enable_log_dirty_pt_masked: | |
904 | * called when reenabling log dirty for the GFNs in the mask after | |
905 | * corresponding bits are cleared in slot->dirty_bitmap. | |
906 | */ | |
907 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
908 | struct kvm_memory_slot *slot); | |
909 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
910 | struct kvm_memory_slot *slot); | |
911 | void (*flush_log_dirty)(struct kvm *kvm); | |
912 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
913 | struct kvm_memory_slot *slot, | |
914 | gfn_t offset, unsigned long mask); | |
25462f7f WH |
915 | /* pmu operations of sub-arch */ |
916 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 | 917 | |
bf9f6ac8 FW |
918 | /* |
919 | * Architecture specific hooks for vCPU blocking due to | |
920 | * HLT instruction. | |
921 | * Returns for .pre_block(): | |
922 | * - 0 means continue to block the vCPU. | |
923 | * - 1 means we cannot block the vCPU since some event | |
924 | * happens during this period, such as, 'ON' bit in | |
925 | * posted-interrupts descriptor is set. | |
926 | */ | |
927 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
928 | void (*post_block)(struct kvm_vcpu *vcpu); | |
efc64404 FW |
929 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
930 | uint32_t guest_irq, bool set); | |
ea4a5ff8 ZX |
931 | }; |
932 | ||
af585b92 | 933 | struct kvm_arch_async_pf { |
7c90705b | 934 | u32 token; |
af585b92 | 935 | gfn_t gfn; |
fb67e14f | 936 | unsigned long cr3; |
c4806acd | 937 | bool direct_map; |
af585b92 GN |
938 | }; |
939 | ||
97896d04 ZX |
940 | extern struct kvm_x86_ops *kvm_x86_ops; |
941 | ||
54f1585a ZX |
942 | int kvm_mmu_module_init(void); |
943 | void kvm_mmu_module_exit(void); | |
944 | ||
945 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
946 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 947 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
7b52345e | 948 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 949 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a | 950 | |
8a3c1a33 | 951 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
952 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
953 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 954 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 955 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
956 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
957 | struct kvm_memory_slot *memslot); | |
958 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
959 | struct kvm_memory_slot *memslot); | |
960 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
961 | struct kvm_memory_slot *memslot); | |
962 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
963 | struct kvm_memory_slot *slot, | |
964 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 965 | void kvm_mmu_zap_all(struct kvm *kvm); |
54bf36aa | 966 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); |
3ad82a7e | 967 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
968 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
969 | ||
ff03a073 | 970 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 971 | |
3200f405 | 972 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 973 | const void *val, int bytes); |
2f333bcb | 974 | |
6ef768fa PB |
975 | struct kvm_irq_mask_notifier { |
976 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
977 | int irq; | |
978 | struct hlist_node link; | |
979 | }; | |
980 | ||
981 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
982 | struct kvm_irq_mask_notifier *kimn); | |
983 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
984 | struct kvm_irq_mask_notifier *kimn); | |
985 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
986 | bool mask); | |
987 | ||
2f333bcb | 988 | extern bool tdp_enabled; |
9f811285 | 989 | |
a3e06bbe LJ |
990 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
991 | ||
92a1f12d JR |
992 | /* control of guest tsc rate supported? */ |
993 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
994 | /* maximum supported tsc_khz for guests */ |
995 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
996 | /* number of bits of the fractional part of the TSC scaling ratio */ |
997 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
998 | /* maximum allowed value of TSC scaling ratio */ | |
999 | extern u64 kvm_max_tsc_scaling_ratio; | |
92a1f12d | 1000 | |
54f1585a | 1001 | enum emulation_result { |
ac0a48c3 PB |
1002 | EMULATE_DONE, /* no further processing */ |
1003 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
1004 | EMULATE_FAIL, /* can't emulate this instruction */ |
1005 | }; | |
1006 | ||
571008da SY |
1007 | #define EMULTYPE_NO_DECODE (1 << 0) |
1008 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1009 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 1010 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 1011 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
1012 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
1013 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
1014 | |
1015 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
1016 | int emulation_type) | |
1017 | { | |
dc25e89e | 1018 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
1019 | } |
1020 | ||
f2b4b7dd | 1021 | void kvm_enable_efer_bits(u64); |
384bb783 | 1022 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 1023 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1024 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
1025 | |
1026 | struct x86_emulate_ctxt; | |
1027 | ||
cf8f70bf | 1028 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
1029 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
1030 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
5cb56059 | 1031 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1032 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1033 | |
3e6e0aab | 1034 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1035 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1036 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1037 | |
7f3d35fd KW |
1038 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1039 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1040 | |
49a9b07e | 1041 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1042 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1043 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1044 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1045 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1046 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1047 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1048 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1049 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1050 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1051 | |
609e36d3 | 1052 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1053 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1054 | |
91586a3b JK |
1055 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1056 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1057 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1058 | |
298101da AK |
1059 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1060 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1061 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1062 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1063 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1064 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1065 | gfn_t gfn, void *data, int offset, int len, | |
1066 | u32 access); | |
0a79b009 | 1067 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1068 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1069 | |
1a577b72 MT |
1070 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1071 | int irq_source_id, int level) | |
1072 | { | |
1073 | /* Logical OR for level trig interrupt */ | |
1074 | if (level) | |
1075 | __set_bit(irq_source_id, irq_state); | |
1076 | else | |
1077 | __clear_bit(irq_source_id, irq_state); | |
1078 | ||
1079 | return !!(*irq_state); | |
1080 | } | |
1081 | ||
1082 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1083 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1084 | |
3419ffc8 SY |
1085 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1086 | ||
54f1585a | 1087 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 1088 | const u8 *new, int bytes); |
1cb3f3ae | 1089 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1090 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1091 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1092 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1093 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1094 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
54987b7a PB |
1095 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1096 | struct x86_exception *exception); | |
ab9ae313 AK |
1097 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1098 | struct x86_exception *exception); | |
1099 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1100 | struct x86_exception *exception); | |
1101 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1102 | struct x86_exception *exception); | |
1103 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1104 | struct x86_exception *exception); | |
54f1585a | 1105 | |
d62caabb AS |
1106 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); |
1107 | ||
54f1585a ZX |
1108 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1109 | ||
dc25e89e AP |
1110 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
1111 | void *insn, int insn_len); | |
a7052897 | 1112 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 1113 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 1114 | |
18552672 | 1115 | void kvm_enable_tdp(void); |
5f4cb662 | 1116 | void kvm_disable_tdp(void); |
18552672 | 1117 | |
54987b7a PB |
1118 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1119 | struct x86_exception *exception) | |
e459e322 XG |
1120 | { |
1121 | return gpa; | |
1122 | } | |
1123 | ||
ec6d273d ZX |
1124 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1125 | { | |
1126 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1127 | ||
1128 | return (struct kvm_mmu_page *)page_private(page); | |
1129 | } | |
1130 | ||
d6e88aec | 1131 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1132 | { |
1133 | u16 ldt; | |
1134 | asm("sldt %0" : "=g"(ldt)); | |
1135 | return ldt; | |
1136 | } | |
1137 | ||
d6e88aec | 1138 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1139 | { |
1140 | asm("lldt %0" : : "rm"(sel)); | |
1141 | } | |
ec6d273d | 1142 | |
ec6d273d ZX |
1143 | #ifdef CONFIG_X86_64 |
1144 | static inline unsigned long read_msr(unsigned long msr) | |
1145 | { | |
1146 | u64 value; | |
1147 | ||
1148 | rdmsrl(msr, value); | |
1149 | return value; | |
1150 | } | |
1151 | #endif | |
1152 | ||
ec6d273d ZX |
1153 | static inline u32 get_rdx_init_val(void) |
1154 | { | |
1155 | return 0x600; /* P6 family */ | |
1156 | } | |
1157 | ||
c1a5d4f9 AK |
1158 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1159 | { | |
1160 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1161 | } | |
1162 | ||
854e8bb1 NA |
1163 | static inline u64 get_canonical(u64 la) |
1164 | { | |
1165 | return ((int64_t)la << 16) >> 16; | |
1166 | } | |
1167 | ||
1168 | static inline bool is_noncanonical_address(u64 la) | |
1169 | { | |
1170 | #ifdef CONFIG_X86_64 | |
1171 | return get_canonical(la) != la; | |
1172 | #else | |
1173 | return false; | |
1174 | #endif | |
1175 | } | |
1176 | ||
ec6d273d ZX |
1177 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1178 | #define TSS_BASE_SIZE 0x68 | |
1179 | #define TSS_IOPB_SIZE (65536 / 8) | |
1180 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1181 | #define RMODE_TSS_SIZE \ |
1182 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1183 | |
37817f29 IE |
1184 | enum { |
1185 | TASK_SWITCH_CALL = 0, | |
1186 | TASK_SWITCH_IRET = 1, | |
1187 | TASK_SWITCH_JMP = 2, | |
1188 | TASK_SWITCH_GATE = 3, | |
1189 | }; | |
1190 | ||
1371d904 | 1191 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1192 | #define HF_HIF_MASK (1 << 1) |
1193 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1194 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1195 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1196 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1197 | #define HF_SMM_MASK (1 << 6) |
1198 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1199 | |
699023e2 PB |
1200 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1201 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1202 | ||
1203 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1204 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1205 | |
4ecac3fd AK |
1206 | /* |
1207 | * Hardware virtualization extension instructions may fault if a | |
1208 | * reboot turns off virtualization while processes are running. | |
1209 | * Trap the fault and ignore the instruction if that happens. | |
1210 | */ | |
b7c4145b | 1211 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1212 | |
5e520e62 | 1213 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1214 | "666: " insn "\n\t" \ |
b7c4145b | 1215 | "668: \n\t" \ |
18b13e54 | 1216 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1217 | "667: \n\t" \ |
5e520e62 | 1218 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1219 | "cmpb $0, kvm_rebooting \n\t" \ |
1220 | "jne 668b \n\t" \ | |
8ceed347 | 1221 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1222 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1223 | ".popsection \n\t" \ |
3ee89722 | 1224 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1225 | |
5e520e62 AK |
1226 | #define __kvm_handle_fault_on_reboot(insn) \ |
1227 | ____kvm_handle_fault_on_reboot(insn, "") | |
1228 | ||
e930bffe AA |
1229 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1230 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1231 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1232 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1233 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1234 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1235 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1236 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1237 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1238 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1239 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1240 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
fe71557a TC |
1241 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
1242 | unsigned long address); | |
e930bffe | 1243 | |
18863bdd | 1244 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1245 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1246 | |
35181e86 | 1247 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1248 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1249 | |
82b32774 | 1250 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1251 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1252 | ||
af585b92 GN |
1253 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1254 | struct kvm_async_pf *work); | |
1255 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1256 | struct kvm_async_pf *work); | |
56028d08 GN |
1257 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1258 | struct kvm_async_pf *work); | |
7c90705b | 1259 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1260 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1261 | ||
db8fcefa AP |
1262 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
1263 | ||
f5132b01 GN |
1264 | int kvm_is_in_guest(void); |
1265 | ||
1d8007bd PB |
1266 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); |
1267 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
d71ba788 PB |
1268 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1269 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1270 | |
8feb4a04 FW |
1271 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1272 | struct kvm_vcpu **dest_vcpu); | |
1273 | ||
d84f1e07 FW |
1274 | void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e, |
1275 | struct kvm_lapic_irq *irq); | |
197a4f4b | 1276 | |
3217f7c2 CD |
1277 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {} |
1278 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {} | |
1279 | ||
1965aae3 | 1280 | #endif /* _ASM_X86_KVM_HOST_H */ |