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a656c8ef 1/*
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2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This header defines architecture specific interfaces, x86 version
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See
7 * the COPYING file in the top-level directory.
8 *
9 */
10
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11#ifndef _ASM_X86_KVM_HOST_H
12#define _ASM_X86_KVM_HOST_H
043405e1 13
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14#include <linux/types.h>
15#include <linux/mm.h>
e930bffe 16#include <linux/mmu_notifier.h>
229456fc 17#include <linux/tracepoint.h>
f5f48ee1 18#include <linux/cpumask.h>
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19
20#include <linux/kvm.h>
21#include <linux/kvm_para.h>
edf88417 22#include <linux/kvm_types.h>
34c16eec 23
50d0a0f9 24#include <asm/pvclock-abi.h>
e01a1b57 25#include <asm/desc.h>
0bed3b56 26#include <asm/mtrr.h>
9962d032 27#include <asm/msr-index.h>
e01a1b57 28
0680fe52 29#define KVM_MAX_VCPUS 64
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30#define KVM_MEMORY_SLOTS 32
31/* memory slots that does not exposed to userspace */
32#define KVM_PRIVATE_MEM_SLOTS 4
cef4dea0 33#define KVM_MMIO_SIZE 16
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34
35#define KVM_PIO_PAGE_OFFSET 1
542472b5 36#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
69a9f69b 37
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38#define CR0_RESERVED_BITS \
39 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
40 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
41 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
42
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43#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
44#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
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45#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \
46 0xFFFFFF0000000000ULL)
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47#define CR4_RESERVED_BITS \
48 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
49 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
50 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
51 | X86_CR4_OSXSAVE \
52 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
53
54#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
55
56
cd6e8f87 57
cd6e8f87 58#define INVALID_PAGE (~(hpa_t)0)
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59#define VALID_PAGE(x) ((x) != INVALID_PAGE)
60
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61#define UNMAPPED_GVA (~(gpa_t)0)
62
ec04b260 63/* KVM Hugepage definitions for x86 */
04326caa 64#define KVM_NR_PAGE_SIZES 3
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65#define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
66#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
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67#define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
68#define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
69#define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
05da4558 70
cd6e8f87 71#define DE_VECTOR 0
19bd8afd 72#define DB_VECTOR 1
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73#define BP_VECTOR 3
74#define OF_VECTOR 4
75#define BR_VECTOR 5
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76#define UD_VECTOR 6
77#define NM_VECTOR 7
78#define DF_VECTOR 8
79#define TS_VECTOR 10
80#define NP_VECTOR 11
81#define SS_VECTOR 12
82#define GP_VECTOR 13
83#define PF_VECTOR 14
77ab6db0 84#define MF_VECTOR 16
53371b50 85#define MC_VECTOR 18
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86
87#define SELECTOR_TI_MASK (1 << 2)
88#define SELECTOR_RPL_MASK 0x03
89
90#define IOPL_SHIFT 12
91
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92#define KVM_PERMILLE_MMU_PAGES 20
93#define KVM_MIN_ALLOC_MMU_PAGES 64
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94#define KVM_MMU_HASH_SHIFT 10
95#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
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96#define KVM_MIN_FREE_MMU_PAGES 5
97#define KVM_REFILL_PAGES 25
73c1160c 98#define KVM_MAX_CPUID_ENTRIES 80
0bed3b56 99#define KVM_NR_FIXED_MTRR_REGION 88
9ba075a6 100#define KVM_NR_VAR_MTRR 8
d657a98e 101
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102#define ASYNC_PF_PER_VCPU 64
103
e935b837 104extern raw_spinlock_t kvm_lock;
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105extern struct list_head vm_list;
106
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107struct kvm_vcpu;
108struct kvm;
af585b92 109struct kvm_async_pf;
d657a98e 110
5fdbf976 111enum kvm_reg {
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112 VCPU_REGS_RAX = 0,
113 VCPU_REGS_RCX = 1,
114 VCPU_REGS_RDX = 2,
115 VCPU_REGS_RBX = 3,
116 VCPU_REGS_RSP = 4,
117 VCPU_REGS_RBP = 5,
118 VCPU_REGS_RSI = 6,
119 VCPU_REGS_RDI = 7,
120#ifdef CONFIG_X86_64
121 VCPU_REGS_R8 = 8,
122 VCPU_REGS_R9 = 9,
123 VCPU_REGS_R10 = 10,
124 VCPU_REGS_R11 = 11,
125 VCPU_REGS_R12 = 12,
126 VCPU_REGS_R13 = 13,
127 VCPU_REGS_R14 = 14,
128 VCPU_REGS_R15 = 15,
129#endif
5fdbf976 130 VCPU_REGS_RIP,
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131 NR_VCPU_REGS
132};
133
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134enum kvm_reg_ex {
135 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
aff48baa 136 VCPU_EXREG_CR3,
6de12732 137 VCPU_EXREG_RFLAGS,
69c73028 138 VCPU_EXREG_CPL,
2fb92db1 139 VCPU_EXREG_SEGMENTS,
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140};
141
2b3ccfa0 142enum {
81609e3e 143 VCPU_SREG_ES,
2b3ccfa0 144 VCPU_SREG_CS,
81609e3e 145 VCPU_SREG_SS,
2b3ccfa0 146 VCPU_SREG_DS,
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147 VCPU_SREG_FS,
148 VCPU_SREG_GS,
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149 VCPU_SREG_TR,
150 VCPU_SREG_LDTR,
151};
152
56e82318 153#include <asm/kvm_emulate.h>
2b3ccfa0 154
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155#define KVM_NR_MEM_OBJS 40
156
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157#define KVM_NR_DB_REGS 4
158
159#define DR6_BD (1 << 13)
160#define DR6_BS (1 << 14)
161#define DR6_FIXED_1 0xffff0ff0
162#define DR6_VOLATILE 0x0000e00f
163
164#define DR7_BP_EN_MASK 0x000000ff
165#define DR7_GE (1 << 9)
166#define DR7_GD (1 << 13)
167#define DR7_FIXED_1 0x00000400
168#define DR7_VOLATILE 0xffff23ff
169
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170/*
171 * We don't want allocation failures within the mmu code, so we preallocate
172 * enough memory for a single page fault in a cache.
173 */
174struct kvm_mmu_memory_cache {
175 int nobjs;
176 void *objects[KVM_NR_MEM_OBJS];
177};
178
179#define NR_PTE_CHAIN_ENTRIES 5
180
181struct kvm_pte_chain {
182 u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES];
183 struct hlist_node link;
184};
185
186/*
187 * kvm_mmu_page_role, below, is defined as:
188 *
189 * bits 0:3 - total guest paging levels (2-4, or zero for real mode)
190 * bits 4:7 - page table level for this shadow (1-4)
191 * bits 8:9 - page table quadrant for 2-level guests
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192 * bit 16 - direct mapping of virtual to physical mapping at gfn
193 * used for real mode and two-dimensional paging
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194 * bits 17:19 - common access permissions for all ptes in this shadow page
195 */
196union kvm_mmu_page_role {
197 unsigned word;
198 struct {
7d76b4d3 199 unsigned level:4;
5b7e0102 200 unsigned cr4_pae:1;
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201 unsigned quadrant:2;
202 unsigned pad_for_nice_hex_output:6;
f6e2c02b 203 unsigned direct:1;
7d76b4d3 204 unsigned access:3;
2e53d63a 205 unsigned invalid:1;
9645bb56 206 unsigned nxe:1;
3dbe1415 207 unsigned cr0_wp:1;
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208 };
209};
210
211struct kvm_mmu_page {
212 struct list_head link;
213 struct hlist_node hash_link;
214
215 /*
216 * The following two entries are used to key the shadow page in the
217 * hash table.
218 */
219 gfn_t gfn;
220 union kvm_mmu_page_role role;
221
222 u64 *spt;
223 /* hold the gfn of each spte inside spt */
224 gfn_t *gfns;
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225 /*
226 * One bit set per slot which has memory
227 * in this shadow page.
228 */
229 DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
0571d366 230 bool multimapped; /* More than one parent_pte? */
4731d4c7 231 bool unsync;
0571d366 232 int root_count; /* Currently serving as active root */
60c8aec6 233 unsigned int unsync_children;
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234 union {
235 u64 *parent_pte; /* !multimapped */
236 struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */
237 };
0074ff63 238 DECLARE_BITMAP(unsync_child_bitmap, 512);
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239};
240
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241struct kvm_pv_mmu_op_buffer {
242 void *ptr;
243 unsigned len;
244 unsigned processed;
245 char buf[512] __aligned(sizeof(long));
246};
247
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248struct kvm_pio_request {
249 unsigned long count;
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250 int in;
251 int port;
252 int size;
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253};
254
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255/*
256 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level
257 * 32-bit). The kvm_mmu structure abstracts the details of the current mmu
258 * mode.
259 */
260struct kvm_mmu {
261 void (*new_cr3)(struct kvm_vcpu *vcpu);
f43addd4 262 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
5777ed34 263 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
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264 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
265 bool prefault);
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266 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
267 struct x86_exception *fault);
d657a98e 268 void (*free)(struct kvm_vcpu *vcpu);
1871c602 269 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
ab9ae313 270 struct x86_exception *exception);
c30a358d 271 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
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272 void (*prefetch_page)(struct kvm_vcpu *vcpu,
273 struct kvm_mmu_page *page);
e8bc217a 274 int (*sync_page)(struct kvm_vcpu *vcpu,
a4a8e6f7 275 struct kvm_mmu_page *sp);
a7052897 276 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
0f53b5b1 277 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
7c562522 278 u64 *spte, const void *pte);
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279 hpa_t root_hpa;
280 int root_level;
281 int shadow_root_level;
a770f6f2 282 union kvm_mmu_page_role base_role;
c5a78f2b 283 bool direct_map;
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284
285 u64 *pae_root;
81407ca5 286 u64 *lm_root;
82725b20 287 u64 rsvd_bits_mask[2][4];
ff03a073 288
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289 bool nx;
290
ff03a073 291 u64 pdptrs[4]; /* pae */
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292};
293
ad312c7c 294struct kvm_vcpu_arch {
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295 /*
296 * rip and regs accesses must go through
297 * kvm_{register,rip}_{read,write} functions.
298 */
299 unsigned long regs[NR_VCPU_REGS];
300 u32 regs_avail;
301 u32 regs_dirty;
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302
303 unsigned long cr0;
e8467fda 304 unsigned long cr0_guest_owned_bits;
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305 unsigned long cr2;
306 unsigned long cr3;
307 unsigned long cr4;
fc78f519 308 unsigned long cr4_guest_owned_bits;
34c16eec 309 unsigned long cr8;
1371d904 310 u32 hflags;
f6801dff 311 u64 efer;
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312 u64 apic_base;
313 struct kvm_lapic *apic; /* kernel irqchip context */
e1035715 314 int32_t apic_arb_prio;
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315 int mp_state;
316 int sipi_vector;
317 u64 ia32_misc_enable_msr;
b209749f 318 bool tpr_access_reporting;
34c16eec 319
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320 /*
321 * Paging state of the vcpu
322 *
323 * If the vcpu runs in guest mode with two level paging this still saves
324 * the paging mode of the l1 guest. This context is always used to
325 * handle faults.
326 */
34c16eec 327 struct kvm_mmu mmu;
8df25a32 328
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329 /*
330 * Paging state of an L2 guest (used for nested npt)
331 *
332 * This context will save all necessary information to walk page tables
333 * of the an L2 guest. This context is only initialized for page table
334 * walking and not for faulting since we never handle l2 page faults on
335 * the host.
336 */
337 struct kvm_mmu nested_mmu;
338
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339 /*
340 * Pointer to the mmu context currently used for
341 * gva_to_gpa translations.
342 */
343 struct kvm_mmu *walk_mmu;
344
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345 /* only needed in kvm_pv_mmu_op() path, but it's hot so
346 * put it here to avoid allocation */
347 struct kvm_pv_mmu_op_buffer mmu_op_buffer;
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348
349 struct kvm_mmu_memory_cache mmu_pte_chain_cache;
350 struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
351 struct kvm_mmu_memory_cache mmu_page_cache;
352 struct kvm_mmu_memory_cache mmu_page_header_cache;
353
354 gfn_t last_pt_write_gfn;
355 int last_pt_write_count;
356 u64 *last_pte_updated;
1b7fcd32 357 gfn_t last_pte_gfn;
34c16eec 358
98918833 359 struct fpu guest_fpu;
2acf923e 360 u64 xcr0;
34c16eec 361
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362 struct kvm_pio_request pio;
363 void *pio_data;
364
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365 u8 event_exit_inst_len;
366
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367 struct kvm_queued_exception {
368 bool pending;
369 bool has_error_code;
ce7ddec4 370 bool reinject;
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371 u8 nr;
372 u32 error_code;
373 } exception;
374
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375 struct kvm_queued_interrupt {
376 bool pending;
66fd3f7f 377 bool soft;
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378 u8 nr;
379 } interrupt;
380
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381 int halt_request; /* real mode on Intel only */
382
383 int cpuid_nent;
07716717 384 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
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385 /* emulate context */
386
387 struct x86_emulate_ctxt emulate_ctxt;
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388 bool emulate_regs_need_sync_to_vcpu;
389 bool emulate_regs_need_sync_from_vcpu;
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390
391 gpa_t time;
50d0a0f9 392 struct pvclock_vcpu_time_info hv_clock;
e48672fa 393 unsigned int hw_tsc_khz;
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394 unsigned int time_offset;
395 struct page *time_page;
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396 u64 last_guest_tsc;
397 u64 last_kernel_ns;
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398 u64 last_tsc_nsec;
399 u64 last_tsc_write;
1e993611 400 u32 virtual_tsc_khz;
c285545f 401 bool tsc_catchup;
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402 u32 tsc_catchup_mult;
403 s8 tsc_catchup_shift;
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404
405 bool nmi_pending;
668f612f 406 bool nmi_injected;
9ba075a6 407
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408 struct mtrr_state_type mtrr_state;
409 u32 pat;
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410
411 int switch_db_regs;
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412 unsigned long db[KVM_NR_DB_REGS];
413 unsigned long dr6;
414 unsigned long dr7;
415 unsigned long eff_db[KVM_NR_DB_REGS];
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416
417 u64 mcg_cap;
418 u64 mcg_status;
419 u64 mcg_ctl;
420 u64 *mce_banks;
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421
422 /* used for guest single stepping over the given code position */
94fe45da 423 unsigned long singlestep_rip;
f92653ee 424
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425 /* fields used by HYPER-V emulation */
426 u64 hv_vapic;
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427
428 cpumask_var_t wbinvd_dirty_mask;
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429
430 struct {
431 bool halted;
432 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
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433 struct gfn_to_hva_cache data;
434 u64 msr_val;
7c90705b 435 u32 id;
6adba527 436 bool send_user_only;
af585b92 437 } apf;
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438};
439
fef9cce0 440struct kvm_arch {
49d5ca26 441 unsigned int n_used_mmu_pages;
f05e70ac 442 unsigned int n_requested_mmu_pages;
39de71ec 443 unsigned int n_max_mmu_pages;
08e850c6 444 atomic_t invlpg_counter;
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445 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
446 /*
447 * Hash table of struct kvm_mmu_page.
448 */
449 struct list_head active_mmu_pages;
4d5c5d0f 450 struct list_head assigned_dev_head;
19de40a8 451 struct iommu_domain *iommu_domain;
522c68c4 452 int iommu_flags;
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453 struct kvm_pic *vpic;
454 struct kvm_ioapic *vioapic;
7837699f 455 struct kvm_pit *vpit;
cc6e462c 456 int vapics_in_nmi_mode;
bfc6d222 457
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458 unsigned int tss_addr;
459 struct page *apic_access_page;
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460
461 gpa_t wall_clock;
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462
463 struct page *ept_identity_pagetable;
464 bool ept_identity_pagetable_done;
b927a3ce 465 gpa_t ept_identity_map_addr;
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466
467 unsigned long irq_sources_bitmap;
afbcf7ab 468 s64 kvmclock_offset;
038f8c11 469 raw_spinlock_t tsc_write_lock;
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470 u64 last_tsc_nsec;
471 u64 last_tsc_offset;
472 u64 last_tsc_write;
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473
474 struct kvm_xen_hvm_config xen_hvm_config;
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475
476 /* fields used by HYPER-V emulation */
477 u64 hv_guest_os_id;
478 u64 hv_hypercall;
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479
480 #ifdef CONFIG_KVM_MMU_AUDIT
481 int audit_point;
482 #endif
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483};
484
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485struct kvm_vm_stat {
486 u32 mmu_shadow_zapped;
487 u32 mmu_pte_write;
488 u32 mmu_pte_updated;
489 u32 mmu_pde_zapped;
490 u32 mmu_flooded;
491 u32 mmu_recycled;
dfc5aa00 492 u32 mmu_cache_miss;
4731d4c7 493 u32 mmu_unsync;
0711456c 494 u32 remote_tlb_flush;
05da4558 495 u32 lpages;
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496};
497
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498struct kvm_vcpu_stat {
499 u32 pf_fixed;
500 u32 pf_guest;
501 u32 tlb_flush;
502 u32 invlpg;
503
504 u32 exits;
505 u32 io_exits;
506 u32 mmio_exits;
507 u32 signal_exits;
508 u32 irq_window_exits;
f08864b4 509 u32 nmi_window_exits;
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510 u32 halt_exits;
511 u32 halt_wakeup;
512 u32 request_irq_exits;
513 u32 irq_exits;
514 u32 host_state_reload;
515 u32 efer_reload;
516 u32 fpu_reload;
517 u32 insn_emulation;
518 u32 insn_emulation_fail;
f11c3a8d 519 u32 hypercalls;
fa89a817 520 u32 irq_injections;
c4abb7c9 521 u32 nmi_injections;
77b4c255 522};
ad312c7c 523
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524struct x86_instruction_info;
525
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526struct kvm_x86_ops {
527 int (*cpu_has_kvm_support)(void); /* __init */
528 int (*disabled_by_bios)(void); /* __init */
10474ae8 529 int (*hardware_enable)(void *dummy);
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530 void (*hardware_disable)(void *dummy);
531 void (*check_processor_compatibility)(void *rtn);
532 int (*hardware_setup)(void); /* __init */
533 void (*hardware_unsetup)(void); /* __exit */
774ead3a 534 bool (*cpu_has_accelerated_tpr)(void);
0e851880 535 void (*cpuid_update)(struct kvm_vcpu *vcpu);
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536
537 /* Create, but do not attach this VCPU */
538 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
539 void (*vcpu_free)(struct kvm_vcpu *vcpu);
540 int (*vcpu_reset)(struct kvm_vcpu *vcpu);
541
542 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
543 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
544 void (*vcpu_put)(struct kvm_vcpu *vcpu);
ea4a5ff8 545
355be0b9
JK
546 void (*set_guest_debug)(struct kvm_vcpu *vcpu,
547 struct kvm_guest_debug *dbg);
ea4a5ff8
ZX
548 int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
549 int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
550 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
551 void (*get_segment)(struct kvm_vcpu *vcpu,
552 struct kvm_segment *var, int seg);
2e4d2653 553 int (*get_cpl)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
554 void (*set_segment)(struct kvm_vcpu *vcpu,
555 struct kvm_segment *var, int seg);
556 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
e8467fda 557 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
aff48baa 558 void (*decache_cr3)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
559 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
560 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
561 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
562 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
563 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
89a27f4d
GN
564 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
565 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
566 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
567 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
020df079 568 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
5fdbf976 569 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
ea4a5ff8
ZX
570 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
571 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
6b52d186 572 void (*fpu_activate)(struct kvm_vcpu *vcpu);
02daab21 573 void (*fpu_deactivate)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
574
575 void (*tlb_flush)(struct kvm_vcpu *vcpu);
ea4a5ff8 576
851ba692
AK
577 void (*run)(struct kvm_vcpu *vcpu);
578 int (*handle_exit)(struct kvm_vcpu *vcpu);
ea4a5ff8 579 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
2809f5d2
GC
580 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
581 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
ea4a5ff8
ZX
582 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
583 unsigned char *hypercall_addr);
66fd3f7f 584 void (*set_irq)(struct kvm_vcpu *vcpu);
95ba8273 585 void (*set_nmi)(struct kvm_vcpu *vcpu);
298101da 586 void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
587 bool has_error_code, u32 error_code,
588 bool reinject);
b463a6f7 589 void (*cancel_injection)(struct kvm_vcpu *vcpu);
78646121 590 int (*interrupt_allowed)(struct kvm_vcpu *vcpu);
95ba8273 591 int (*nmi_allowed)(struct kvm_vcpu *vcpu);
3cfc3092
JK
592 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
593 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
95ba8273
GN
594 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
595 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
596 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
ea4a5ff8 597 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
67253af5 598 int (*get_tdp_level)(void);
4b12f0de 599 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
17cc3935 600 int (*get_lpage_level)(void);
4e47c7a6 601 bool (*rdtscp_supported)(void);
e48672fa 602 void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment);
344f414f 603
1c97f0a0
JR
604 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
605
d4330ef2
JR
606 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry);
607
f5f48ee1
SY
608 bool (*has_wbinvd_exit)(void);
609
4051b188 610 void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz);
99e3e30a
ZA
611 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
612
857e4099
JR
613 u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc);
614
586f9607 615 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2);
8a76d7f2
JR
616
617 int (*check_intercept)(struct kvm_vcpu *vcpu,
618 struct x86_instruction_info *info,
619 enum x86_intercept_stage stage);
620
229456fc 621 const struct trace_print_flags *exit_reasons_str;
ea4a5ff8
ZX
622};
623
af585b92 624struct kvm_arch_async_pf {
7c90705b 625 u32 token;
af585b92 626 gfn_t gfn;
fb67e14f 627 unsigned long cr3;
c4806acd 628 bool direct_map;
af585b92
GN
629};
630
97896d04
ZX
631extern struct kvm_x86_ops *kvm_x86_ops;
632
54f1585a
ZX
633int kvm_mmu_module_init(void);
634void kvm_mmu_module_exit(void);
635
636void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
637int kvm_mmu_create(struct kvm_vcpu *vcpu);
638int kvm_mmu_setup(struct kvm_vcpu *vcpu);
639void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte);
7b52345e 640void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 641 u64 dirty_mask, u64 nx_mask, u64 x_mask);
54f1585a
ZX
642
643int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
644void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
645void kvm_mmu_zap_all(struct kvm *kvm);
3ad82a7e 646unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
54f1585a
ZX
647void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
648
ff03a073 649int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
cc4b6871 650
3200f405 651int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 652 const void *val, int bytes);
2f333bcb
MT
653int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
654 gpa_t addr, unsigned long *ret);
4b12f0de 655u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
2f333bcb
MT
656
657extern bool tdp_enabled;
9f811285 658
92a1f12d
JR
659/* control of guest tsc rate supported? */
660extern bool kvm_has_tsc_control;
661/* minimum supported tsc_khz for guests */
662extern u32 kvm_min_guest_tsc_khz;
663/* maximum supported tsc_khz for guests */
664extern u32 kvm_max_guest_tsc_khz;
665
54f1585a
ZX
666enum emulation_result {
667 EMULATE_DONE, /* no further processing */
668 EMULATE_DO_MMIO, /* kvm_run filled with mmio request */
669 EMULATE_FAIL, /* can't emulate this instruction */
670};
671
571008da
SY
672#define EMULTYPE_NO_DECODE (1 << 0)
673#define EMULTYPE_TRAP_UD (1 << 1)
ba8afb6b 674#define EMULTYPE_SKIP (1 << 2)
dc25e89e
AP
675int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
676 int emulation_type, void *insn, int insn_len);
51d8b661
AP
677
678static inline int emulate_instruction(struct kvm_vcpu *vcpu,
679 int emulation_type)
680{
dc25e89e 681 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
51d8b661
AP
682}
683
f2b4b7dd 684void kvm_enable_efer_bits(u64);
54f1585a
ZX
685int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data);
686int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
687
688struct x86_emulate_ctxt;
689
cf8f70bf 690int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port);
54f1585a
ZX
691void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
692int kvm_emulate_halt(struct kvm_vcpu *vcpu);
f5f48ee1 693int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
54f1585a 694
3e6e0aab 695void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
c697518a 696int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
3e6e0aab 697
e269fb21
JK
698int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
699 bool has_error_code, u32 error_code);
37817f29 700
49a9b07e 701int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
2390218b 702int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
a83b29c6 703int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
eea1cff9 704int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
020df079
GN
705int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
706int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
2d3ad1f4
AK
707unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
708void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
54f1585a 709void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
2acf923e 710int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
54f1585a
ZX
711
712int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
713int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
714
91586a3b
JK
715unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
716void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
717
298101da
AK
718void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
719void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
ce7ddec4
JR
720void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
721void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
6389ee94 722void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
ec92fe44
JR
723int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
724 gfn_t gfn, void *data, int offset, int len,
725 u32 access);
6389ee94 726void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
0a79b009 727bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
298101da 728
4925663a 729int kvm_pic_set_irq(void *opaque, int irq, int level);
3de42dc0 730
3419ffc8
SY
731void kvm_inject_nmi(struct kvm_vcpu *vcpu);
732
10ab25cd 733int fx_init(struct kvm_vcpu *vcpu);
54f1585a 734
d835dfec 735void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
54f1585a 736void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT
737 const u8 *new, int bytes,
738 bool guest_initiated);
54f1585a
ZX
739int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
740void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
741int kvm_mmu_load(struct kvm_vcpu *vcpu);
742void kvm_mmu_unload(struct kvm_vcpu *vcpu);
0ba73cda 743void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
ab9ae313
AK
744gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
745 struct x86_exception *exception);
746gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
747 struct x86_exception *exception);
748gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
749 struct x86_exception *exception);
750gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
751 struct x86_exception *exception);
54f1585a
ZX
752
753int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
754
dc25e89e
AP
755int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
756 void *insn, int insn_len);
a7052897 757void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
34c16eec 758
18552672 759void kvm_enable_tdp(void);
5f4cb662 760void kvm_disable_tdp(void);
18552672 761
de7d789a 762int complete_pio(struct kvm_vcpu *vcpu);
f850e2e6 763bool kvm_check_iopl(struct kvm_vcpu *vcpu);
ec6d273d
ZX
764
765static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
766{
767 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
768
769 return (struct kvm_mmu_page *)page_private(page);
770}
771
d6e88aec 772static inline u16 kvm_read_ldt(void)
ec6d273d
ZX
773{
774 u16 ldt;
775 asm("sldt %0" : "=g"(ldt));
776 return ldt;
777}
778
d6e88aec 779static inline void kvm_load_ldt(u16 sel)
ec6d273d
ZX
780{
781 asm("lldt %0" : : "rm"(sel));
782}
ec6d273d 783
ec6d273d
ZX
784#ifdef CONFIG_X86_64
785static inline unsigned long read_msr(unsigned long msr)
786{
787 u64 value;
788
789 rdmsrl(msr, value);
790 return value;
791}
792#endif
793
ec6d273d
ZX
794static inline u32 get_rdx_init_val(void)
795{
796 return 0x600; /* P6 family */
797}
798
c1a5d4f9
AK
799static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
800{
801 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
802}
803
ec6d273d
ZX
804#define TSS_IOPB_BASE_OFFSET 0x66
805#define TSS_BASE_SIZE 0x68
806#define TSS_IOPB_SIZE (65536 / 8)
807#define TSS_REDIRECTION_SIZE (256 / 8)
7d76b4d3
JP
808#define RMODE_TSS_SIZE \
809 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
53e0aa7b 810
37817f29
IE
811enum {
812 TASK_SWITCH_CALL = 0,
813 TASK_SWITCH_IRET = 1,
814 TASK_SWITCH_JMP = 2,
815 TASK_SWITCH_GATE = 3,
816};
817
1371d904 818#define HF_GIF_MASK (1 << 0)
3d6368ef
AG
819#define HF_HIF_MASK (1 << 1)
820#define HF_VINTR_MASK (1 << 2)
95ba8273 821#define HF_NMI_MASK (1 << 3)
44c11430 822#define HF_IRET_MASK (1 << 4)
ec9e60b2 823#define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
1371d904 824
4ecac3fd
AK
825/*
826 * Hardware virtualization extension instructions may fault if a
827 * reboot turns off virtualization while processes are running.
828 * Trap the fault and ignore the instruction if that happens.
829 */
b7c4145b
AK
830asmlinkage void kvm_spurious_fault(void);
831extern bool kvm_rebooting;
4ecac3fd 832
5e520e62 833#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \
4ecac3fd 834 "666: " insn "\n\t" \
b7c4145b 835 "668: \n\t" \
18b13e54 836 ".pushsection .fixup, \"ax\" \n" \
4ecac3fd 837 "667: \n\t" \
5e520e62 838 cleanup_insn "\n\t" \
b7c4145b
AK
839 "cmpb $0, kvm_rebooting \n\t" \
840 "jne 668b \n\t" \
8ceed347 841 __ASM_SIZE(push) " $666b \n\t" \
b7c4145b 842 "call kvm_spurious_fault \n\t" \
4ecac3fd
AK
843 ".popsection \n\t" \
844 ".pushsection __ex_table, \"a\" \n\t" \
8ceed347 845 _ASM_PTR " 666b, 667b \n\t" \
4ecac3fd
AK
846 ".popsection"
847
5e520e62
AK
848#define __kvm_handle_fault_on_reboot(insn) \
849 ____kvm_handle_fault_on_reboot(insn, "")
850
e930bffe
AA
851#define KVM_ARCH_WANT_MMU_NOTIFIER
852int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
853int kvm_age_hva(struct kvm *kvm, unsigned long hva);
8ee53820 854int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
3da0dd43 855void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
82725b20 856int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
a1b37100
GN
857int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
858int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
0b71785d 859int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
e930bffe 860
18863bdd 861void kvm_define_shared_msr(unsigned index, u32 msr);
d5696725 862void kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
18863bdd 863
f92653ee
JK
864bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
865
af585b92
GN
866void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
867 struct kvm_async_pf *work);
868void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
869 struct kvm_async_pf *work);
56028d08
GN
870void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
871 struct kvm_async_pf *work);
7c90705b 872bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu);
af585b92
GN
873extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
874
db8fcefa
AP
875void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
876
1965aae3 877#endif /* _ASM_X86_KVM_HOST_H */