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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
87276880 | 27 | #include <linux/irqbypass.h> |
5c919412 | 28 | #include <linux/hyperv.h> |
34c16eec | 29 | |
50d0a0f9 | 30 | #include <asm/pvclock-abi.h> |
e01a1b57 | 31 | #include <asm/desc.h> |
0bed3b56 | 32 | #include <asm/mtrr.h> |
9962d032 | 33 | #include <asm/msr-index.h> |
3ee89722 | 34 | #include <asm/asm.h> |
e01a1b57 | 35 | |
cbf64358 | 36 | #define KVM_MAX_VCPUS 255 |
a59cb29e | 37 | #define KVM_SOFT_MAX_VCPUS 160 |
1d4e7e3c | 38 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
39 | /* memory slots that are not exposed to userspace */ |
40 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 41 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 42 | |
69a9f69b | 43 | #define KVM_PIO_PAGE_OFFSET 1 |
542472b5 | 44 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
920552b2 | 45 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
69a9f69b | 46 | |
8175e5b7 AG |
47 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
48 | ||
cfec82cb JR |
49 | #define CR0_RESERVED_BITS \ |
50 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
51 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
52 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
53 | ||
346874c9 | 54 | #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL |
cfaa790a | 55 | #define CR3_PCID_INVD BIT_64(63) |
cfec82cb JR |
56 | #define CR4_RESERVED_BITS \ |
57 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
58 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 59 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 60 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
56d6efc2 | 61 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP)) |
cfec82cb JR |
62 | |
63 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
64 | ||
65 | ||
cd6e8f87 | 66 | |
cd6e8f87 | 67 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
68 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
69 | ||
cd6e8f87 ZX |
70 | #define UNMAPPED_GVA (~(gpa_t)0) |
71 | ||
ec04b260 | 72 | /* KVM Hugepage definitions for x86 */ |
04326caa | 73 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
74 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
75 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
76 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
77 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
78 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 79 | |
6d9d41e5 CD |
80 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
81 | { | |
82 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
83 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
84 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
85 | } | |
86 | ||
d657a98e ZX |
87 | #define KVM_PERMILLE_MMU_PAGES 20 |
88 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
89 | #define KVM_MMU_HASH_SHIFT 10 |
90 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
91 | #define KVM_MIN_FREE_MMU_PAGES 5 |
92 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 93 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 94 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 95 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 96 | |
af585b92 GN |
97 | #define ASYNC_PF_PER_VCPU 64 |
98 | ||
5fdbf976 | 99 | enum kvm_reg { |
2b3ccfa0 ZX |
100 | VCPU_REGS_RAX = 0, |
101 | VCPU_REGS_RCX = 1, | |
102 | VCPU_REGS_RDX = 2, | |
103 | VCPU_REGS_RBX = 3, | |
104 | VCPU_REGS_RSP = 4, | |
105 | VCPU_REGS_RBP = 5, | |
106 | VCPU_REGS_RSI = 6, | |
107 | VCPU_REGS_RDI = 7, | |
108 | #ifdef CONFIG_X86_64 | |
109 | VCPU_REGS_R8 = 8, | |
110 | VCPU_REGS_R9 = 9, | |
111 | VCPU_REGS_R10 = 10, | |
112 | VCPU_REGS_R11 = 11, | |
113 | VCPU_REGS_R12 = 12, | |
114 | VCPU_REGS_R13 = 13, | |
115 | VCPU_REGS_R14 = 14, | |
116 | VCPU_REGS_R15 = 15, | |
117 | #endif | |
5fdbf976 | 118 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
119 | NR_VCPU_REGS |
120 | }; | |
121 | ||
6de4f3ad AK |
122 | enum kvm_reg_ex { |
123 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 124 | VCPU_EXREG_CR3, |
6de12732 | 125 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 126 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
127 | }; |
128 | ||
2b3ccfa0 | 129 | enum { |
81609e3e | 130 | VCPU_SREG_ES, |
2b3ccfa0 | 131 | VCPU_SREG_CS, |
81609e3e | 132 | VCPU_SREG_SS, |
2b3ccfa0 | 133 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
134 | VCPU_SREG_FS, |
135 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
136 | VCPU_SREG_TR, |
137 | VCPU_SREG_LDTR, | |
138 | }; | |
139 | ||
56e82318 | 140 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 141 | |
d657a98e ZX |
142 | #define KVM_NR_MEM_OBJS 40 |
143 | ||
42dbaa5a JK |
144 | #define KVM_NR_DB_REGS 4 |
145 | ||
146 | #define DR6_BD (1 << 13) | |
147 | #define DR6_BS (1 << 14) | |
6f43ed01 NA |
148 | #define DR6_RTM (1 << 16) |
149 | #define DR6_FIXED_1 0xfffe0ff0 | |
150 | #define DR6_INIT 0xffff0ff0 | |
151 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
152 | |
153 | #define DR7_BP_EN_MASK 0x000000ff | |
154 | #define DR7_GE (1 << 9) | |
155 | #define DR7_GD (1 << 13) | |
156 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 157 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 158 | |
c205fb7d NA |
159 | #define PFERR_PRESENT_BIT 0 |
160 | #define PFERR_WRITE_BIT 1 | |
161 | #define PFERR_USER_BIT 2 | |
162 | #define PFERR_RSVD_BIT 3 | |
163 | #define PFERR_FETCH_BIT 4 | |
164 | ||
165 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
166 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
167 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
168 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
169 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
170 | ||
41383771 GN |
171 | /* apic attention bits */ |
172 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
173 | /* |
174 | * The following bit is set with PV-EOI, unset on EOI. | |
175 | * We detect PV-EOI changes by guest by comparing | |
176 | * this bit with PV-EOI in guest memory. | |
177 | * See the implementation in apic_update_pv_eoi. | |
178 | */ | |
179 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 180 | |
d84f1e07 FW |
181 | struct kvm_kernel_irq_routing_entry; |
182 | ||
d657a98e ZX |
183 | /* |
184 | * We don't want allocation failures within the mmu code, so we preallocate | |
185 | * enough memory for a single page fault in a cache. | |
186 | */ | |
187 | struct kvm_mmu_memory_cache { | |
188 | int nobjs; | |
189 | void *objects[KVM_NR_MEM_OBJS]; | |
190 | }; | |
191 | ||
d657a98e ZX |
192 | union kvm_mmu_page_role { |
193 | unsigned word; | |
194 | struct { | |
7d76b4d3 | 195 | unsigned level:4; |
5b7e0102 | 196 | unsigned cr4_pae:1; |
7d76b4d3 | 197 | unsigned quadrant:2; |
f6e2c02b | 198 | unsigned direct:1; |
7d76b4d3 | 199 | unsigned access:3; |
2e53d63a | 200 | unsigned invalid:1; |
9645bb56 | 201 | unsigned nxe:1; |
3dbe1415 | 202 | unsigned cr0_wp:1; |
411c588d | 203 | unsigned smep_andnot_wp:1; |
0be0226f | 204 | unsigned smap_andnot_wp:1; |
699023e2 PB |
205 | unsigned :8; |
206 | ||
207 | /* | |
208 | * This is left at the top of the word so that | |
209 | * kvm_memslots_for_spte_role can extract it with a | |
210 | * simple shift. While there is room, give it a whole | |
211 | * byte so it is also faster to load it from memory. | |
212 | */ | |
213 | unsigned smm:8; | |
d657a98e ZX |
214 | }; |
215 | }; | |
216 | ||
018aabb5 TY |
217 | struct kvm_rmap_head { |
218 | unsigned long val; | |
219 | }; | |
220 | ||
d657a98e ZX |
221 | struct kvm_mmu_page { |
222 | struct list_head link; | |
223 | struct hlist_node hash_link; | |
224 | ||
225 | /* | |
226 | * The following two entries are used to key the shadow page in the | |
227 | * hash table. | |
228 | */ | |
229 | gfn_t gfn; | |
230 | union kvm_mmu_page_role role; | |
231 | ||
232 | u64 *spt; | |
233 | /* hold the gfn of each spte inside spt */ | |
234 | gfn_t *gfns; | |
4731d4c7 | 235 | bool unsync; |
0571d366 | 236 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 237 | unsigned int unsync_children; |
018aabb5 | 238 | struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ |
f6f8adee XG |
239 | |
240 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 241 | unsigned long mmu_valid_gen; |
f6f8adee | 242 | |
0074ff63 | 243 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
244 | |
245 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
246 | /* |
247 | * Used out of the mmu-lock to avoid reading spte values while an | |
248 | * update is in progress; see the comments in __get_spte_lockless(). | |
249 | */ | |
c2a2ac2b XG |
250 | int clear_spte_count; |
251 | #endif | |
252 | ||
0cbf8e43 | 253 | /* Number of writes since the last time traversal visited this page. */ |
a30f47cb | 254 | int write_flooding_count; |
d657a98e ZX |
255 | }; |
256 | ||
1c08364c AK |
257 | struct kvm_pio_request { |
258 | unsigned long count; | |
1c08364c AK |
259 | int in; |
260 | int port; | |
261 | int size; | |
1c08364c AK |
262 | }; |
263 | ||
a0a64f50 XG |
264 | struct rsvd_bits_validate { |
265 | u64 rsvd_bits_mask[2][4]; | |
266 | u64 bad_mt_xwr; | |
267 | }; | |
268 | ||
d657a98e ZX |
269 | /* |
270 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
271 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
272 | * mode. | |
273 | */ | |
274 | struct kvm_mmu { | |
f43addd4 | 275 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 276 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 277 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
278 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
279 | bool prefault); | |
6389ee94 AK |
280 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
281 | struct x86_exception *fault); | |
1871c602 | 282 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 283 | struct x86_exception *exception); |
54987b7a PB |
284 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
285 | struct x86_exception *exception); | |
e8bc217a | 286 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 287 | struct kvm_mmu_page *sp); |
a7052897 | 288 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 289 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 290 | u64 *spte, const void *pte); |
d657a98e ZX |
291 | hpa_t root_hpa; |
292 | int root_level; | |
293 | int shadow_root_level; | |
a770f6f2 | 294 | union kvm_mmu_page_role base_role; |
c5a78f2b | 295 | bool direct_map; |
d657a98e | 296 | |
97d64b78 AK |
297 | /* |
298 | * Bitmap; bit set = permission fault | |
299 | * Byte index: page fault error code [4:1] | |
300 | * Bit index: pte permissions in ACC_* format | |
301 | */ | |
302 | u8 permissions[16]; | |
303 | ||
d657a98e | 304 | u64 *pae_root; |
81407ca5 | 305 | u64 *lm_root; |
c258b62b XG |
306 | |
307 | /* | |
308 | * check zero bits on shadow page table entries, these | |
309 | * bits include not only hardware reserved bits but also | |
310 | * the bits spte never used. | |
311 | */ | |
312 | struct rsvd_bits_validate shadow_zero_check; | |
313 | ||
a0a64f50 | 314 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 315 | |
6fd01b71 AK |
316 | /* |
317 | * Bitmap: bit set = last pte in walk | |
318 | * index[0:1]: level (zero-based) | |
319 | * index[2]: pte.ps | |
320 | */ | |
321 | u8 last_pte_bitmap; | |
322 | ||
2d48a985 JR |
323 | bool nx; |
324 | ||
ff03a073 | 325 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
326 | }; |
327 | ||
f5132b01 GN |
328 | enum pmc_type { |
329 | KVM_PMC_GP = 0, | |
330 | KVM_PMC_FIXED, | |
331 | }; | |
332 | ||
333 | struct kvm_pmc { | |
334 | enum pmc_type type; | |
335 | u8 idx; | |
336 | u64 counter; | |
337 | u64 eventsel; | |
338 | struct perf_event *perf_event; | |
339 | struct kvm_vcpu *vcpu; | |
340 | }; | |
341 | ||
342 | struct kvm_pmu { | |
343 | unsigned nr_arch_gp_counters; | |
344 | unsigned nr_arch_fixed_counters; | |
345 | unsigned available_event_types; | |
346 | u64 fixed_ctr_ctrl; | |
347 | u64 global_ctrl; | |
348 | u64 global_status; | |
349 | u64 global_ovf_ctrl; | |
350 | u64 counter_bitmask[2]; | |
351 | u64 global_ctrl_mask; | |
103af0a9 | 352 | u64 reserved_bits; |
f5132b01 | 353 | u8 version; |
15c7ad51 RR |
354 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
355 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
356 | struct irq_work irq_work; |
357 | u64 reprogram_pmi; | |
358 | }; | |
359 | ||
25462f7f WH |
360 | struct kvm_pmu_ops; |
361 | ||
360b948d PB |
362 | enum { |
363 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 364 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 365 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
366 | }; |
367 | ||
86fd5270 XG |
368 | struct kvm_mtrr_range { |
369 | u64 base; | |
370 | u64 mask; | |
19efffa2 | 371 | struct list_head node; |
86fd5270 XG |
372 | }; |
373 | ||
70109e7d | 374 | struct kvm_mtrr { |
86fd5270 | 375 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 376 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 377 | u64 deftype; |
19efffa2 XG |
378 | |
379 | struct list_head head; | |
70109e7d XG |
380 | }; |
381 | ||
1f4b34f8 AS |
382 | /* Hyper-V SynIC timer */ |
383 | struct kvm_vcpu_hv_stimer { | |
384 | struct hrtimer timer; | |
385 | int index; | |
386 | u64 config; | |
387 | u64 count; | |
388 | u64 exp_time; | |
389 | struct hv_message msg; | |
390 | bool msg_pending; | |
391 | }; | |
392 | ||
5c919412 AS |
393 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
394 | struct kvm_vcpu_hv_synic { | |
395 | u64 version; | |
396 | u64 control; | |
397 | u64 msg_page; | |
398 | u64 evt_page; | |
399 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
400 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
401 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
402 | DECLARE_BITMAP(vec_bitmap, 256); | |
403 | bool active; | |
404 | }; | |
405 | ||
e83d5887 AS |
406 | /* Hyper-V per vcpu emulation context */ |
407 | struct kvm_vcpu_hv { | |
408 | u64 hv_vapic; | |
9eec50b8 | 409 | s64 runtime_offset; |
5c919412 | 410 | struct kvm_vcpu_hv_synic synic; |
db397571 | 411 | struct kvm_hyperv_exit exit; |
1f4b34f8 AS |
412 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; |
413 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
e83d5887 AS |
414 | }; |
415 | ||
ad312c7c | 416 | struct kvm_vcpu_arch { |
5fdbf976 MT |
417 | /* |
418 | * rip and regs accesses must go through | |
419 | * kvm_{register,rip}_{read,write} functions. | |
420 | */ | |
421 | unsigned long regs[NR_VCPU_REGS]; | |
422 | u32 regs_avail; | |
423 | u32 regs_dirty; | |
34c16eec ZX |
424 | |
425 | unsigned long cr0; | |
e8467fda | 426 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
427 | unsigned long cr2; |
428 | unsigned long cr3; | |
429 | unsigned long cr4; | |
fc78f519 | 430 | unsigned long cr4_guest_owned_bits; |
34c16eec | 431 | unsigned long cr8; |
1371d904 | 432 | u32 hflags; |
f6801dff | 433 | u64 efer; |
34c16eec ZX |
434 | u64 apic_base; |
435 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 436 | bool apicv_active; |
6308630b | 437 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 438 | unsigned long apic_attention; |
e1035715 | 439 | int32_t apic_arb_prio; |
34c16eec | 440 | int mp_state; |
34c16eec | 441 | u64 ia32_misc_enable_msr; |
64d60670 | 442 | u64 smbase; |
b209749f | 443 | bool tpr_access_reporting; |
20300099 | 444 | u64 ia32_xss; |
34c16eec | 445 | |
14dfe855 JR |
446 | /* |
447 | * Paging state of the vcpu | |
448 | * | |
449 | * If the vcpu runs in guest mode with two level paging this still saves | |
450 | * the paging mode of the l1 guest. This context is always used to | |
451 | * handle faults. | |
452 | */ | |
34c16eec | 453 | struct kvm_mmu mmu; |
8df25a32 | 454 | |
6539e738 JR |
455 | /* |
456 | * Paging state of an L2 guest (used for nested npt) | |
457 | * | |
458 | * This context will save all necessary information to walk page tables | |
459 | * of the an L2 guest. This context is only initialized for page table | |
460 | * walking and not for faulting since we never handle l2 page faults on | |
461 | * the host. | |
462 | */ | |
463 | struct kvm_mmu nested_mmu; | |
464 | ||
14dfe855 JR |
465 | /* |
466 | * Pointer to the mmu context currently used for | |
467 | * gva_to_gpa translations. | |
468 | */ | |
469 | struct kvm_mmu *walk_mmu; | |
470 | ||
53c07b18 | 471 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
472 | struct kvm_mmu_memory_cache mmu_page_cache; |
473 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
474 | ||
98918833 | 475 | struct fpu guest_fpu; |
c447e76b | 476 | bool eager_fpu; |
2acf923e | 477 | u64 xcr0; |
d7876f1b | 478 | u64 guest_supported_xcr0; |
4344ee98 | 479 | u32 guest_xstate_size; |
34c16eec | 480 | |
34c16eec ZX |
481 | struct kvm_pio_request pio; |
482 | void *pio_data; | |
483 | ||
66fd3f7f GN |
484 | u8 event_exit_inst_len; |
485 | ||
298101da AK |
486 | struct kvm_queued_exception { |
487 | bool pending; | |
488 | bool has_error_code; | |
ce7ddec4 | 489 | bool reinject; |
298101da AK |
490 | u8 nr; |
491 | u32 error_code; | |
492 | } exception; | |
493 | ||
937a7eae AK |
494 | struct kvm_queued_interrupt { |
495 | bool pending; | |
66fd3f7f | 496 | bool soft; |
937a7eae AK |
497 | u8 nr; |
498 | } interrupt; | |
499 | ||
34c16eec ZX |
500 | int halt_request; /* real mode on Intel only */ |
501 | ||
502 | int cpuid_nent; | |
07716717 | 503 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
504 | |
505 | int maxphyaddr; | |
506 | ||
34c16eec ZX |
507 | /* emulate context */ |
508 | ||
509 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
510 | bool emulate_regs_need_sync_to_vcpu; |
511 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 512 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
513 | |
514 | gpa_t time; | |
50d0a0f9 | 515 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 516 | unsigned int hw_tsc_khz; |
0b79459b AH |
517 | struct gfn_to_hva_cache pv_time; |
518 | bool pv_time_enabled; | |
51d59c6b MT |
519 | /* set guest stopped flag in pvclock flags field */ |
520 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
521 | |
522 | struct { | |
523 | u64 msr_val; | |
524 | u64 last_steal; | |
525 | u64 accum_steal; | |
526 | struct gfn_to_hva_cache stime; | |
527 | struct kvm_steal_time steal; | |
528 | } st; | |
529 | ||
1d5f066e | 530 | u64 last_guest_tsc; |
6f526ec5 | 531 | u64 last_host_tsc; |
0dd6a6ed | 532 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
533 | u64 this_tsc_nsec; |
534 | u64 this_tsc_write; | |
0d3da0d2 | 535 | u64 this_tsc_generation; |
c285545f | 536 | bool tsc_catchup; |
cc578287 ZA |
537 | bool tsc_always_catchup; |
538 | s8 virtual_tsc_shift; | |
539 | u32 virtual_tsc_mult; | |
540 | u32 virtual_tsc_khz; | |
ba904635 | 541 | s64 ia32_tsc_adjust_msr; |
ad721883 | 542 | u64 tsc_scaling_ratio; |
3419ffc8 | 543 | |
7460fb4a AK |
544 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
545 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
546 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 547 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 548 | |
70109e7d | 549 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 550 | u64 pat; |
42dbaa5a | 551 | |
360b948d | 552 | unsigned switch_db_regs; |
42dbaa5a JK |
553 | unsigned long db[KVM_NR_DB_REGS]; |
554 | unsigned long dr6; | |
555 | unsigned long dr7; | |
556 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 557 | unsigned long guest_debug_dr7; |
890ca9ae HY |
558 | |
559 | u64 mcg_cap; | |
560 | u64 mcg_status; | |
561 | u64 mcg_ctl; | |
562 | u64 *mce_banks; | |
94fe45da | 563 | |
bebb106a XG |
564 | /* Cache MMIO info */ |
565 | u64 mmio_gva; | |
566 | unsigned access; | |
567 | gfn_t mmio_gfn; | |
56f17dd3 | 568 | u64 mmio_gen; |
bebb106a | 569 | |
f5132b01 GN |
570 | struct kvm_pmu pmu; |
571 | ||
94fe45da | 572 | /* used for guest single stepping over the given code position */ |
94fe45da | 573 | unsigned long singlestep_rip; |
f92653ee | 574 | |
e83d5887 | 575 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
576 | |
577 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 578 | |
1cb3f3ae XG |
579 | unsigned long last_retry_eip; |
580 | unsigned long last_retry_addr; | |
581 | ||
af585b92 GN |
582 | struct { |
583 | bool halted; | |
584 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
585 | struct gfn_to_hva_cache data; |
586 | u64 msr_val; | |
7c90705b | 587 | u32 id; |
6adba527 | 588 | bool send_user_only; |
af585b92 | 589 | } apf; |
2b036c6b BO |
590 | |
591 | /* OSVW MSRs (AMD only) */ | |
592 | struct { | |
593 | u64 length; | |
594 | u64 status; | |
595 | } osvw; | |
ae7a2a3f MT |
596 | |
597 | struct { | |
598 | u64 msr_val; | |
599 | struct gfn_to_hva_cache data; | |
600 | } pv_eoi; | |
93c05d3e XG |
601 | |
602 | /* | |
603 | * Indicate whether the access faults on its page table in guest | |
604 | * which is set when fix page fault and used to detect unhandeable | |
605 | * instruction. | |
606 | */ | |
607 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
608 | |
609 | /* set at EPT violation at this point */ | |
610 | unsigned long exit_qualification; | |
6aef266c SV |
611 | |
612 | /* pv related host specific info */ | |
613 | struct { | |
614 | bool pv_unhalted; | |
615 | } pv; | |
7543a635 SR |
616 | |
617 | int pending_ioapic_eoi; | |
1c1a9ce9 | 618 | int pending_external_vector; |
34c16eec ZX |
619 | }; |
620 | ||
db3fe4eb | 621 | struct kvm_lpage_info { |
db3fe4eb TY |
622 | int write_count; |
623 | }; | |
624 | ||
625 | struct kvm_arch_memory_slot { | |
018aabb5 | 626 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
627 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
628 | }; | |
629 | ||
3548a259 RK |
630 | /* |
631 | * We use as the mode the number of bits allocated in the LDR for the | |
632 | * logical processor ID. It happens that these are all powers of two. | |
633 | * This makes it is very easy to detect cases where the APICs are | |
634 | * configured for multiple modes; in that case, we cannot use the map and | |
635 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
636 | */ | |
637 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
638 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
639 | #define KVM_APIC_MODE_X2APIC 16 | |
640 | ||
1e08ec4a GN |
641 | struct kvm_apic_map { |
642 | struct rcu_head rcu; | |
3548a259 | 643 | u8 mode; |
1e08ec4a GN |
644 | struct kvm_lapic *phys_map[256]; |
645 | /* first index is cluster id second is cpu id in a cluster */ | |
646 | struct kvm_lapic *logical_map[16][16]; | |
647 | }; | |
648 | ||
e83d5887 AS |
649 | /* Hyper-V emulation context */ |
650 | struct kvm_hv { | |
651 | u64 hv_guest_os_id; | |
652 | u64 hv_hypercall; | |
653 | u64 hv_tsc_page; | |
e7d9513b AS |
654 | |
655 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
656 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
657 | u64 hv_crash_ctl; | |
e83d5887 AS |
658 | }; |
659 | ||
fef9cce0 | 660 | struct kvm_arch { |
49d5ca26 | 661 | unsigned int n_used_mmu_pages; |
f05e70ac | 662 | unsigned int n_requested_mmu_pages; |
39de71ec | 663 | unsigned int n_max_mmu_pages; |
332b207d | 664 | unsigned int indirect_shadow_pages; |
5304b8d3 | 665 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
666 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
667 | /* | |
668 | * Hash table of struct kvm_mmu_page. | |
669 | */ | |
670 | struct list_head active_mmu_pages; | |
365c8868 XG |
671 | struct list_head zapped_obsolete_pages; |
672 | ||
4d5c5d0f | 673 | struct list_head assigned_dev_head; |
19de40a8 | 674 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 675 | bool iommu_noncoherent; |
e0f0bbc5 AW |
676 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
677 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
678 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
679 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
680 | struct kvm_pic *vpic; |
681 | struct kvm_ioapic *vioapic; | |
7837699f | 682 | struct kvm_pit *vpit; |
42720138 | 683 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
684 | struct mutex apic_map_lock; |
685 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 686 | |
bfc6d222 | 687 | unsigned int tss_addr; |
c24ae0dc | 688 | bool apic_access_page_done; |
18068523 GOC |
689 | |
690 | gpa_t wall_clock; | |
b7ebfb05 | 691 | |
b7ebfb05 | 692 | bool ept_identity_pagetable_done; |
b927a3ce | 693 | gpa_t ept_identity_map_addr; |
5550af4d SY |
694 | |
695 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 696 | s64 kvmclock_offset; |
038f8c11 | 697 | raw_spinlock_t tsc_write_lock; |
f38e098f | 698 | u64 last_tsc_nsec; |
f38e098f | 699 | u64 last_tsc_write; |
5d3cb0f6 | 700 | u32 last_tsc_khz; |
e26101b1 ZA |
701 | u64 cur_tsc_nsec; |
702 | u64 cur_tsc_write; | |
703 | u64 cur_tsc_offset; | |
0d3da0d2 | 704 | u64 cur_tsc_generation; |
b48aa97e | 705 | int nr_vcpus_matched_tsc; |
ffde22ac | 706 | |
d828199e MT |
707 | spinlock_t pvclock_gtod_sync_lock; |
708 | bool use_master_clock; | |
709 | u64 master_kernel_ns; | |
710 | cycle_t master_cycle_now; | |
7e44e449 | 711 | struct delayed_work kvmclock_update_work; |
332967a3 | 712 | struct delayed_work kvmclock_sync_work; |
d828199e | 713 | |
ffde22ac | 714 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 715 | |
6ef768fa PB |
716 | /* reads protected by irq_srcu, writes by irq_lock */ |
717 | struct hlist_head mask_notifier_list; | |
718 | ||
e83d5887 | 719 | struct kvm_hv hyperv; |
b034cf01 XG |
720 | |
721 | #ifdef CONFIG_KVM_MMU_AUDIT | |
722 | int audit_point; | |
723 | #endif | |
54750f2c MT |
724 | |
725 | bool boot_vcpu_runs_old_kvmclock; | |
d71ba788 | 726 | u32 bsp_vcpu_id; |
90de4a18 NA |
727 | |
728 | u64 disabled_quirks; | |
49df6397 SR |
729 | |
730 | bool irqchip_split; | |
b053b2ae | 731 | u8 nr_reserved_ioapic_pins; |
d69fb81f ZX |
732 | }; |
733 | ||
0711456c ZX |
734 | struct kvm_vm_stat { |
735 | u32 mmu_shadow_zapped; | |
736 | u32 mmu_pte_write; | |
737 | u32 mmu_pte_updated; | |
738 | u32 mmu_pde_zapped; | |
739 | u32 mmu_flooded; | |
740 | u32 mmu_recycled; | |
dfc5aa00 | 741 | u32 mmu_cache_miss; |
4731d4c7 | 742 | u32 mmu_unsync; |
0711456c | 743 | u32 remote_tlb_flush; |
05da4558 | 744 | u32 lpages; |
0711456c ZX |
745 | }; |
746 | ||
77b4c255 ZX |
747 | struct kvm_vcpu_stat { |
748 | u32 pf_fixed; | |
749 | u32 pf_guest; | |
750 | u32 tlb_flush; | |
751 | u32 invlpg; | |
752 | ||
753 | u32 exits; | |
754 | u32 io_exits; | |
755 | u32 mmio_exits; | |
756 | u32 signal_exits; | |
757 | u32 irq_window_exits; | |
f08864b4 | 758 | u32 nmi_window_exits; |
77b4c255 | 759 | u32 halt_exits; |
f7819512 | 760 | u32 halt_successful_poll; |
62bea5bf | 761 | u32 halt_attempted_poll; |
77b4c255 ZX |
762 | u32 halt_wakeup; |
763 | u32 request_irq_exits; | |
764 | u32 irq_exits; | |
765 | u32 host_state_reload; | |
766 | u32 efer_reload; | |
767 | u32 fpu_reload; | |
768 | u32 insn_emulation; | |
769 | u32 insn_emulation_fail; | |
f11c3a8d | 770 | u32 hypercalls; |
fa89a817 | 771 | u32 irq_injections; |
c4abb7c9 | 772 | u32 nmi_injections; |
77b4c255 | 773 | }; |
ad312c7c | 774 | |
8a76d7f2 JR |
775 | struct x86_instruction_info; |
776 | ||
8fe8ab46 WA |
777 | struct msr_data { |
778 | bool host_initiated; | |
779 | u32 index; | |
780 | u64 data; | |
781 | }; | |
782 | ||
cb5281a5 PB |
783 | struct kvm_lapic_irq { |
784 | u32 vector; | |
b7cb2231 PB |
785 | u16 delivery_mode; |
786 | u16 dest_mode; | |
787 | bool level; | |
788 | u16 trig_mode; | |
cb5281a5 PB |
789 | u32 shorthand; |
790 | u32 dest_id; | |
93bbf0b8 | 791 | bool msi_redir_hint; |
cb5281a5 PB |
792 | }; |
793 | ||
ea4a5ff8 ZX |
794 | struct kvm_x86_ops { |
795 | int (*cpu_has_kvm_support)(void); /* __init */ | |
796 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
797 | int (*hardware_enable)(void); |
798 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
799 | void (*check_processor_compatibility)(void *rtn); |
800 | int (*hardware_setup)(void); /* __init */ | |
801 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 802 | bool (*cpu_has_accelerated_tpr)(void); |
6d396b55 | 803 | bool (*cpu_has_high_real_mode_segbase)(void); |
0e851880 | 804 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
805 | |
806 | /* Create, but do not attach this VCPU */ | |
807 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
808 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 809 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
810 | |
811 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
812 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
813 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 814 | |
a96036b8 | 815 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 816 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 817 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
818 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
819 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
820 | struct kvm_segment *var, int seg); | |
2e4d2653 | 821 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
822 | void (*set_segment)(struct kvm_vcpu *vcpu, |
823 | struct kvm_segment *var, int seg); | |
824 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 825 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 826 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
827 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
828 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
829 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 830 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 831 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
832 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
833 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
834 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
835 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
836 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
837 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 838 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 839 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 840 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
841 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
842 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
0fdd74f7 | 843 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 844 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
845 | |
846 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 847 | |
851ba692 AK |
848 | void (*run)(struct kvm_vcpu *vcpu); |
849 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 850 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 851 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 852 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
853 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
854 | unsigned char *hypercall_addr); | |
66fd3f7f | 855 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 856 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 857 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
858 | bool has_error_code, u32 error_code, |
859 | bool reinject); | |
b463a6f7 | 860 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 861 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 862 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
863 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
864 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
865 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
866 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 867 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
d62caabb AS |
868 | bool (*get_enable_apicv)(void); |
869 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); | |
c7c9c56c YZ |
870 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
871 | void (*hwapic_isr_update)(struct kvm *kvm, int isr); | |
6308630b | 872 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d14695f | 873 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
4256f43f | 874 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d YZ |
875 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
876 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 877 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 878 | int (*get_tdp_level)(void); |
4b12f0de | 879 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 880 | int (*get_lpage_level)(void); |
4e47c7a6 | 881 | bool (*rdtscp_supported)(void); |
ad756a16 | 882 | bool (*invpcid_supported)(void); |
58ea6767 | 883 | void (*adjust_tsc_offset_guest)(struct kvm_vcpu *vcpu, s64 adjustment); |
344f414f | 884 | |
1c97f0a0 JR |
885 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
886 | ||
d4330ef2 JR |
887 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
888 | ||
f5f48ee1 SY |
889 | bool (*has_wbinvd_exit)(void); |
890 | ||
ba904635 | 891 | u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
892 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
893 | ||
886b470c | 894 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc); |
857e4099 | 895 | |
586f9607 | 896 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
897 | |
898 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
899 | struct x86_instruction_info *info, | |
900 | enum x86_intercept_stage stage); | |
a547c6db | 901 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 902 | bool (*mpx_supported)(void); |
55412b2e | 903 | bool (*xsaves_supported)(void); |
b6b8a145 JK |
904 | |
905 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ae97a3b8 RK |
906 | |
907 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
908 | |
909 | /* | |
910 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
911 | * be valid if the specific arch has hardware-accelerated dirty logging | |
912 | * mechanism. Currently only for PML on VMX. | |
913 | * | |
914 | * - slot_enable_log_dirty: | |
915 | * called when enabling log dirty mode for the slot. | |
916 | * - slot_disable_log_dirty: | |
917 | * called when disabling log dirty mode for the slot. | |
918 | * also called when slot is created with log dirty disabled. | |
919 | * - flush_log_dirty: | |
920 | * called before reporting dirty_bitmap to userspace. | |
921 | * - enable_log_dirty_pt_masked: | |
922 | * called when reenabling log dirty for the GFNs in the mask after | |
923 | * corresponding bits are cleared in slot->dirty_bitmap. | |
924 | */ | |
925 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
926 | struct kvm_memory_slot *slot); | |
927 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
928 | struct kvm_memory_slot *slot); | |
929 | void (*flush_log_dirty)(struct kvm *kvm); | |
930 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
931 | struct kvm_memory_slot *slot, | |
932 | gfn_t offset, unsigned long mask); | |
25462f7f WH |
933 | /* pmu operations of sub-arch */ |
934 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 | 935 | |
bf9f6ac8 FW |
936 | /* |
937 | * Architecture specific hooks for vCPU blocking due to | |
938 | * HLT instruction. | |
939 | * Returns for .pre_block(): | |
940 | * - 0 means continue to block the vCPU. | |
941 | * - 1 means we cannot block the vCPU since some event | |
942 | * happens during this period, such as, 'ON' bit in | |
943 | * posted-interrupts descriptor is set. | |
944 | */ | |
945 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
946 | void (*post_block)(struct kvm_vcpu *vcpu); | |
efc64404 FW |
947 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
948 | uint32_t guest_irq, bool set); | |
ea4a5ff8 ZX |
949 | }; |
950 | ||
af585b92 | 951 | struct kvm_arch_async_pf { |
7c90705b | 952 | u32 token; |
af585b92 | 953 | gfn_t gfn; |
fb67e14f | 954 | unsigned long cr3; |
c4806acd | 955 | bool direct_map; |
af585b92 GN |
956 | }; |
957 | ||
97896d04 ZX |
958 | extern struct kvm_x86_ops *kvm_x86_ops; |
959 | ||
54f1585a ZX |
960 | int kvm_mmu_module_init(void); |
961 | void kvm_mmu_module_exit(void); | |
962 | ||
963 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
964 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 965 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
7b52345e | 966 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 967 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a | 968 | |
8a3c1a33 | 969 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
970 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
971 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 972 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 973 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
974 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
975 | struct kvm_memory_slot *memslot); | |
976 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
977 | struct kvm_memory_slot *memslot); | |
978 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
979 | struct kvm_memory_slot *memslot); | |
980 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
981 | struct kvm_memory_slot *slot, | |
982 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 983 | void kvm_mmu_zap_all(struct kvm *kvm); |
54bf36aa | 984 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); |
3ad82a7e | 985 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
986 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
987 | ||
ff03a073 | 988 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 989 | |
3200f405 | 990 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 991 | const void *val, int bytes); |
2f333bcb | 992 | |
6ef768fa PB |
993 | struct kvm_irq_mask_notifier { |
994 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
995 | int irq; | |
996 | struct hlist_node link; | |
997 | }; | |
998 | ||
999 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1000 | struct kvm_irq_mask_notifier *kimn); | |
1001 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1002 | struct kvm_irq_mask_notifier *kimn); | |
1003 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1004 | bool mask); | |
1005 | ||
2f333bcb | 1006 | extern bool tdp_enabled; |
9f811285 | 1007 | |
a3e06bbe LJ |
1008 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
1009 | ||
92a1f12d JR |
1010 | /* control of guest tsc rate supported? */ |
1011 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
1012 | /* maximum supported tsc_khz for guests */ |
1013 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
1014 | /* number of bits of the fractional part of the TSC scaling ratio */ |
1015 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1016 | /* maximum allowed value of TSC scaling ratio */ | |
1017 | extern u64 kvm_max_tsc_scaling_ratio; | |
92a1f12d | 1018 | |
54f1585a | 1019 | enum emulation_result { |
ac0a48c3 PB |
1020 | EMULATE_DONE, /* no further processing */ |
1021 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
1022 | EMULATE_FAIL, /* can't emulate this instruction */ |
1023 | }; | |
1024 | ||
571008da SY |
1025 | #define EMULTYPE_NO_DECODE (1 << 0) |
1026 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1027 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 1028 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 1029 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
1030 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
1031 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
1032 | |
1033 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
1034 | int emulation_type) | |
1035 | { | |
dc25e89e | 1036 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
1037 | } |
1038 | ||
f2b4b7dd | 1039 | void kvm_enable_efer_bits(u64); |
384bb783 | 1040 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 1041 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1042 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
1043 | |
1044 | struct x86_emulate_ctxt; | |
1045 | ||
cf8f70bf | 1046 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
1047 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
1048 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
5cb56059 | 1049 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1050 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1051 | |
3e6e0aab | 1052 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1053 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1054 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1055 | |
7f3d35fd KW |
1056 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1057 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1058 | |
49a9b07e | 1059 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1060 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1061 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1062 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1063 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1064 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1065 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1066 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1067 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1068 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1069 | |
609e36d3 | 1070 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1071 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1072 | |
91586a3b JK |
1073 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1074 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1075 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1076 | |
298101da AK |
1077 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1078 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1079 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1080 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1081 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1082 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1083 | gfn_t gfn, void *data, int offset, int len, | |
1084 | u32 access); | |
0a79b009 | 1085 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1086 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1087 | |
1a577b72 MT |
1088 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1089 | int irq_source_id, int level) | |
1090 | { | |
1091 | /* Logical OR for level trig interrupt */ | |
1092 | if (level) | |
1093 | __set_bit(irq_source_id, irq_state); | |
1094 | else | |
1095 | __clear_bit(irq_source_id, irq_state); | |
1096 | ||
1097 | return !!(*irq_state); | |
1098 | } | |
1099 | ||
1100 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1101 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1102 | |
3419ffc8 SY |
1103 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1104 | ||
54f1585a | 1105 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 1106 | const u8 *new, int bytes); |
1cb3f3ae | 1107 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1108 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1109 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1110 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1111 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1112 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
54987b7a PB |
1113 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1114 | struct x86_exception *exception); | |
ab9ae313 AK |
1115 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1116 | struct x86_exception *exception); | |
1117 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1118 | struct x86_exception *exception); | |
1119 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1120 | struct x86_exception *exception); | |
1121 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1122 | struct x86_exception *exception); | |
54f1585a | 1123 | |
d62caabb AS |
1124 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); |
1125 | ||
54f1585a ZX |
1126 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1127 | ||
dc25e89e AP |
1128 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
1129 | void *insn, int insn_len); | |
a7052897 | 1130 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 1131 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 1132 | |
18552672 | 1133 | void kvm_enable_tdp(void); |
5f4cb662 | 1134 | void kvm_disable_tdp(void); |
18552672 | 1135 | |
54987b7a PB |
1136 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1137 | struct x86_exception *exception) | |
e459e322 XG |
1138 | { |
1139 | return gpa; | |
1140 | } | |
1141 | ||
ec6d273d ZX |
1142 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1143 | { | |
1144 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1145 | ||
1146 | return (struct kvm_mmu_page *)page_private(page); | |
1147 | } | |
1148 | ||
d6e88aec | 1149 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1150 | { |
1151 | u16 ldt; | |
1152 | asm("sldt %0" : "=g"(ldt)); | |
1153 | return ldt; | |
1154 | } | |
1155 | ||
d6e88aec | 1156 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1157 | { |
1158 | asm("lldt %0" : : "rm"(sel)); | |
1159 | } | |
ec6d273d | 1160 | |
ec6d273d ZX |
1161 | #ifdef CONFIG_X86_64 |
1162 | static inline unsigned long read_msr(unsigned long msr) | |
1163 | { | |
1164 | u64 value; | |
1165 | ||
1166 | rdmsrl(msr, value); | |
1167 | return value; | |
1168 | } | |
1169 | #endif | |
1170 | ||
ec6d273d ZX |
1171 | static inline u32 get_rdx_init_val(void) |
1172 | { | |
1173 | return 0x600; /* P6 family */ | |
1174 | } | |
1175 | ||
c1a5d4f9 AK |
1176 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1177 | { | |
1178 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1179 | } | |
1180 | ||
854e8bb1 NA |
1181 | static inline u64 get_canonical(u64 la) |
1182 | { | |
1183 | return ((int64_t)la << 16) >> 16; | |
1184 | } | |
1185 | ||
1186 | static inline bool is_noncanonical_address(u64 la) | |
1187 | { | |
1188 | #ifdef CONFIG_X86_64 | |
1189 | return get_canonical(la) != la; | |
1190 | #else | |
1191 | return false; | |
1192 | #endif | |
1193 | } | |
1194 | ||
ec6d273d ZX |
1195 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1196 | #define TSS_BASE_SIZE 0x68 | |
1197 | #define TSS_IOPB_SIZE (65536 / 8) | |
1198 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1199 | #define RMODE_TSS_SIZE \ |
1200 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1201 | |
37817f29 IE |
1202 | enum { |
1203 | TASK_SWITCH_CALL = 0, | |
1204 | TASK_SWITCH_IRET = 1, | |
1205 | TASK_SWITCH_JMP = 2, | |
1206 | TASK_SWITCH_GATE = 3, | |
1207 | }; | |
1208 | ||
1371d904 | 1209 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1210 | #define HF_HIF_MASK (1 << 1) |
1211 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1212 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1213 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1214 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1215 | #define HF_SMM_MASK (1 << 6) |
1216 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1217 | |
699023e2 PB |
1218 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1219 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1220 | ||
1221 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1222 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1223 | |
4ecac3fd AK |
1224 | /* |
1225 | * Hardware virtualization extension instructions may fault if a | |
1226 | * reboot turns off virtualization while processes are running. | |
1227 | * Trap the fault and ignore the instruction if that happens. | |
1228 | */ | |
b7c4145b | 1229 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1230 | |
5e520e62 | 1231 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1232 | "666: " insn "\n\t" \ |
b7c4145b | 1233 | "668: \n\t" \ |
18b13e54 | 1234 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1235 | "667: \n\t" \ |
5e520e62 | 1236 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1237 | "cmpb $0, kvm_rebooting \n\t" \ |
1238 | "jne 668b \n\t" \ | |
8ceed347 | 1239 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1240 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1241 | ".popsection \n\t" \ |
3ee89722 | 1242 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1243 | |
5e520e62 AK |
1244 | #define __kvm_handle_fault_on_reboot(insn) \ |
1245 | ____kvm_handle_fault_on_reboot(insn, "") | |
1246 | ||
e930bffe AA |
1247 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1248 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1249 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1250 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1251 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1252 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1253 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1254 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1255 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1256 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1257 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1258 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
fe71557a TC |
1259 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
1260 | unsigned long address); | |
e930bffe | 1261 | |
18863bdd | 1262 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1263 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1264 | |
35181e86 | 1265 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1266 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1267 | |
82b32774 | 1268 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1269 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1270 | ||
af585b92 GN |
1271 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1272 | struct kvm_async_pf *work); | |
1273 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1274 | struct kvm_async_pf *work); | |
56028d08 GN |
1275 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1276 | struct kvm_async_pf *work); | |
7c90705b | 1277 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1278 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1279 | ||
db8fcefa AP |
1280 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
1281 | ||
f5132b01 GN |
1282 | int kvm_is_in_guest(void); |
1283 | ||
1d8007bd PB |
1284 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); |
1285 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
d71ba788 PB |
1286 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1287 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1288 | |
8feb4a04 FW |
1289 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1290 | struct kvm_vcpu **dest_vcpu); | |
1291 | ||
d84f1e07 FW |
1292 | void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e, |
1293 | struct kvm_lapic_irq *irq); | |
197a4f4b | 1294 | |
3217f7c2 CD |
1295 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {} |
1296 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {} | |
1297 | ||
1965aae3 | 1298 | #endif /* _ASM_X86_KVM_HOST_H */ |