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KVM: MMU: Make kvm_handle_hva() handle range of addresses
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a656c8ef 1/*
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2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This header defines architecture specific interfaces, x86 version
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See
7 * the COPYING file in the top-level directory.
8 *
9 */
10
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11#ifndef _ASM_X86_KVM_HOST_H
12#define _ASM_X86_KVM_HOST_H
043405e1 13
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14#include <linux/types.h>
15#include <linux/mm.h>
e930bffe 16#include <linux/mmu_notifier.h>
229456fc 17#include <linux/tracepoint.h>
f5f48ee1 18#include <linux/cpumask.h>
f5132b01 19#include <linux/irq_work.h>
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20
21#include <linux/kvm.h>
22#include <linux/kvm_para.h>
edf88417 23#include <linux/kvm_types.h>
f5132b01 24#include <linux/perf_event.h>
34c16eec 25
50d0a0f9 26#include <asm/pvclock-abi.h>
e01a1b57 27#include <asm/desc.h>
0bed3b56 28#include <asm/mtrr.h>
9962d032 29#include <asm/msr-index.h>
3ee89722 30#include <asm/asm.h>
e01a1b57 31
8c3ba334 32#define KVM_MAX_VCPUS 254
a59cb29e 33#define KVM_SOFT_MAX_VCPUS 160
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34#define KVM_MEMORY_SLOTS 32
35/* memory slots that does not exposed to userspace */
36#define KVM_PRIVATE_MEM_SLOTS 4
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37#define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS)
38
cef4dea0 39#define KVM_MMIO_SIZE 16
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40
41#define KVM_PIO_PAGE_OFFSET 1
542472b5 42#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
69a9f69b 43
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44#define CR0_RESERVED_BITS \
45 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
46 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
47 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
48
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49#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
50#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
ad756a16 51#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL
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52#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \
53 0xFFFFFF0000000000ULL)
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54#define CR4_RESERVED_BITS \
55 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
56 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
ad756a16 57 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
d9c3476d 58 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \
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59 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
60
61#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
62
63
cd6e8f87 64
cd6e8f87 65#define INVALID_PAGE (~(hpa_t)0)
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66#define VALID_PAGE(x) ((x) != INVALID_PAGE)
67
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68#define UNMAPPED_GVA (~(gpa_t)0)
69
ec04b260 70/* KVM Hugepage definitions for x86 */
04326caa 71#define KVM_NR_PAGE_SIZES 3
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72#define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
73#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
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74#define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
75#define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
76#define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
05da4558 77
cd6e8f87 78#define DE_VECTOR 0
19bd8afd 79#define DB_VECTOR 1
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80#define BP_VECTOR 3
81#define OF_VECTOR 4
82#define BR_VECTOR 5
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83#define UD_VECTOR 6
84#define NM_VECTOR 7
85#define DF_VECTOR 8
86#define TS_VECTOR 10
87#define NP_VECTOR 11
88#define SS_VECTOR 12
89#define GP_VECTOR 13
90#define PF_VECTOR 14
77ab6db0 91#define MF_VECTOR 16
53371b50 92#define MC_VECTOR 18
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93
94#define SELECTOR_TI_MASK (1 << 2)
95#define SELECTOR_RPL_MASK 0x03
96
97#define IOPL_SHIFT 12
98
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99#define KVM_PERMILLE_MMU_PAGES 20
100#define KVM_MIN_ALLOC_MMU_PAGES 64
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101#define KVM_MMU_HASH_SHIFT 10
102#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
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103#define KVM_MIN_FREE_MMU_PAGES 5
104#define KVM_REFILL_PAGES 25
73c1160c 105#define KVM_MAX_CPUID_ENTRIES 80
0bed3b56 106#define KVM_NR_FIXED_MTRR_REGION 88
9ba075a6 107#define KVM_NR_VAR_MTRR 8
d657a98e 108
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109#define ASYNC_PF_PER_VCPU 64
110
e935b837 111extern raw_spinlock_t kvm_lock;
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112extern struct list_head vm_list;
113
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114struct kvm_vcpu;
115struct kvm;
af585b92 116struct kvm_async_pf;
d657a98e 117
5fdbf976 118enum kvm_reg {
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119 VCPU_REGS_RAX = 0,
120 VCPU_REGS_RCX = 1,
121 VCPU_REGS_RDX = 2,
122 VCPU_REGS_RBX = 3,
123 VCPU_REGS_RSP = 4,
124 VCPU_REGS_RBP = 5,
125 VCPU_REGS_RSI = 6,
126 VCPU_REGS_RDI = 7,
127#ifdef CONFIG_X86_64
128 VCPU_REGS_R8 = 8,
129 VCPU_REGS_R9 = 9,
130 VCPU_REGS_R10 = 10,
131 VCPU_REGS_R11 = 11,
132 VCPU_REGS_R12 = 12,
133 VCPU_REGS_R13 = 13,
134 VCPU_REGS_R14 = 14,
135 VCPU_REGS_R15 = 15,
136#endif
5fdbf976 137 VCPU_REGS_RIP,
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138 NR_VCPU_REGS
139};
140
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141enum kvm_reg_ex {
142 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
aff48baa 143 VCPU_EXREG_CR3,
6de12732 144 VCPU_EXREG_RFLAGS,
69c73028 145 VCPU_EXREG_CPL,
2fb92db1 146 VCPU_EXREG_SEGMENTS,
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147};
148
2b3ccfa0 149enum {
81609e3e 150 VCPU_SREG_ES,
2b3ccfa0 151 VCPU_SREG_CS,
81609e3e 152 VCPU_SREG_SS,
2b3ccfa0 153 VCPU_SREG_DS,
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154 VCPU_SREG_FS,
155 VCPU_SREG_GS,
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156 VCPU_SREG_TR,
157 VCPU_SREG_LDTR,
158};
159
56e82318 160#include <asm/kvm_emulate.h>
2b3ccfa0 161
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162#define KVM_NR_MEM_OBJS 40
163
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164#define KVM_NR_DB_REGS 4
165
166#define DR6_BD (1 << 13)
167#define DR6_BS (1 << 14)
168#define DR6_FIXED_1 0xffff0ff0
169#define DR6_VOLATILE 0x0000e00f
170
171#define DR7_BP_EN_MASK 0x000000ff
172#define DR7_GE (1 << 9)
173#define DR7_GD (1 << 13)
174#define DR7_FIXED_1 0x00000400
175#define DR7_VOLATILE 0xffff23ff
176
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177/* apic attention bits */
178#define KVM_APIC_CHECK_VAPIC 0
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179/*
180 * The following bit is set with PV-EOI, unset on EOI.
181 * We detect PV-EOI changes by guest by comparing
182 * this bit with PV-EOI in guest memory.
183 * See the implementation in apic_update_pv_eoi.
184 */
185#define KVM_APIC_PV_EOI_PENDING 1
41383771 186
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187/*
188 * We don't want allocation failures within the mmu code, so we preallocate
189 * enough memory for a single page fault in a cache.
190 */
191struct kvm_mmu_memory_cache {
192 int nobjs;
193 void *objects[KVM_NR_MEM_OBJS];
194};
195
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196/*
197 * kvm_mmu_page_role, below, is defined as:
198 *
199 * bits 0:3 - total guest paging levels (2-4, or zero for real mode)
200 * bits 4:7 - page table level for this shadow (1-4)
201 * bits 8:9 - page table quadrant for 2-level guests
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202 * bit 16 - direct mapping of virtual to physical mapping at gfn
203 * used for real mode and two-dimensional paging
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204 * bits 17:19 - common access permissions for all ptes in this shadow page
205 */
206union kvm_mmu_page_role {
207 unsigned word;
208 struct {
7d76b4d3 209 unsigned level:4;
5b7e0102 210 unsigned cr4_pae:1;
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211 unsigned quadrant:2;
212 unsigned pad_for_nice_hex_output:6;
f6e2c02b 213 unsigned direct:1;
7d76b4d3 214 unsigned access:3;
2e53d63a 215 unsigned invalid:1;
9645bb56 216 unsigned nxe:1;
3dbe1415 217 unsigned cr0_wp:1;
411c588d 218 unsigned smep_andnot_wp:1;
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219 };
220};
221
222struct kvm_mmu_page {
223 struct list_head link;
224 struct hlist_node hash_link;
225
226 /*
227 * The following two entries are used to key the shadow page in the
228 * hash table.
229 */
230 gfn_t gfn;
231 union kvm_mmu_page_role role;
232
233 u64 *spt;
234 /* hold the gfn of each spte inside spt */
235 gfn_t *gfns;
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236 /*
237 * One bit set per slot which has memory
238 * in this shadow page.
239 */
93a5cef0 240 DECLARE_BITMAP(slot_bitmap, KVM_MEM_SLOTS_NUM);
4731d4c7 241 bool unsync;
0571d366 242 int root_count; /* Currently serving as active root */
60c8aec6 243 unsigned int unsync_children;
67052b35 244 unsigned long parent_ptes; /* Reverse mapping for parent_pte */
0074ff63 245 DECLARE_BITMAP(unsync_child_bitmap, 512);
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246
247#ifdef CONFIG_X86_32
248 int clear_spte_count;
249#endif
250
a30f47cb 251 int write_flooding_count;
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252};
253
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254struct kvm_pio_request {
255 unsigned long count;
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256 int in;
257 int port;
258 int size;
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259};
260
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261/*
262 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level
263 * 32-bit). The kvm_mmu structure abstracts the details of the current mmu
264 * mode.
265 */
266struct kvm_mmu {
267 void (*new_cr3)(struct kvm_vcpu *vcpu);
f43addd4 268 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
5777ed34 269 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
e4e517b4 270 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
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271 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
272 bool prefault);
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273 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
274 struct x86_exception *fault);
d657a98e 275 void (*free)(struct kvm_vcpu *vcpu);
1871c602 276 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
ab9ae313 277 struct x86_exception *exception);
c30a358d 278 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
e8bc217a 279 int (*sync_page)(struct kvm_vcpu *vcpu,
a4a8e6f7 280 struct kvm_mmu_page *sp);
a7052897 281 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
0f53b5b1 282 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
7c562522 283 u64 *spte, const void *pte);
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284 hpa_t root_hpa;
285 int root_level;
286 int shadow_root_level;
a770f6f2 287 union kvm_mmu_page_role base_role;
c5a78f2b 288 bool direct_map;
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289
290 u64 *pae_root;
81407ca5 291 u64 *lm_root;
82725b20 292 u64 rsvd_bits_mask[2][4];
ff03a073 293
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294 bool nx;
295
ff03a073 296 u64 pdptrs[4]; /* pae */
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297};
298
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299enum pmc_type {
300 KVM_PMC_GP = 0,
301 KVM_PMC_FIXED,
302};
303
304struct kvm_pmc {
305 enum pmc_type type;
306 u8 idx;
307 u64 counter;
308 u64 eventsel;
309 struct perf_event *perf_event;
310 struct kvm_vcpu *vcpu;
311};
312
313struct kvm_pmu {
314 unsigned nr_arch_gp_counters;
315 unsigned nr_arch_fixed_counters;
316 unsigned available_event_types;
317 u64 fixed_ctr_ctrl;
318 u64 global_ctrl;
319 u64 global_status;
320 u64 global_ovf_ctrl;
321 u64 counter_bitmask[2];
322 u64 global_ctrl_mask;
323 u8 version;
324 struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC];
325 struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED];
326 struct irq_work irq_work;
327 u64 reprogram_pmi;
328};
329
ad312c7c 330struct kvm_vcpu_arch {
5fdbf976
MT
331 /*
332 * rip and regs accesses must go through
333 * kvm_{register,rip}_{read,write} functions.
334 */
335 unsigned long regs[NR_VCPU_REGS];
336 u32 regs_avail;
337 u32 regs_dirty;
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338
339 unsigned long cr0;
e8467fda 340 unsigned long cr0_guest_owned_bits;
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341 unsigned long cr2;
342 unsigned long cr3;
343 unsigned long cr4;
fc78f519 344 unsigned long cr4_guest_owned_bits;
34c16eec 345 unsigned long cr8;
1371d904 346 u32 hflags;
f6801dff 347 u64 efer;
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348 u64 apic_base;
349 struct kvm_lapic *apic; /* kernel irqchip context */
41383771 350 unsigned long apic_attention;
e1035715 351 int32_t apic_arb_prio;
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352 int mp_state;
353 int sipi_vector;
354 u64 ia32_misc_enable_msr;
b209749f 355 bool tpr_access_reporting;
34c16eec 356
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357 /*
358 * Paging state of the vcpu
359 *
360 * If the vcpu runs in guest mode with two level paging this still saves
361 * the paging mode of the l1 guest. This context is always used to
362 * handle faults.
363 */
34c16eec 364 struct kvm_mmu mmu;
8df25a32 365
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366 /*
367 * Paging state of an L2 guest (used for nested npt)
368 *
369 * This context will save all necessary information to walk page tables
370 * of the an L2 guest. This context is only initialized for page table
371 * walking and not for faulting since we never handle l2 page faults on
372 * the host.
373 */
374 struct kvm_mmu nested_mmu;
375
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376 /*
377 * Pointer to the mmu context currently used for
378 * gva_to_gpa translations.
379 */
380 struct kvm_mmu *walk_mmu;
381
53c07b18 382 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
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383 struct kvm_mmu_memory_cache mmu_page_cache;
384 struct kvm_mmu_memory_cache mmu_page_header_cache;
385
98918833 386 struct fpu guest_fpu;
2acf923e 387 u64 xcr0;
34c16eec 388
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389 struct kvm_pio_request pio;
390 void *pio_data;
391
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392 u8 event_exit_inst_len;
393
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394 struct kvm_queued_exception {
395 bool pending;
396 bool has_error_code;
ce7ddec4 397 bool reinject;
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398 u8 nr;
399 u32 error_code;
400 } exception;
401
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402 struct kvm_queued_interrupt {
403 bool pending;
66fd3f7f 404 bool soft;
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405 u8 nr;
406 } interrupt;
407
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408 int halt_request; /* real mode on Intel only */
409
410 int cpuid_nent;
07716717 411 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
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412 /* emulate context */
413
414 struct x86_emulate_ctxt emulate_ctxt;
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415 bool emulate_regs_need_sync_to_vcpu;
416 bool emulate_regs_need_sync_from_vcpu;
18068523
GOC
417
418 gpa_t time;
50d0a0f9 419 struct pvclock_vcpu_time_info hv_clock;
e48672fa 420 unsigned int hw_tsc_khz;
18068523
GOC
421 unsigned int time_offset;
422 struct page *time_page;
c9aaa895
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423
424 struct {
425 u64 msr_val;
426 u64 last_steal;
427 u64 accum_steal;
428 struct gfn_to_hva_cache stime;
429 struct kvm_steal_time steal;
430 } st;
431
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432 u64 last_guest_tsc;
433 u64 last_kernel_ns;
6f526ec5 434 u64 last_host_tsc;
0dd6a6ed 435 u64 tsc_offset_adjustment;
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436 u64 this_tsc_nsec;
437 u64 this_tsc_write;
438 u8 this_tsc_generation;
c285545f 439 bool tsc_catchup;
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440 bool tsc_always_catchup;
441 s8 virtual_tsc_shift;
442 u32 virtual_tsc_mult;
443 u32 virtual_tsc_khz;
3419ffc8 444
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445 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
446 unsigned nmi_pending; /* NMI queued after currently running handler */
447 bool nmi_injected; /* Trying to inject an NMI this entry */
9ba075a6 448
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SY
449 struct mtrr_state_type mtrr_state;
450 u32 pat;
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JK
451
452 int switch_db_regs;
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453 unsigned long db[KVM_NR_DB_REGS];
454 unsigned long dr6;
455 unsigned long dr7;
456 unsigned long eff_db[KVM_NR_DB_REGS];
890ca9ae
HY
457
458 u64 mcg_cap;
459 u64 mcg_status;
460 u64 mcg_ctl;
461 u64 *mce_banks;
94fe45da 462
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XG
463 /* Cache MMIO info */
464 u64 mmio_gva;
465 unsigned access;
466 gfn_t mmio_gfn;
467
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GN
468 struct kvm_pmu pmu;
469
94fe45da 470 /* used for guest single stepping over the given code position */
94fe45da 471 unsigned long singlestep_rip;
f92653ee 472
10388a07
GN
473 /* fields used by HYPER-V emulation */
474 u64 hv_vapic;
f5f48ee1
SY
475
476 cpumask_var_t wbinvd_dirty_mask;
af585b92 477
1cb3f3ae
XG
478 unsigned long last_retry_eip;
479 unsigned long last_retry_addr;
480
af585b92
GN
481 struct {
482 bool halted;
483 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
344d9588
GN
484 struct gfn_to_hva_cache data;
485 u64 msr_val;
7c90705b 486 u32 id;
6adba527 487 bool send_user_only;
af585b92 488 } apf;
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BO
489
490 /* OSVW MSRs (AMD only) */
491 struct {
492 u64 length;
493 u64 status;
494 } osvw;
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MT
495
496 struct {
497 u64 msr_val;
498 struct gfn_to_hva_cache data;
499 } pv_eoi;
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ZX
500};
501
db3fe4eb
TY
502struct kvm_lpage_info {
503 unsigned long rmap_pde;
504 int write_count;
505};
506
507struct kvm_arch_memory_slot {
508 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
509};
510
fef9cce0 511struct kvm_arch {
49d5ca26 512 unsigned int n_used_mmu_pages;
f05e70ac 513 unsigned int n_requested_mmu_pages;
39de71ec 514 unsigned int n_max_mmu_pages;
332b207d 515 unsigned int indirect_shadow_pages;
f05e70ac
ZX
516 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
517 /*
518 * Hash table of struct kvm_mmu_page.
519 */
520 struct list_head active_mmu_pages;
4d5c5d0f 521 struct list_head assigned_dev_head;
19de40a8 522 struct iommu_domain *iommu_domain;
522c68c4 523 int iommu_flags;
d7deeeb0
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524 struct kvm_pic *vpic;
525 struct kvm_ioapic *vioapic;
7837699f 526 struct kvm_pit *vpit;
cc6e462c 527 int vapics_in_nmi_mode;
bfc6d222 528
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ZX
529 unsigned int tss_addr;
530 struct page *apic_access_page;
18068523
GOC
531
532 gpa_t wall_clock;
b7ebfb05
SY
533
534 struct page *ept_identity_pagetable;
535 bool ept_identity_pagetable_done;
b927a3ce 536 gpa_t ept_identity_map_addr;
5550af4d
SY
537
538 unsigned long irq_sources_bitmap;
afbcf7ab 539 s64 kvmclock_offset;
038f8c11 540 raw_spinlock_t tsc_write_lock;
f38e098f 541 u64 last_tsc_nsec;
f38e098f 542 u64 last_tsc_write;
5d3cb0f6 543 u32 last_tsc_khz;
e26101b1
ZA
544 u64 cur_tsc_nsec;
545 u64 cur_tsc_write;
546 u64 cur_tsc_offset;
547 u8 cur_tsc_generation;
ffde22ac
ES
548
549 struct kvm_xen_hvm_config xen_hvm_config;
55cd8e5a
GN
550
551 /* fields used by HYPER-V emulation */
552 u64 hv_guest_os_id;
553 u64 hv_hypercall;
b034cf01
XG
554
555 #ifdef CONFIG_KVM_MMU_AUDIT
556 int audit_point;
557 #endif
d69fb81f
ZX
558};
559
0711456c
ZX
560struct kvm_vm_stat {
561 u32 mmu_shadow_zapped;
562 u32 mmu_pte_write;
563 u32 mmu_pte_updated;
564 u32 mmu_pde_zapped;
565 u32 mmu_flooded;
566 u32 mmu_recycled;
dfc5aa00 567 u32 mmu_cache_miss;
4731d4c7 568 u32 mmu_unsync;
0711456c 569 u32 remote_tlb_flush;
05da4558 570 u32 lpages;
0711456c
ZX
571};
572
77b4c255
ZX
573struct kvm_vcpu_stat {
574 u32 pf_fixed;
575 u32 pf_guest;
576 u32 tlb_flush;
577 u32 invlpg;
578
579 u32 exits;
580 u32 io_exits;
581 u32 mmio_exits;
582 u32 signal_exits;
583 u32 irq_window_exits;
f08864b4 584 u32 nmi_window_exits;
77b4c255
ZX
585 u32 halt_exits;
586 u32 halt_wakeup;
587 u32 request_irq_exits;
588 u32 irq_exits;
589 u32 host_state_reload;
590 u32 efer_reload;
591 u32 fpu_reload;
592 u32 insn_emulation;
593 u32 insn_emulation_fail;
f11c3a8d 594 u32 hypercalls;
fa89a817 595 u32 irq_injections;
c4abb7c9 596 u32 nmi_injections;
77b4c255 597};
ad312c7c 598
8a76d7f2
JR
599struct x86_instruction_info;
600
ea4a5ff8
ZX
601struct kvm_x86_ops {
602 int (*cpu_has_kvm_support)(void); /* __init */
603 int (*disabled_by_bios)(void); /* __init */
10474ae8 604 int (*hardware_enable)(void *dummy);
ea4a5ff8
ZX
605 void (*hardware_disable)(void *dummy);
606 void (*check_processor_compatibility)(void *rtn);
607 int (*hardware_setup)(void); /* __init */
608 void (*hardware_unsetup)(void); /* __exit */
774ead3a 609 bool (*cpu_has_accelerated_tpr)(void);
0e851880 610 void (*cpuid_update)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
611
612 /* Create, but do not attach this VCPU */
613 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
614 void (*vcpu_free)(struct kvm_vcpu *vcpu);
615 int (*vcpu_reset)(struct kvm_vcpu *vcpu);
616
617 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
618 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
619 void (*vcpu_put)(struct kvm_vcpu *vcpu);
ea4a5ff8 620
355be0b9
JK
621 void (*set_guest_debug)(struct kvm_vcpu *vcpu,
622 struct kvm_guest_debug *dbg);
ea4a5ff8
ZX
623 int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
624 int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
625 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
626 void (*get_segment)(struct kvm_vcpu *vcpu,
627 struct kvm_segment *var, int seg);
2e4d2653 628 int (*get_cpl)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
629 void (*set_segment)(struct kvm_vcpu *vcpu,
630 struct kvm_segment *var, int seg);
631 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
e8467fda 632 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
aff48baa 633 void (*decache_cr3)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
634 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
635 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
636 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
5e1746d6 637 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
ea4a5ff8 638 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
89a27f4d
GN
639 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
640 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
641 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
642 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
020df079 643 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
5fdbf976 644 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
ea4a5ff8
ZX
645 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
646 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
6b52d186 647 void (*fpu_activate)(struct kvm_vcpu *vcpu);
02daab21 648 void (*fpu_deactivate)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
649
650 void (*tlb_flush)(struct kvm_vcpu *vcpu);
ea4a5ff8 651
851ba692
AK
652 void (*run)(struct kvm_vcpu *vcpu);
653 int (*handle_exit)(struct kvm_vcpu *vcpu);
ea4a5ff8 654 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
2809f5d2
GC
655 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
656 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
ea4a5ff8
ZX
657 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
658 unsigned char *hypercall_addr);
66fd3f7f 659 void (*set_irq)(struct kvm_vcpu *vcpu);
95ba8273 660 void (*set_nmi)(struct kvm_vcpu *vcpu);
298101da 661 void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
662 bool has_error_code, u32 error_code,
663 bool reinject);
b463a6f7 664 void (*cancel_injection)(struct kvm_vcpu *vcpu);
78646121 665 int (*interrupt_allowed)(struct kvm_vcpu *vcpu);
95ba8273 666 int (*nmi_allowed)(struct kvm_vcpu *vcpu);
3cfc3092
JK
667 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
668 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
95ba8273
GN
669 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
670 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
671 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
ea4a5ff8 672 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
67253af5 673 int (*get_tdp_level)(void);
4b12f0de 674 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
17cc3935 675 int (*get_lpage_level)(void);
4e47c7a6 676 bool (*rdtscp_supported)(void);
ad756a16 677 bool (*invpcid_supported)(void);
f1e2b260 678 void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host);
344f414f 679
1c97f0a0
JR
680 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
681
d4330ef2
JR
682 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry);
683
f5f48ee1
SY
684 bool (*has_wbinvd_exit)(void);
685
cc578287 686 void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale);
99e3e30a
ZA
687 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
688
857e4099 689 u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc);
d5c1785d 690 u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu);
857e4099 691
586f9607 692 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2);
8a76d7f2
JR
693
694 int (*check_intercept)(struct kvm_vcpu *vcpu,
695 struct x86_instruction_info *info,
696 enum x86_intercept_stage stage);
ea4a5ff8
ZX
697};
698
af585b92 699struct kvm_arch_async_pf {
7c90705b 700 u32 token;
af585b92 701 gfn_t gfn;
fb67e14f 702 unsigned long cr3;
c4806acd 703 bool direct_map;
af585b92
GN
704};
705
97896d04
ZX
706extern struct kvm_x86_ops *kvm_x86_ops;
707
f1e2b260
MT
708static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
709 s64 adjustment)
710{
711 kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false);
712}
713
714static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
715{
716 kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true);
717}
718
54f1585a
ZX
719int kvm_mmu_module_init(void);
720void kvm_mmu_module_exit(void);
721
722void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
723int kvm_mmu_create(struct kvm_vcpu *vcpu);
724int kvm_mmu_setup(struct kvm_vcpu *vcpu);
7b52345e 725void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 726 u64 dirty_mask, u64 nx_mask, u64 x_mask);
54f1585a
ZX
727
728int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
729void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
5dc99b23
TY
730void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
731 struct kvm_memory_slot *slot,
732 gfn_t gfn_offset, unsigned long mask);
54f1585a 733void kvm_mmu_zap_all(struct kvm *kvm);
3ad82a7e 734unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
54f1585a
ZX
735void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
736
ff03a073 737int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
cc4b6871 738
3200f405 739int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 740 const void *val, int bytes);
4b12f0de 741u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
2f333bcb
MT
742
743extern bool tdp_enabled;
9f811285 744
a3e06bbe
LJ
745u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
746
92a1f12d
JR
747/* control of guest tsc rate supported? */
748extern bool kvm_has_tsc_control;
749/* minimum supported tsc_khz for guests */
750extern u32 kvm_min_guest_tsc_khz;
751/* maximum supported tsc_khz for guests */
752extern u32 kvm_max_guest_tsc_khz;
753
54f1585a
ZX
754enum emulation_result {
755 EMULATE_DONE, /* no further processing */
756 EMULATE_DO_MMIO, /* kvm_run filled with mmio request */
757 EMULATE_FAIL, /* can't emulate this instruction */
758};
759
571008da
SY
760#define EMULTYPE_NO_DECODE (1 << 0)
761#define EMULTYPE_TRAP_UD (1 << 1)
ba8afb6b 762#define EMULTYPE_SKIP (1 << 2)
1cb3f3ae 763#define EMULTYPE_RETRY (1 << 3)
dc25e89e
AP
764int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
765 int emulation_type, void *insn, int insn_len);
51d8b661
AP
766
767static inline int emulate_instruction(struct kvm_vcpu *vcpu,
768 int emulation_type)
769{
dc25e89e 770 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
51d8b661
AP
771}
772
f2b4b7dd 773void kvm_enable_efer_bits(u64);
54f1585a
ZX
774int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data);
775int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
776
777struct x86_emulate_ctxt;
778
cf8f70bf 779int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port);
54f1585a
ZX
780void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
781int kvm_emulate_halt(struct kvm_vcpu *vcpu);
f5f48ee1 782int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
54f1585a 783
3e6e0aab 784void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
c697518a 785int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
3e6e0aab 786
7f3d35fd
KW
787int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
788 int reason, bool has_error_code, u32 error_code);
37817f29 789
49a9b07e 790int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
2390218b 791int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
a83b29c6 792int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
eea1cff9 793int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
020df079
GN
794int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
795int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
2d3ad1f4
AK
796unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
797void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
54f1585a 798void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
2acf923e 799int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
54f1585a
ZX
800
801int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
802int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
803
91586a3b
JK
804unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
805void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
022cd0e8 806bool kvm_rdpmc(struct kvm_vcpu *vcpu);
91586a3b 807
298101da
AK
808void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
809void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
ce7ddec4
JR
810void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
811void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
6389ee94 812void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
ec92fe44
JR
813int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
814 gfn_t gfn, void *data, int offset, int len,
815 u32 access);
6389ee94 816void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
0a79b009 817bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
298101da 818
4925663a 819int kvm_pic_set_irq(void *opaque, int irq, int level);
3de42dc0 820
3419ffc8
SY
821void kvm_inject_nmi(struct kvm_vcpu *vcpu);
822
10ab25cd 823int fx_init(struct kvm_vcpu *vcpu);
54f1585a 824
d835dfec 825void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
54f1585a 826void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
f57f2ef5 827 const u8 *new, int bytes);
1cb3f3ae 828int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
54f1585a
ZX
829int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
830void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
831int kvm_mmu_load(struct kvm_vcpu *vcpu);
832void kvm_mmu_unload(struct kvm_vcpu *vcpu);
0ba73cda 833void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
e459e322 834gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
ab9ae313
AK
835gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
836 struct x86_exception *exception);
837gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
838 struct x86_exception *exception);
839gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
840 struct x86_exception *exception);
841gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
842 struct x86_exception *exception);
54f1585a
ZX
843
844int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
845
dc25e89e
AP
846int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
847 void *insn, int insn_len);
a7052897 848void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
34c16eec 849
18552672 850void kvm_enable_tdp(void);
5f4cb662 851void kvm_disable_tdp(void);
18552672 852
de7d789a 853int complete_pio(struct kvm_vcpu *vcpu);
f850e2e6 854bool kvm_check_iopl(struct kvm_vcpu *vcpu);
ec6d273d 855
e459e322
XG
856static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
857{
858 return gpa;
859}
860
ec6d273d
ZX
861static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
862{
863 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
864
865 return (struct kvm_mmu_page *)page_private(page);
866}
867
d6e88aec 868static inline u16 kvm_read_ldt(void)
ec6d273d
ZX
869{
870 u16 ldt;
871 asm("sldt %0" : "=g"(ldt));
872 return ldt;
873}
874
d6e88aec 875static inline void kvm_load_ldt(u16 sel)
ec6d273d
ZX
876{
877 asm("lldt %0" : : "rm"(sel));
878}
ec6d273d 879
ec6d273d
ZX
880#ifdef CONFIG_X86_64
881static inline unsigned long read_msr(unsigned long msr)
882{
883 u64 value;
884
885 rdmsrl(msr, value);
886 return value;
887}
888#endif
889
ec6d273d
ZX
890static inline u32 get_rdx_init_val(void)
891{
892 return 0x600; /* P6 family */
893}
894
c1a5d4f9
AK
895static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
896{
897 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
898}
899
ec6d273d
ZX
900#define TSS_IOPB_BASE_OFFSET 0x66
901#define TSS_BASE_SIZE 0x68
902#define TSS_IOPB_SIZE (65536 / 8)
903#define TSS_REDIRECTION_SIZE (256 / 8)
7d76b4d3
JP
904#define RMODE_TSS_SIZE \
905 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
53e0aa7b 906
37817f29
IE
907enum {
908 TASK_SWITCH_CALL = 0,
909 TASK_SWITCH_IRET = 1,
910 TASK_SWITCH_JMP = 2,
911 TASK_SWITCH_GATE = 3,
912};
913
1371d904 914#define HF_GIF_MASK (1 << 0)
3d6368ef
AG
915#define HF_HIF_MASK (1 << 1)
916#define HF_VINTR_MASK (1 << 2)
95ba8273 917#define HF_NMI_MASK (1 << 3)
44c11430 918#define HF_IRET_MASK (1 << 4)
ec9e60b2 919#define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
1371d904 920
4ecac3fd
AK
921/*
922 * Hardware virtualization extension instructions may fault if a
923 * reboot turns off virtualization while processes are running.
924 * Trap the fault and ignore the instruction if that happens.
925 */
b7c4145b
AK
926asmlinkage void kvm_spurious_fault(void);
927extern bool kvm_rebooting;
4ecac3fd 928
5e520e62 929#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \
4ecac3fd 930 "666: " insn "\n\t" \
b7c4145b 931 "668: \n\t" \
18b13e54 932 ".pushsection .fixup, \"ax\" \n" \
4ecac3fd 933 "667: \n\t" \
5e520e62 934 cleanup_insn "\n\t" \
b7c4145b
AK
935 "cmpb $0, kvm_rebooting \n\t" \
936 "jne 668b \n\t" \
8ceed347 937 __ASM_SIZE(push) " $666b \n\t" \
b7c4145b 938 "call kvm_spurious_fault \n\t" \
4ecac3fd 939 ".popsection \n\t" \
3ee89722 940 _ASM_EXTABLE(666b, 667b)
4ecac3fd 941
5e520e62
AK
942#define __kvm_handle_fault_on_reboot(insn) \
943 ____kvm_handle_fault_on_reboot(insn, "")
944
e930bffe
AA
945#define KVM_ARCH_WANT_MMU_NOTIFIER
946int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
947int kvm_age_hva(struct kvm *kvm, unsigned long hva);
8ee53820 948int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
3da0dd43 949void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
82725b20 950int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
a1b37100
GN
951int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
952int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
0b71785d 953int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
e930bffe 954
18863bdd 955void kvm_define_shared_msr(unsigned index, u32 msr);
d5696725 956void kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
18863bdd 957
f92653ee
JK
958bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
959
af585b92
GN
960void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
961 struct kvm_async_pf *work);
962void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
963 struct kvm_async_pf *work);
56028d08
GN
964void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
965 struct kvm_async_pf *work);
7c90705b 966bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu);
af585b92
GN
967extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
968
db8fcefa
AP
969void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
970
f5132b01
GN
971int kvm_is_in_guest(void);
972
973void kvm_pmu_init(struct kvm_vcpu *vcpu);
974void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
975void kvm_pmu_reset(struct kvm_vcpu *vcpu);
976void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu);
977bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr);
978int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
979int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
980int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
981void kvm_handle_pmu_event(struct kvm_vcpu *vcpu);
982void kvm_deliver_pmi(struct kvm_vcpu *vcpu);
983
1965aae3 984#endif /* _ASM_X86_KVM_HOST_H */