]>
Commit | Line | Data |
---|---|---|
a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
34c16eec | 25 | |
50d0a0f9 | 26 | #include <asm/pvclock-abi.h> |
e01a1b57 | 27 | #include <asm/desc.h> |
0bed3b56 | 28 | #include <asm/mtrr.h> |
9962d032 | 29 | #include <asm/msr-index.h> |
3ee89722 | 30 | #include <asm/asm.h> |
e01a1b57 | 31 | |
8c3ba334 | 32 | #define KVM_MAX_VCPUS 254 |
a59cb29e | 33 | #define KVM_SOFT_MAX_VCPUS 160 |
69a9f69b AK |
34 | #define KVM_MEMORY_SLOTS 32 |
35 | /* memory slots that does not exposed to userspace */ | |
36 | #define KVM_PRIVATE_MEM_SLOTS 4 | |
93a5cef0 XG |
37 | #define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
38 | ||
cef4dea0 | 39 | #define KVM_MMIO_SIZE 16 |
69a9f69b AK |
40 | |
41 | #define KVM_PIO_PAGE_OFFSET 1 | |
542472b5 | 42 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
69a9f69b | 43 | |
cfec82cb JR |
44 | #define CR0_RESERVED_BITS \ |
45 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
46 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
47 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
48 | ||
cd6e8f87 ZX |
49 | #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) |
50 | #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) | |
ad756a16 | 51 | #define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL |
7d76b4d3 JP |
52 | #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ |
53 | 0xFFFFFF0000000000ULL) | |
cfec82cb JR |
54 | #define CR4_RESERVED_BITS \ |
55 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
56 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 57 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
d9c3476d | 58 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \ |
cfec82cb JR |
59 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
60 | ||
61 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
62 | ||
63 | ||
cd6e8f87 | 64 | |
cd6e8f87 | 65 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
66 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
67 | ||
cd6e8f87 ZX |
68 | #define UNMAPPED_GVA (~(gpa_t)0) |
69 | ||
ec04b260 | 70 | /* KVM Hugepage definitions for x86 */ |
04326caa | 71 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
72 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
73 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
74 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
75 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
76 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 77 | |
cd6e8f87 | 78 | #define DE_VECTOR 0 |
19bd8afd | 79 | #define DB_VECTOR 1 |
77ab6db0 JK |
80 | #define BP_VECTOR 3 |
81 | #define OF_VECTOR 4 | |
82 | #define BR_VECTOR 5 | |
cd6e8f87 ZX |
83 | #define UD_VECTOR 6 |
84 | #define NM_VECTOR 7 | |
85 | #define DF_VECTOR 8 | |
86 | #define TS_VECTOR 10 | |
87 | #define NP_VECTOR 11 | |
88 | #define SS_VECTOR 12 | |
89 | #define GP_VECTOR 13 | |
90 | #define PF_VECTOR 14 | |
77ab6db0 | 91 | #define MF_VECTOR 16 |
53371b50 | 92 | #define MC_VECTOR 18 |
cd6e8f87 ZX |
93 | |
94 | #define SELECTOR_TI_MASK (1 << 2) | |
95 | #define SELECTOR_RPL_MASK 0x03 | |
96 | ||
97 | #define IOPL_SHIFT 12 | |
98 | ||
d657a98e ZX |
99 | #define KVM_PERMILLE_MMU_PAGES 20 |
100 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
101 | #define KVM_MMU_HASH_SHIFT 10 |
102 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
103 | #define KVM_MIN_FREE_MMU_PAGES 5 |
104 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 105 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 106 | #define KVM_NR_FIXED_MTRR_REGION 88 |
9ba075a6 | 107 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 108 | |
af585b92 GN |
109 | #define ASYNC_PF_PER_VCPU 64 |
110 | ||
e935b837 | 111 | extern raw_spinlock_t kvm_lock; |
e9b11c17 ZX |
112 | extern struct list_head vm_list; |
113 | ||
d657a98e ZX |
114 | struct kvm_vcpu; |
115 | struct kvm; | |
af585b92 | 116 | struct kvm_async_pf; |
d657a98e | 117 | |
5fdbf976 | 118 | enum kvm_reg { |
2b3ccfa0 ZX |
119 | VCPU_REGS_RAX = 0, |
120 | VCPU_REGS_RCX = 1, | |
121 | VCPU_REGS_RDX = 2, | |
122 | VCPU_REGS_RBX = 3, | |
123 | VCPU_REGS_RSP = 4, | |
124 | VCPU_REGS_RBP = 5, | |
125 | VCPU_REGS_RSI = 6, | |
126 | VCPU_REGS_RDI = 7, | |
127 | #ifdef CONFIG_X86_64 | |
128 | VCPU_REGS_R8 = 8, | |
129 | VCPU_REGS_R9 = 9, | |
130 | VCPU_REGS_R10 = 10, | |
131 | VCPU_REGS_R11 = 11, | |
132 | VCPU_REGS_R12 = 12, | |
133 | VCPU_REGS_R13 = 13, | |
134 | VCPU_REGS_R14 = 14, | |
135 | VCPU_REGS_R15 = 15, | |
136 | #endif | |
5fdbf976 | 137 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
138 | NR_VCPU_REGS |
139 | }; | |
140 | ||
6de4f3ad AK |
141 | enum kvm_reg_ex { |
142 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 143 | VCPU_EXREG_CR3, |
6de12732 | 144 | VCPU_EXREG_RFLAGS, |
69c73028 | 145 | VCPU_EXREG_CPL, |
2fb92db1 | 146 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
147 | }; |
148 | ||
2b3ccfa0 | 149 | enum { |
81609e3e | 150 | VCPU_SREG_ES, |
2b3ccfa0 | 151 | VCPU_SREG_CS, |
81609e3e | 152 | VCPU_SREG_SS, |
2b3ccfa0 | 153 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
154 | VCPU_SREG_FS, |
155 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
156 | VCPU_SREG_TR, |
157 | VCPU_SREG_LDTR, | |
158 | }; | |
159 | ||
56e82318 | 160 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 161 | |
d657a98e ZX |
162 | #define KVM_NR_MEM_OBJS 40 |
163 | ||
42dbaa5a JK |
164 | #define KVM_NR_DB_REGS 4 |
165 | ||
166 | #define DR6_BD (1 << 13) | |
167 | #define DR6_BS (1 << 14) | |
168 | #define DR6_FIXED_1 0xffff0ff0 | |
169 | #define DR6_VOLATILE 0x0000e00f | |
170 | ||
171 | #define DR7_BP_EN_MASK 0x000000ff | |
172 | #define DR7_GE (1 << 9) | |
173 | #define DR7_GD (1 << 13) | |
174 | #define DR7_FIXED_1 0x00000400 | |
175 | #define DR7_VOLATILE 0xffff23ff | |
176 | ||
41383771 GN |
177 | /* apic attention bits */ |
178 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
179 | /* |
180 | * The following bit is set with PV-EOI, unset on EOI. | |
181 | * We detect PV-EOI changes by guest by comparing | |
182 | * this bit with PV-EOI in guest memory. | |
183 | * See the implementation in apic_update_pv_eoi. | |
184 | */ | |
185 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 186 | |
d657a98e ZX |
187 | /* |
188 | * We don't want allocation failures within the mmu code, so we preallocate | |
189 | * enough memory for a single page fault in a cache. | |
190 | */ | |
191 | struct kvm_mmu_memory_cache { | |
192 | int nobjs; | |
193 | void *objects[KVM_NR_MEM_OBJS]; | |
194 | }; | |
195 | ||
d657a98e ZX |
196 | /* |
197 | * kvm_mmu_page_role, below, is defined as: | |
198 | * | |
199 | * bits 0:3 - total guest paging levels (2-4, or zero for real mode) | |
200 | * bits 4:7 - page table level for this shadow (1-4) | |
201 | * bits 8:9 - page table quadrant for 2-level guests | |
f6e2c02b AK |
202 | * bit 16 - direct mapping of virtual to physical mapping at gfn |
203 | * used for real mode and two-dimensional paging | |
d657a98e ZX |
204 | * bits 17:19 - common access permissions for all ptes in this shadow page |
205 | */ | |
206 | union kvm_mmu_page_role { | |
207 | unsigned word; | |
208 | struct { | |
7d76b4d3 | 209 | unsigned level:4; |
5b7e0102 | 210 | unsigned cr4_pae:1; |
7d76b4d3 JP |
211 | unsigned quadrant:2; |
212 | unsigned pad_for_nice_hex_output:6; | |
f6e2c02b | 213 | unsigned direct:1; |
7d76b4d3 | 214 | unsigned access:3; |
2e53d63a | 215 | unsigned invalid:1; |
9645bb56 | 216 | unsigned nxe:1; |
3dbe1415 | 217 | unsigned cr0_wp:1; |
411c588d | 218 | unsigned smep_andnot_wp:1; |
d657a98e ZX |
219 | }; |
220 | }; | |
221 | ||
222 | struct kvm_mmu_page { | |
223 | struct list_head link; | |
224 | struct hlist_node hash_link; | |
225 | ||
226 | /* | |
227 | * The following two entries are used to key the shadow page in the | |
228 | * hash table. | |
229 | */ | |
230 | gfn_t gfn; | |
231 | union kvm_mmu_page_role role; | |
232 | ||
233 | u64 *spt; | |
234 | /* hold the gfn of each spte inside spt */ | |
235 | gfn_t *gfns; | |
291f26bc SY |
236 | /* |
237 | * One bit set per slot which has memory | |
238 | * in this shadow page. | |
239 | */ | |
93a5cef0 | 240 | DECLARE_BITMAP(slot_bitmap, KVM_MEM_SLOTS_NUM); |
4731d4c7 | 241 | bool unsync; |
0571d366 | 242 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 243 | unsigned int unsync_children; |
67052b35 | 244 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
0074ff63 | 245 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
246 | |
247 | #ifdef CONFIG_X86_32 | |
248 | int clear_spte_count; | |
249 | #endif | |
250 | ||
a30f47cb | 251 | int write_flooding_count; |
d657a98e ZX |
252 | }; |
253 | ||
1c08364c AK |
254 | struct kvm_pio_request { |
255 | unsigned long count; | |
1c08364c AK |
256 | int in; |
257 | int port; | |
258 | int size; | |
1c08364c AK |
259 | }; |
260 | ||
d657a98e ZX |
261 | /* |
262 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
263 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
264 | * mode. | |
265 | */ | |
266 | struct kvm_mmu { | |
267 | void (*new_cr3)(struct kvm_vcpu *vcpu); | |
f43addd4 | 268 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 269 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 270 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
271 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
272 | bool prefault); | |
6389ee94 AK |
273 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
274 | struct x86_exception *fault); | |
d657a98e | 275 | void (*free)(struct kvm_vcpu *vcpu); |
1871c602 | 276 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 277 | struct x86_exception *exception); |
c30a358d | 278 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
e8bc217a | 279 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 280 | struct kvm_mmu_page *sp); |
a7052897 | 281 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 282 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 283 | u64 *spte, const void *pte); |
d657a98e ZX |
284 | hpa_t root_hpa; |
285 | int root_level; | |
286 | int shadow_root_level; | |
a770f6f2 | 287 | union kvm_mmu_page_role base_role; |
c5a78f2b | 288 | bool direct_map; |
d657a98e ZX |
289 | |
290 | u64 *pae_root; | |
81407ca5 | 291 | u64 *lm_root; |
82725b20 | 292 | u64 rsvd_bits_mask[2][4]; |
ff03a073 | 293 | |
2d48a985 JR |
294 | bool nx; |
295 | ||
ff03a073 | 296 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
297 | }; |
298 | ||
f5132b01 GN |
299 | enum pmc_type { |
300 | KVM_PMC_GP = 0, | |
301 | KVM_PMC_FIXED, | |
302 | }; | |
303 | ||
304 | struct kvm_pmc { | |
305 | enum pmc_type type; | |
306 | u8 idx; | |
307 | u64 counter; | |
308 | u64 eventsel; | |
309 | struct perf_event *perf_event; | |
310 | struct kvm_vcpu *vcpu; | |
311 | }; | |
312 | ||
313 | struct kvm_pmu { | |
314 | unsigned nr_arch_gp_counters; | |
315 | unsigned nr_arch_fixed_counters; | |
316 | unsigned available_event_types; | |
317 | u64 fixed_ctr_ctrl; | |
318 | u64 global_ctrl; | |
319 | u64 global_status; | |
320 | u64 global_ovf_ctrl; | |
321 | u64 counter_bitmask[2]; | |
322 | u64 global_ctrl_mask; | |
323 | u8 version; | |
15c7ad51 RR |
324 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
325 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
326 | struct irq_work irq_work; |
327 | u64 reprogram_pmi; | |
328 | }; | |
329 | ||
ad312c7c | 330 | struct kvm_vcpu_arch { |
5fdbf976 MT |
331 | /* |
332 | * rip and regs accesses must go through | |
333 | * kvm_{register,rip}_{read,write} functions. | |
334 | */ | |
335 | unsigned long regs[NR_VCPU_REGS]; | |
336 | u32 regs_avail; | |
337 | u32 regs_dirty; | |
34c16eec ZX |
338 | |
339 | unsigned long cr0; | |
e8467fda | 340 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
341 | unsigned long cr2; |
342 | unsigned long cr3; | |
343 | unsigned long cr4; | |
fc78f519 | 344 | unsigned long cr4_guest_owned_bits; |
34c16eec | 345 | unsigned long cr8; |
1371d904 | 346 | u32 hflags; |
f6801dff | 347 | u64 efer; |
34c16eec ZX |
348 | u64 apic_base; |
349 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
41383771 | 350 | unsigned long apic_attention; |
e1035715 | 351 | int32_t apic_arb_prio; |
34c16eec ZX |
352 | int mp_state; |
353 | int sipi_vector; | |
354 | u64 ia32_misc_enable_msr; | |
b209749f | 355 | bool tpr_access_reporting; |
34c16eec | 356 | |
14dfe855 JR |
357 | /* |
358 | * Paging state of the vcpu | |
359 | * | |
360 | * If the vcpu runs in guest mode with two level paging this still saves | |
361 | * the paging mode of the l1 guest. This context is always used to | |
362 | * handle faults. | |
363 | */ | |
34c16eec | 364 | struct kvm_mmu mmu; |
8df25a32 | 365 | |
6539e738 JR |
366 | /* |
367 | * Paging state of an L2 guest (used for nested npt) | |
368 | * | |
369 | * This context will save all necessary information to walk page tables | |
370 | * of the an L2 guest. This context is only initialized for page table | |
371 | * walking and not for faulting since we never handle l2 page faults on | |
372 | * the host. | |
373 | */ | |
374 | struct kvm_mmu nested_mmu; | |
375 | ||
14dfe855 JR |
376 | /* |
377 | * Pointer to the mmu context currently used for | |
378 | * gva_to_gpa translations. | |
379 | */ | |
380 | struct kvm_mmu *walk_mmu; | |
381 | ||
53c07b18 | 382 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
383 | struct kvm_mmu_memory_cache mmu_page_cache; |
384 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
385 | ||
98918833 | 386 | struct fpu guest_fpu; |
2acf923e | 387 | u64 xcr0; |
34c16eec | 388 | |
34c16eec ZX |
389 | struct kvm_pio_request pio; |
390 | void *pio_data; | |
391 | ||
66fd3f7f GN |
392 | u8 event_exit_inst_len; |
393 | ||
298101da AK |
394 | struct kvm_queued_exception { |
395 | bool pending; | |
396 | bool has_error_code; | |
ce7ddec4 | 397 | bool reinject; |
298101da AK |
398 | u8 nr; |
399 | u32 error_code; | |
400 | } exception; | |
401 | ||
937a7eae AK |
402 | struct kvm_queued_interrupt { |
403 | bool pending; | |
66fd3f7f | 404 | bool soft; |
937a7eae AK |
405 | u8 nr; |
406 | } interrupt; | |
407 | ||
34c16eec ZX |
408 | int halt_request; /* real mode on Intel only */ |
409 | ||
410 | int cpuid_nent; | |
07716717 | 411 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
34c16eec ZX |
412 | /* emulate context */ |
413 | ||
414 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
415 | bool emulate_regs_need_sync_to_vcpu; |
416 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 417 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
418 | |
419 | gpa_t time; | |
50d0a0f9 | 420 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 421 | unsigned int hw_tsc_khz; |
18068523 GOC |
422 | unsigned int time_offset; |
423 | struct page *time_page; | |
51d59c6b MT |
424 | /* set guest stopped flag in pvclock flags field */ |
425 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
426 | |
427 | struct { | |
428 | u64 msr_val; | |
429 | u64 last_steal; | |
430 | u64 accum_steal; | |
431 | struct gfn_to_hva_cache stime; | |
432 | struct kvm_steal_time steal; | |
433 | } st; | |
434 | ||
1d5f066e ZA |
435 | u64 last_guest_tsc; |
436 | u64 last_kernel_ns; | |
6f526ec5 | 437 | u64 last_host_tsc; |
0dd6a6ed | 438 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
439 | u64 this_tsc_nsec; |
440 | u64 this_tsc_write; | |
441 | u8 this_tsc_generation; | |
c285545f | 442 | bool tsc_catchup; |
cc578287 ZA |
443 | bool tsc_always_catchup; |
444 | s8 virtual_tsc_shift; | |
445 | u32 virtual_tsc_mult; | |
446 | u32 virtual_tsc_khz; | |
3419ffc8 | 447 | |
7460fb4a AK |
448 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
449 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
450 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
9ba075a6 | 451 | |
0bed3b56 SY |
452 | struct mtrr_state_type mtrr_state; |
453 | u32 pat; | |
42dbaa5a JK |
454 | |
455 | int switch_db_regs; | |
42dbaa5a JK |
456 | unsigned long db[KVM_NR_DB_REGS]; |
457 | unsigned long dr6; | |
458 | unsigned long dr7; | |
459 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
890ca9ae HY |
460 | |
461 | u64 mcg_cap; | |
462 | u64 mcg_status; | |
463 | u64 mcg_ctl; | |
464 | u64 *mce_banks; | |
94fe45da | 465 | |
bebb106a XG |
466 | /* Cache MMIO info */ |
467 | u64 mmio_gva; | |
468 | unsigned access; | |
469 | gfn_t mmio_gfn; | |
470 | ||
f5132b01 GN |
471 | struct kvm_pmu pmu; |
472 | ||
94fe45da | 473 | /* used for guest single stepping over the given code position */ |
94fe45da | 474 | unsigned long singlestep_rip; |
f92653ee | 475 | |
10388a07 GN |
476 | /* fields used by HYPER-V emulation */ |
477 | u64 hv_vapic; | |
f5f48ee1 SY |
478 | |
479 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 480 | |
1cb3f3ae XG |
481 | unsigned long last_retry_eip; |
482 | unsigned long last_retry_addr; | |
483 | ||
af585b92 GN |
484 | struct { |
485 | bool halted; | |
486 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
487 | struct gfn_to_hva_cache data; |
488 | u64 msr_val; | |
7c90705b | 489 | u32 id; |
6adba527 | 490 | bool send_user_only; |
af585b92 | 491 | } apf; |
2b036c6b BO |
492 | |
493 | /* OSVW MSRs (AMD only) */ | |
494 | struct { | |
495 | u64 length; | |
496 | u64 status; | |
497 | } osvw; | |
ae7a2a3f MT |
498 | |
499 | struct { | |
500 | u64 msr_val; | |
501 | struct gfn_to_hva_cache data; | |
502 | } pv_eoi; | |
34c16eec ZX |
503 | }; |
504 | ||
db3fe4eb | 505 | struct kvm_lpage_info { |
db3fe4eb TY |
506 | int write_count; |
507 | }; | |
508 | ||
509 | struct kvm_arch_memory_slot { | |
d89cc617 | 510 | unsigned long *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
511 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
512 | }; | |
513 | ||
fef9cce0 | 514 | struct kvm_arch { |
49d5ca26 | 515 | unsigned int n_used_mmu_pages; |
f05e70ac | 516 | unsigned int n_requested_mmu_pages; |
39de71ec | 517 | unsigned int n_max_mmu_pages; |
332b207d | 518 | unsigned int indirect_shadow_pages; |
f05e70ac ZX |
519 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
520 | /* | |
521 | * Hash table of struct kvm_mmu_page. | |
522 | */ | |
523 | struct list_head active_mmu_pages; | |
4d5c5d0f | 524 | struct list_head assigned_dev_head; |
19de40a8 | 525 | struct iommu_domain *iommu_domain; |
522c68c4 | 526 | int iommu_flags; |
d7deeeb0 ZX |
527 | struct kvm_pic *vpic; |
528 | struct kvm_ioapic *vioapic; | |
7837699f | 529 | struct kvm_pit *vpit; |
cc6e462c | 530 | int vapics_in_nmi_mode; |
bfc6d222 | 531 | |
bfc6d222 ZX |
532 | unsigned int tss_addr; |
533 | struct page *apic_access_page; | |
18068523 GOC |
534 | |
535 | gpa_t wall_clock; | |
b7ebfb05 SY |
536 | |
537 | struct page *ept_identity_pagetable; | |
538 | bool ept_identity_pagetable_done; | |
b927a3ce | 539 | gpa_t ept_identity_map_addr; |
5550af4d SY |
540 | |
541 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 542 | s64 kvmclock_offset; |
038f8c11 | 543 | raw_spinlock_t tsc_write_lock; |
f38e098f | 544 | u64 last_tsc_nsec; |
f38e098f | 545 | u64 last_tsc_write; |
5d3cb0f6 | 546 | u32 last_tsc_khz; |
e26101b1 ZA |
547 | u64 cur_tsc_nsec; |
548 | u64 cur_tsc_write; | |
549 | u64 cur_tsc_offset; | |
550 | u8 cur_tsc_generation; | |
ffde22ac ES |
551 | |
552 | struct kvm_xen_hvm_config xen_hvm_config; | |
55cd8e5a GN |
553 | |
554 | /* fields used by HYPER-V emulation */ | |
555 | u64 hv_guest_os_id; | |
556 | u64 hv_hypercall; | |
b034cf01 XG |
557 | |
558 | #ifdef CONFIG_KVM_MMU_AUDIT | |
559 | int audit_point; | |
560 | #endif | |
d69fb81f ZX |
561 | }; |
562 | ||
0711456c ZX |
563 | struct kvm_vm_stat { |
564 | u32 mmu_shadow_zapped; | |
565 | u32 mmu_pte_write; | |
566 | u32 mmu_pte_updated; | |
567 | u32 mmu_pde_zapped; | |
568 | u32 mmu_flooded; | |
569 | u32 mmu_recycled; | |
dfc5aa00 | 570 | u32 mmu_cache_miss; |
4731d4c7 | 571 | u32 mmu_unsync; |
0711456c | 572 | u32 remote_tlb_flush; |
05da4558 | 573 | u32 lpages; |
0711456c ZX |
574 | }; |
575 | ||
77b4c255 ZX |
576 | struct kvm_vcpu_stat { |
577 | u32 pf_fixed; | |
578 | u32 pf_guest; | |
579 | u32 tlb_flush; | |
580 | u32 invlpg; | |
581 | ||
582 | u32 exits; | |
583 | u32 io_exits; | |
584 | u32 mmio_exits; | |
585 | u32 signal_exits; | |
586 | u32 irq_window_exits; | |
f08864b4 | 587 | u32 nmi_window_exits; |
77b4c255 ZX |
588 | u32 halt_exits; |
589 | u32 halt_wakeup; | |
590 | u32 request_irq_exits; | |
591 | u32 irq_exits; | |
592 | u32 host_state_reload; | |
593 | u32 efer_reload; | |
594 | u32 fpu_reload; | |
595 | u32 insn_emulation; | |
596 | u32 insn_emulation_fail; | |
f11c3a8d | 597 | u32 hypercalls; |
fa89a817 | 598 | u32 irq_injections; |
c4abb7c9 | 599 | u32 nmi_injections; |
77b4c255 | 600 | }; |
ad312c7c | 601 | |
8a76d7f2 JR |
602 | struct x86_instruction_info; |
603 | ||
ea4a5ff8 ZX |
604 | struct kvm_x86_ops { |
605 | int (*cpu_has_kvm_support)(void); /* __init */ | |
606 | int (*disabled_by_bios)(void); /* __init */ | |
10474ae8 | 607 | int (*hardware_enable)(void *dummy); |
ea4a5ff8 ZX |
608 | void (*hardware_disable)(void *dummy); |
609 | void (*check_processor_compatibility)(void *rtn); | |
610 | int (*hardware_setup)(void); /* __init */ | |
611 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 612 | bool (*cpu_has_accelerated_tpr)(void); |
0e851880 | 613 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
614 | |
615 | /* Create, but do not attach this VCPU */ | |
616 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
617 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
618 | int (*vcpu_reset)(struct kvm_vcpu *vcpu); | |
619 | ||
620 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
621 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
622 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 623 | |
355be0b9 JK |
624 | void (*set_guest_debug)(struct kvm_vcpu *vcpu, |
625 | struct kvm_guest_debug *dbg); | |
ea4a5ff8 ZX |
626 | int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata); |
627 | int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
628 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); | |
629 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
630 | struct kvm_segment *var, int seg); | |
2e4d2653 | 631 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
632 | void (*set_segment)(struct kvm_vcpu *vcpu, |
633 | struct kvm_segment *var, int seg); | |
634 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 635 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 636 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
637 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
638 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
639 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 640 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 641 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
642 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
643 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
644 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
645 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
020df079 | 646 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 647 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
648 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
649 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
6b52d186 | 650 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 651 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
652 | |
653 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 654 | |
851ba692 AK |
655 | void (*run)(struct kvm_vcpu *vcpu); |
656 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 657 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 GC |
658 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
659 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); | |
ea4a5ff8 ZX |
660 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
661 | unsigned char *hypercall_addr); | |
66fd3f7f | 662 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 663 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 664 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
665 | bool has_error_code, u32 error_code, |
666 | bool reinject); | |
b463a6f7 | 667 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 668 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 669 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
670 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
671 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
95ba8273 GN |
672 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
673 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
674 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); | |
ea4a5ff8 | 675 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 676 | int (*get_tdp_level)(void); |
4b12f0de | 677 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 678 | int (*get_lpage_level)(void); |
4e47c7a6 | 679 | bool (*rdtscp_supported)(void); |
ad756a16 | 680 | bool (*invpcid_supported)(void); |
f1e2b260 | 681 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 682 | |
1c97f0a0 JR |
683 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
684 | ||
d4330ef2 JR |
685 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
686 | ||
f5f48ee1 SY |
687 | bool (*has_wbinvd_exit)(void); |
688 | ||
cc578287 | 689 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
99e3e30a ZA |
690 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
691 | ||
857e4099 | 692 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
d5c1785d | 693 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu); |
857e4099 | 694 | |
586f9607 | 695 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
696 | |
697 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
698 | struct x86_instruction_info *info, | |
699 | enum x86_intercept_stage stage); | |
ea4a5ff8 ZX |
700 | }; |
701 | ||
af585b92 | 702 | struct kvm_arch_async_pf { |
7c90705b | 703 | u32 token; |
af585b92 | 704 | gfn_t gfn; |
fb67e14f | 705 | unsigned long cr3; |
c4806acd | 706 | bool direct_map; |
af585b92 GN |
707 | }; |
708 | ||
97896d04 ZX |
709 | extern struct kvm_x86_ops *kvm_x86_ops; |
710 | ||
f1e2b260 MT |
711 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
712 | s64 adjustment) | |
713 | { | |
714 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
715 | } | |
716 | ||
717 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
718 | { | |
719 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
720 | } | |
721 | ||
54f1585a ZX |
722 | int kvm_mmu_module_init(void); |
723 | void kvm_mmu_module_exit(void); | |
724 | ||
725 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
726 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
727 | int kvm_mmu_setup(struct kvm_vcpu *vcpu); | |
7b52345e | 728 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 729 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a ZX |
730 | |
731 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu); | |
732 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot); | |
5dc99b23 TY |
733 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
734 | struct kvm_memory_slot *slot, | |
735 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 736 | void kvm_mmu_zap_all(struct kvm *kvm); |
3ad82a7e | 737 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
738 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
739 | ||
ff03a073 | 740 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 741 | |
3200f405 | 742 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 743 | const void *val, int bytes); |
4b12f0de | 744 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); |
2f333bcb MT |
745 | |
746 | extern bool tdp_enabled; | |
9f811285 | 747 | |
a3e06bbe LJ |
748 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
749 | ||
92a1f12d JR |
750 | /* control of guest tsc rate supported? */ |
751 | extern bool kvm_has_tsc_control; | |
752 | /* minimum supported tsc_khz for guests */ | |
753 | extern u32 kvm_min_guest_tsc_khz; | |
754 | /* maximum supported tsc_khz for guests */ | |
755 | extern u32 kvm_max_guest_tsc_khz; | |
756 | ||
54f1585a ZX |
757 | enum emulation_result { |
758 | EMULATE_DONE, /* no further processing */ | |
759 | EMULATE_DO_MMIO, /* kvm_run filled with mmio request */ | |
760 | EMULATE_FAIL, /* can't emulate this instruction */ | |
761 | }; | |
762 | ||
571008da SY |
763 | #define EMULTYPE_NO_DECODE (1 << 0) |
764 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 765 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 766 | #define EMULTYPE_RETRY (1 << 3) |
dc25e89e AP |
767 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
768 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
769 | |
770 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
771 | int emulation_type) | |
772 | { | |
dc25e89e | 773 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
774 | } |
775 | ||
f2b4b7dd | 776 | void kvm_enable_efer_bits(u64); |
54f1585a ZX |
777 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); |
778 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
779 | ||
780 | struct x86_emulate_ctxt; | |
781 | ||
cf8f70bf | 782 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
783 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
784 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
f5f48ee1 | 785 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 786 | |
3e6e0aab | 787 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 788 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
3e6e0aab | 789 | |
7f3d35fd KW |
790 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
791 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 792 | |
49a9b07e | 793 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 794 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 795 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 796 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
797 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
798 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
799 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
800 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 801 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 802 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a ZX |
803 | |
804 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); | |
805 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
806 | ||
91586a3b JK |
807 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
808 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 809 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 810 | |
298101da AK |
811 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
812 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
813 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
814 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 815 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
816 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
817 | gfn_t gfn, void *data, int offset, int len, | |
818 | u32 access); | |
6389ee94 | 819 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
0a79b009 | 820 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
298101da | 821 | |
1a577b72 MT |
822 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
823 | int irq_source_id, int level) | |
824 | { | |
825 | /* Logical OR for level trig interrupt */ | |
826 | if (level) | |
827 | __set_bit(irq_source_id, irq_state); | |
828 | else | |
829 | __clear_bit(irq_source_id, irq_state); | |
830 | ||
831 | return !!(*irq_state); | |
832 | } | |
833 | ||
834 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
835 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 836 | |
3419ffc8 SY |
837 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
838 | ||
10ab25cd | 839 | int fx_init(struct kvm_vcpu *vcpu); |
54f1585a | 840 | |
d835dfec | 841 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); |
54f1585a | 842 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 843 | const u8 *new, int bytes); |
1cb3f3ae | 844 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
845 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
846 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
847 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
848 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 849 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
e459e322 | 850 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
ab9ae313 AK |
851 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
852 | struct x86_exception *exception); | |
853 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
854 | struct x86_exception *exception); | |
855 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
856 | struct x86_exception *exception); | |
857 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
858 | struct x86_exception *exception); | |
54f1585a ZX |
859 | |
860 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
861 | ||
dc25e89e AP |
862 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
863 | void *insn, int insn_len); | |
a7052897 | 864 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
34c16eec | 865 | |
18552672 | 866 | void kvm_enable_tdp(void); |
5f4cb662 | 867 | void kvm_disable_tdp(void); |
18552672 | 868 | |
de7d789a | 869 | int complete_pio(struct kvm_vcpu *vcpu); |
f850e2e6 | 870 | bool kvm_check_iopl(struct kvm_vcpu *vcpu); |
ec6d273d | 871 | |
e459e322 XG |
872 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
873 | { | |
874 | return gpa; | |
875 | } | |
876 | ||
ec6d273d ZX |
877 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
878 | { | |
879 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
880 | ||
881 | return (struct kvm_mmu_page *)page_private(page); | |
882 | } | |
883 | ||
d6e88aec | 884 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
885 | { |
886 | u16 ldt; | |
887 | asm("sldt %0" : "=g"(ldt)); | |
888 | return ldt; | |
889 | } | |
890 | ||
d6e88aec | 891 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
892 | { |
893 | asm("lldt %0" : : "rm"(sel)); | |
894 | } | |
ec6d273d | 895 | |
ec6d273d ZX |
896 | #ifdef CONFIG_X86_64 |
897 | static inline unsigned long read_msr(unsigned long msr) | |
898 | { | |
899 | u64 value; | |
900 | ||
901 | rdmsrl(msr, value); | |
902 | return value; | |
903 | } | |
904 | #endif | |
905 | ||
ec6d273d ZX |
906 | static inline u32 get_rdx_init_val(void) |
907 | { | |
908 | return 0x600; /* P6 family */ | |
909 | } | |
910 | ||
c1a5d4f9 AK |
911 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
912 | { | |
913 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
914 | } | |
915 | ||
ec6d273d ZX |
916 | #define TSS_IOPB_BASE_OFFSET 0x66 |
917 | #define TSS_BASE_SIZE 0x68 | |
918 | #define TSS_IOPB_SIZE (65536 / 8) | |
919 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
920 | #define RMODE_TSS_SIZE \ |
921 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 922 | |
37817f29 IE |
923 | enum { |
924 | TASK_SWITCH_CALL = 0, | |
925 | TASK_SWITCH_IRET = 1, | |
926 | TASK_SWITCH_JMP = 2, | |
927 | TASK_SWITCH_GATE = 3, | |
928 | }; | |
929 | ||
1371d904 | 930 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
931 | #define HF_HIF_MASK (1 << 1) |
932 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 933 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 934 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 935 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
1371d904 | 936 | |
4ecac3fd AK |
937 | /* |
938 | * Hardware virtualization extension instructions may fault if a | |
939 | * reboot turns off virtualization while processes are running. | |
940 | * Trap the fault and ignore the instruction if that happens. | |
941 | */ | |
b7c4145b AK |
942 | asmlinkage void kvm_spurious_fault(void); |
943 | extern bool kvm_rebooting; | |
4ecac3fd | 944 | |
5e520e62 | 945 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 946 | "666: " insn "\n\t" \ |
b7c4145b | 947 | "668: \n\t" \ |
18b13e54 | 948 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 949 | "667: \n\t" \ |
5e520e62 | 950 | cleanup_insn "\n\t" \ |
b7c4145b AK |
951 | "cmpb $0, kvm_rebooting \n\t" \ |
952 | "jne 668b \n\t" \ | |
8ceed347 | 953 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 954 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 955 | ".popsection \n\t" \ |
3ee89722 | 956 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 957 | |
5e520e62 AK |
958 | #define __kvm_handle_fault_on_reboot(insn) \ |
959 | ____kvm_handle_fault_on_reboot(insn, "") | |
960 | ||
e930bffe AA |
961 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
962 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 963 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
e930bffe | 964 | int kvm_age_hva(struct kvm *kvm, unsigned long hva); |
8ee53820 | 965 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 966 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
82725b20 | 967 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu); |
a1b37100 GN |
968 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
969 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 970 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
e930bffe | 971 | |
18863bdd | 972 | void kvm_define_shared_msr(unsigned index, u32 msr); |
d5696725 | 973 | void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 974 | |
f92653ee JK |
975 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
976 | ||
af585b92 GN |
977 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
978 | struct kvm_async_pf *work); | |
979 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
980 | struct kvm_async_pf *work); | |
56028d08 GN |
981 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
982 | struct kvm_async_pf *work); | |
7c90705b | 983 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
984 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
985 | ||
db8fcefa AP |
986 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
987 | ||
f5132b01 GN |
988 | int kvm_is_in_guest(void); |
989 | ||
990 | void kvm_pmu_init(struct kvm_vcpu *vcpu); | |
991 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu); | |
992 | void kvm_pmu_reset(struct kvm_vcpu *vcpu); | |
993 | void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu); | |
994 | bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr); | |
995 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
996 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
997 | int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); | |
998 | void kvm_handle_pmu_event(struct kvm_vcpu *vcpu); | |
999 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu); | |
1000 | ||
1965aae3 | 1001 | #endif /* _ASM_X86_KVM_HOST_H */ |