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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
34c16eec | 27 | |
50d0a0f9 | 28 | #include <asm/pvclock-abi.h> |
e01a1b57 | 29 | #include <asm/desc.h> |
0bed3b56 | 30 | #include <asm/mtrr.h> |
9962d032 | 31 | #include <asm/msr-index.h> |
3ee89722 | 32 | #include <asm/asm.h> |
e01a1b57 | 33 | |
cbf64358 | 34 | #define KVM_MAX_VCPUS 255 |
a59cb29e | 35 | #define KVM_SOFT_MAX_VCPUS 160 |
0f888f5a | 36 | #define KVM_USER_MEM_SLOTS 125 |
0743247f AW |
37 | /* memory slots that are not exposed to userspace */ |
38 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 39 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 40 | |
cef4dea0 | 41 | #define KVM_MMIO_SIZE 16 |
69a9f69b AK |
42 | |
43 | #define KVM_PIO_PAGE_OFFSET 1 | |
542472b5 | 44 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
69a9f69b | 45 | |
8175e5b7 AG |
46 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
47 | ||
cfec82cb JR |
48 | #define CR0_RESERVED_BITS \ |
49 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
50 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
51 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
52 | ||
cd6e8f87 ZX |
53 | #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) |
54 | #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) | |
ad756a16 | 55 | #define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL |
7d76b4d3 JP |
56 | #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ |
57 | 0xFFFFFF0000000000ULL) | |
cfec82cb JR |
58 | #define CR4_RESERVED_BITS \ |
59 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
60 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 61 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
d9c3476d | 62 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \ |
cfec82cb JR |
63 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
64 | ||
65 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
66 | ||
67 | ||
cd6e8f87 | 68 | |
cd6e8f87 | 69 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
70 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
71 | ||
cd6e8f87 ZX |
72 | #define UNMAPPED_GVA (~(gpa_t)0) |
73 | ||
ec04b260 | 74 | /* KVM Hugepage definitions for x86 */ |
04326caa | 75 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
76 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
77 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
78 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
79 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
80 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 81 | |
cd6e8f87 ZX |
82 | #define SELECTOR_TI_MASK (1 << 2) |
83 | #define SELECTOR_RPL_MASK 0x03 | |
84 | ||
85 | #define IOPL_SHIFT 12 | |
86 | ||
d657a98e ZX |
87 | #define KVM_PERMILLE_MMU_PAGES 20 |
88 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
89 | #define KVM_MMU_HASH_SHIFT 10 |
90 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
91 | #define KVM_MIN_FREE_MMU_PAGES 5 |
92 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 93 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 94 | #define KVM_NR_FIXED_MTRR_REGION 88 |
9ba075a6 | 95 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 96 | |
af585b92 GN |
97 | #define ASYNC_PF_PER_VCPU 64 |
98 | ||
d657a98e ZX |
99 | struct kvm_vcpu; |
100 | struct kvm; | |
af585b92 | 101 | struct kvm_async_pf; |
d657a98e | 102 | |
5fdbf976 | 103 | enum kvm_reg { |
2b3ccfa0 ZX |
104 | VCPU_REGS_RAX = 0, |
105 | VCPU_REGS_RCX = 1, | |
106 | VCPU_REGS_RDX = 2, | |
107 | VCPU_REGS_RBX = 3, | |
108 | VCPU_REGS_RSP = 4, | |
109 | VCPU_REGS_RBP = 5, | |
110 | VCPU_REGS_RSI = 6, | |
111 | VCPU_REGS_RDI = 7, | |
112 | #ifdef CONFIG_X86_64 | |
113 | VCPU_REGS_R8 = 8, | |
114 | VCPU_REGS_R9 = 9, | |
115 | VCPU_REGS_R10 = 10, | |
116 | VCPU_REGS_R11 = 11, | |
117 | VCPU_REGS_R12 = 12, | |
118 | VCPU_REGS_R13 = 13, | |
119 | VCPU_REGS_R14 = 14, | |
120 | VCPU_REGS_R15 = 15, | |
121 | #endif | |
5fdbf976 | 122 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
123 | NR_VCPU_REGS |
124 | }; | |
125 | ||
6de4f3ad AK |
126 | enum kvm_reg_ex { |
127 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 128 | VCPU_EXREG_CR3, |
6de12732 | 129 | VCPU_EXREG_RFLAGS, |
69c73028 | 130 | VCPU_EXREG_CPL, |
2fb92db1 | 131 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
132 | }; |
133 | ||
2b3ccfa0 | 134 | enum { |
81609e3e | 135 | VCPU_SREG_ES, |
2b3ccfa0 | 136 | VCPU_SREG_CS, |
81609e3e | 137 | VCPU_SREG_SS, |
2b3ccfa0 | 138 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
139 | VCPU_SREG_FS, |
140 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
141 | VCPU_SREG_TR, |
142 | VCPU_SREG_LDTR, | |
143 | }; | |
144 | ||
56e82318 | 145 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 146 | |
d657a98e ZX |
147 | #define KVM_NR_MEM_OBJS 40 |
148 | ||
42dbaa5a JK |
149 | #define KVM_NR_DB_REGS 4 |
150 | ||
151 | #define DR6_BD (1 << 13) | |
152 | #define DR6_BS (1 << 14) | |
153 | #define DR6_FIXED_1 0xffff0ff0 | |
154 | #define DR6_VOLATILE 0x0000e00f | |
155 | ||
156 | #define DR7_BP_EN_MASK 0x000000ff | |
157 | #define DR7_GE (1 << 9) | |
158 | #define DR7_GD (1 << 13) | |
159 | #define DR7_FIXED_1 0x00000400 | |
160 | #define DR7_VOLATILE 0xffff23ff | |
161 | ||
41383771 GN |
162 | /* apic attention bits */ |
163 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
164 | /* |
165 | * The following bit is set with PV-EOI, unset on EOI. | |
166 | * We detect PV-EOI changes by guest by comparing | |
167 | * this bit with PV-EOI in guest memory. | |
168 | * See the implementation in apic_update_pv_eoi. | |
169 | */ | |
170 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 171 | |
d657a98e ZX |
172 | /* |
173 | * We don't want allocation failures within the mmu code, so we preallocate | |
174 | * enough memory for a single page fault in a cache. | |
175 | */ | |
176 | struct kvm_mmu_memory_cache { | |
177 | int nobjs; | |
178 | void *objects[KVM_NR_MEM_OBJS]; | |
179 | }; | |
180 | ||
d657a98e ZX |
181 | /* |
182 | * kvm_mmu_page_role, below, is defined as: | |
183 | * | |
184 | * bits 0:3 - total guest paging levels (2-4, or zero for real mode) | |
185 | * bits 4:7 - page table level for this shadow (1-4) | |
186 | * bits 8:9 - page table quadrant for 2-level guests | |
f6e2c02b AK |
187 | * bit 16 - direct mapping of virtual to physical mapping at gfn |
188 | * used for real mode and two-dimensional paging | |
d657a98e ZX |
189 | * bits 17:19 - common access permissions for all ptes in this shadow page |
190 | */ | |
191 | union kvm_mmu_page_role { | |
192 | unsigned word; | |
193 | struct { | |
7d76b4d3 | 194 | unsigned level:4; |
5b7e0102 | 195 | unsigned cr4_pae:1; |
7d76b4d3 JP |
196 | unsigned quadrant:2; |
197 | unsigned pad_for_nice_hex_output:6; | |
f6e2c02b | 198 | unsigned direct:1; |
7d76b4d3 | 199 | unsigned access:3; |
2e53d63a | 200 | unsigned invalid:1; |
9645bb56 | 201 | unsigned nxe:1; |
3dbe1415 | 202 | unsigned cr0_wp:1; |
411c588d | 203 | unsigned smep_andnot_wp:1; |
d657a98e ZX |
204 | }; |
205 | }; | |
206 | ||
207 | struct kvm_mmu_page { | |
208 | struct list_head link; | |
209 | struct hlist_node hash_link; | |
210 | ||
211 | /* | |
212 | * The following two entries are used to key the shadow page in the | |
213 | * hash table. | |
214 | */ | |
215 | gfn_t gfn; | |
216 | union kvm_mmu_page_role role; | |
217 | ||
218 | u64 *spt; | |
219 | /* hold the gfn of each spte inside spt */ | |
220 | gfn_t *gfns; | |
4731d4c7 | 221 | bool unsync; |
0571d366 | 222 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 223 | unsigned int unsync_children; |
67052b35 | 224 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
5304b8d3 | 225 | unsigned long mmu_valid_gen; |
0074ff63 | 226 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
227 | |
228 | #ifdef CONFIG_X86_32 | |
229 | int clear_spte_count; | |
230 | #endif | |
231 | ||
a30f47cb | 232 | int write_flooding_count; |
d657a98e ZX |
233 | }; |
234 | ||
1c08364c AK |
235 | struct kvm_pio_request { |
236 | unsigned long count; | |
1c08364c AK |
237 | int in; |
238 | int port; | |
239 | int size; | |
1c08364c AK |
240 | }; |
241 | ||
d657a98e ZX |
242 | /* |
243 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
244 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
245 | * mode. | |
246 | */ | |
247 | struct kvm_mmu { | |
248 | void (*new_cr3)(struct kvm_vcpu *vcpu); | |
f43addd4 | 249 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 250 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 251 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
252 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
253 | bool prefault); | |
6389ee94 AK |
254 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
255 | struct x86_exception *fault); | |
d657a98e | 256 | void (*free)(struct kvm_vcpu *vcpu); |
1871c602 | 257 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 258 | struct x86_exception *exception); |
c30a358d | 259 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
e8bc217a | 260 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 261 | struct kvm_mmu_page *sp); |
a7052897 | 262 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 263 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 264 | u64 *spte, const void *pte); |
d657a98e ZX |
265 | hpa_t root_hpa; |
266 | int root_level; | |
267 | int shadow_root_level; | |
a770f6f2 | 268 | union kvm_mmu_page_role base_role; |
c5a78f2b | 269 | bool direct_map; |
d657a98e | 270 | |
97d64b78 AK |
271 | /* |
272 | * Bitmap; bit set = permission fault | |
273 | * Byte index: page fault error code [4:1] | |
274 | * Bit index: pte permissions in ACC_* format | |
275 | */ | |
276 | u8 permissions[16]; | |
277 | ||
d657a98e | 278 | u64 *pae_root; |
81407ca5 | 279 | u64 *lm_root; |
82725b20 | 280 | u64 rsvd_bits_mask[2][4]; |
ff03a073 | 281 | |
6fd01b71 AK |
282 | /* |
283 | * Bitmap: bit set = last pte in walk | |
284 | * index[0:1]: level (zero-based) | |
285 | * index[2]: pte.ps | |
286 | */ | |
287 | u8 last_pte_bitmap; | |
288 | ||
2d48a985 JR |
289 | bool nx; |
290 | ||
ff03a073 | 291 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
292 | }; |
293 | ||
f5132b01 GN |
294 | enum pmc_type { |
295 | KVM_PMC_GP = 0, | |
296 | KVM_PMC_FIXED, | |
297 | }; | |
298 | ||
299 | struct kvm_pmc { | |
300 | enum pmc_type type; | |
301 | u8 idx; | |
302 | u64 counter; | |
303 | u64 eventsel; | |
304 | struct perf_event *perf_event; | |
305 | struct kvm_vcpu *vcpu; | |
306 | }; | |
307 | ||
308 | struct kvm_pmu { | |
309 | unsigned nr_arch_gp_counters; | |
310 | unsigned nr_arch_fixed_counters; | |
311 | unsigned available_event_types; | |
312 | u64 fixed_ctr_ctrl; | |
313 | u64 global_ctrl; | |
314 | u64 global_status; | |
315 | u64 global_ovf_ctrl; | |
316 | u64 counter_bitmask[2]; | |
317 | u64 global_ctrl_mask; | |
318 | u8 version; | |
15c7ad51 RR |
319 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
320 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
321 | struct irq_work irq_work; |
322 | u64 reprogram_pmi; | |
323 | }; | |
324 | ||
ad312c7c | 325 | struct kvm_vcpu_arch { |
5fdbf976 MT |
326 | /* |
327 | * rip and regs accesses must go through | |
328 | * kvm_{register,rip}_{read,write} functions. | |
329 | */ | |
330 | unsigned long regs[NR_VCPU_REGS]; | |
331 | u32 regs_avail; | |
332 | u32 regs_dirty; | |
34c16eec ZX |
333 | |
334 | unsigned long cr0; | |
e8467fda | 335 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
336 | unsigned long cr2; |
337 | unsigned long cr3; | |
338 | unsigned long cr4; | |
fc78f519 | 339 | unsigned long cr4_guest_owned_bits; |
34c16eec | 340 | unsigned long cr8; |
1371d904 | 341 | u32 hflags; |
f6801dff | 342 | u64 efer; |
34c16eec ZX |
343 | u64 apic_base; |
344 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
41383771 | 345 | unsigned long apic_attention; |
e1035715 | 346 | int32_t apic_arb_prio; |
34c16eec | 347 | int mp_state; |
34c16eec | 348 | u64 ia32_misc_enable_msr; |
b209749f | 349 | bool tpr_access_reporting; |
34c16eec | 350 | |
14dfe855 JR |
351 | /* |
352 | * Paging state of the vcpu | |
353 | * | |
354 | * If the vcpu runs in guest mode with two level paging this still saves | |
355 | * the paging mode of the l1 guest. This context is always used to | |
356 | * handle faults. | |
357 | */ | |
34c16eec | 358 | struct kvm_mmu mmu; |
8df25a32 | 359 | |
6539e738 JR |
360 | /* |
361 | * Paging state of an L2 guest (used for nested npt) | |
362 | * | |
363 | * This context will save all necessary information to walk page tables | |
364 | * of the an L2 guest. This context is only initialized for page table | |
365 | * walking and not for faulting since we never handle l2 page faults on | |
366 | * the host. | |
367 | */ | |
368 | struct kvm_mmu nested_mmu; | |
369 | ||
14dfe855 JR |
370 | /* |
371 | * Pointer to the mmu context currently used for | |
372 | * gva_to_gpa translations. | |
373 | */ | |
374 | struct kvm_mmu *walk_mmu; | |
375 | ||
53c07b18 | 376 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
377 | struct kvm_mmu_memory_cache mmu_page_cache; |
378 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
379 | ||
98918833 | 380 | struct fpu guest_fpu; |
2acf923e | 381 | u64 xcr0; |
34c16eec | 382 | |
34c16eec ZX |
383 | struct kvm_pio_request pio; |
384 | void *pio_data; | |
385 | ||
66fd3f7f GN |
386 | u8 event_exit_inst_len; |
387 | ||
298101da AK |
388 | struct kvm_queued_exception { |
389 | bool pending; | |
390 | bool has_error_code; | |
ce7ddec4 | 391 | bool reinject; |
298101da AK |
392 | u8 nr; |
393 | u32 error_code; | |
394 | } exception; | |
395 | ||
937a7eae AK |
396 | struct kvm_queued_interrupt { |
397 | bool pending; | |
66fd3f7f | 398 | bool soft; |
937a7eae AK |
399 | u8 nr; |
400 | } interrupt; | |
401 | ||
34c16eec ZX |
402 | int halt_request; /* real mode on Intel only */ |
403 | ||
404 | int cpuid_nent; | |
07716717 | 405 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
34c16eec ZX |
406 | /* emulate context */ |
407 | ||
408 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
409 | bool emulate_regs_need_sync_to_vcpu; |
410 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 411 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
412 | |
413 | gpa_t time; | |
50d0a0f9 | 414 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 415 | unsigned int hw_tsc_khz; |
0b79459b AH |
416 | struct gfn_to_hva_cache pv_time; |
417 | bool pv_time_enabled; | |
51d59c6b MT |
418 | /* set guest stopped flag in pvclock flags field */ |
419 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
420 | |
421 | struct { | |
422 | u64 msr_val; | |
423 | u64 last_steal; | |
424 | u64 accum_steal; | |
425 | struct gfn_to_hva_cache stime; | |
426 | struct kvm_steal_time steal; | |
427 | } st; | |
428 | ||
1d5f066e ZA |
429 | u64 last_guest_tsc; |
430 | u64 last_kernel_ns; | |
6f526ec5 | 431 | u64 last_host_tsc; |
0dd6a6ed | 432 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
433 | u64 this_tsc_nsec; |
434 | u64 this_tsc_write; | |
435 | u8 this_tsc_generation; | |
c285545f | 436 | bool tsc_catchup; |
cc578287 ZA |
437 | bool tsc_always_catchup; |
438 | s8 virtual_tsc_shift; | |
439 | u32 virtual_tsc_mult; | |
440 | u32 virtual_tsc_khz; | |
ba904635 | 441 | s64 ia32_tsc_adjust_msr; |
3419ffc8 | 442 | |
7460fb4a AK |
443 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
444 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
445 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
9ba075a6 | 446 | |
0bed3b56 SY |
447 | struct mtrr_state_type mtrr_state; |
448 | u32 pat; | |
42dbaa5a JK |
449 | |
450 | int switch_db_regs; | |
42dbaa5a JK |
451 | unsigned long db[KVM_NR_DB_REGS]; |
452 | unsigned long dr6; | |
453 | unsigned long dr7; | |
454 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 455 | unsigned long guest_debug_dr7; |
890ca9ae HY |
456 | |
457 | u64 mcg_cap; | |
458 | u64 mcg_status; | |
459 | u64 mcg_ctl; | |
460 | u64 *mce_banks; | |
94fe45da | 461 | |
bebb106a XG |
462 | /* Cache MMIO info */ |
463 | u64 mmio_gva; | |
464 | unsigned access; | |
465 | gfn_t mmio_gfn; | |
466 | ||
f5132b01 GN |
467 | struct kvm_pmu pmu; |
468 | ||
94fe45da | 469 | /* used for guest single stepping over the given code position */ |
94fe45da | 470 | unsigned long singlestep_rip; |
f92653ee | 471 | |
10388a07 GN |
472 | /* fields used by HYPER-V emulation */ |
473 | u64 hv_vapic; | |
f5f48ee1 SY |
474 | |
475 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 476 | |
1cb3f3ae XG |
477 | unsigned long last_retry_eip; |
478 | unsigned long last_retry_addr; | |
479 | ||
af585b92 GN |
480 | struct { |
481 | bool halted; | |
482 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
483 | struct gfn_to_hva_cache data; |
484 | u64 msr_val; | |
7c90705b | 485 | u32 id; |
6adba527 | 486 | bool send_user_only; |
af585b92 | 487 | } apf; |
2b036c6b BO |
488 | |
489 | /* OSVW MSRs (AMD only) */ | |
490 | struct { | |
491 | u64 length; | |
492 | u64 status; | |
493 | } osvw; | |
ae7a2a3f MT |
494 | |
495 | struct { | |
496 | u64 msr_val; | |
497 | struct gfn_to_hva_cache data; | |
498 | } pv_eoi; | |
93c05d3e XG |
499 | |
500 | /* | |
501 | * Indicate whether the access faults on its page table in guest | |
502 | * which is set when fix page fault and used to detect unhandeable | |
503 | * instruction. | |
504 | */ | |
505 | bool write_fault_to_shadow_pgtable; | |
34c16eec ZX |
506 | }; |
507 | ||
db3fe4eb | 508 | struct kvm_lpage_info { |
db3fe4eb TY |
509 | int write_count; |
510 | }; | |
511 | ||
512 | struct kvm_arch_memory_slot { | |
d89cc617 | 513 | unsigned long *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
514 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
515 | }; | |
516 | ||
1e08ec4a GN |
517 | struct kvm_apic_map { |
518 | struct rcu_head rcu; | |
519 | u8 ldr_bits; | |
520 | /* fields bellow are used to decode ldr values in different modes */ | |
521 | u32 cid_shift, cid_mask, lid_mask; | |
522 | struct kvm_lapic *phys_map[256]; | |
523 | /* first index is cluster id second is cpu id in a cluster */ | |
524 | struct kvm_lapic *logical_map[16][16]; | |
525 | }; | |
526 | ||
fef9cce0 | 527 | struct kvm_arch { |
49d5ca26 | 528 | unsigned int n_used_mmu_pages; |
f05e70ac | 529 | unsigned int n_requested_mmu_pages; |
39de71ec | 530 | unsigned int n_max_mmu_pages; |
332b207d | 531 | unsigned int indirect_shadow_pages; |
5304b8d3 | 532 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
533 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
534 | /* | |
535 | * Hash table of struct kvm_mmu_page. | |
536 | */ | |
537 | struct list_head active_mmu_pages; | |
365c8868 XG |
538 | struct list_head zapped_obsolete_pages; |
539 | ||
4d5c5d0f | 540 | struct list_head assigned_dev_head; |
19de40a8 | 541 | struct iommu_domain *iommu_domain; |
522c68c4 | 542 | int iommu_flags; |
d7deeeb0 ZX |
543 | struct kvm_pic *vpic; |
544 | struct kvm_ioapic *vioapic; | |
7837699f | 545 | struct kvm_pit *vpit; |
cc6e462c | 546 | int vapics_in_nmi_mode; |
1e08ec4a GN |
547 | struct mutex apic_map_lock; |
548 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 549 | |
bfc6d222 ZX |
550 | unsigned int tss_addr; |
551 | struct page *apic_access_page; | |
18068523 GOC |
552 | |
553 | gpa_t wall_clock; | |
b7ebfb05 SY |
554 | |
555 | struct page *ept_identity_pagetable; | |
556 | bool ept_identity_pagetable_done; | |
b927a3ce | 557 | gpa_t ept_identity_map_addr; |
5550af4d SY |
558 | |
559 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 560 | s64 kvmclock_offset; |
038f8c11 | 561 | raw_spinlock_t tsc_write_lock; |
f38e098f | 562 | u64 last_tsc_nsec; |
f38e098f | 563 | u64 last_tsc_write; |
5d3cb0f6 | 564 | u32 last_tsc_khz; |
e26101b1 ZA |
565 | u64 cur_tsc_nsec; |
566 | u64 cur_tsc_write; | |
567 | u64 cur_tsc_offset; | |
568 | u8 cur_tsc_generation; | |
b48aa97e | 569 | int nr_vcpus_matched_tsc; |
ffde22ac | 570 | |
d828199e MT |
571 | spinlock_t pvclock_gtod_sync_lock; |
572 | bool use_master_clock; | |
573 | u64 master_kernel_ns; | |
574 | cycle_t master_cycle_now; | |
575 | ||
ffde22ac | 576 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a GN |
577 | |
578 | /* fields used by HYPER-V emulation */ | |
579 | u64 hv_guest_os_id; | |
580 | u64 hv_hypercall; | |
b034cf01 XG |
581 | |
582 | #ifdef CONFIG_KVM_MMU_AUDIT | |
583 | int audit_point; | |
584 | #endif | |
d69fb81f ZX |
585 | }; |
586 | ||
0711456c ZX |
587 | struct kvm_vm_stat { |
588 | u32 mmu_shadow_zapped; | |
589 | u32 mmu_pte_write; | |
590 | u32 mmu_pte_updated; | |
591 | u32 mmu_pde_zapped; | |
592 | u32 mmu_flooded; | |
593 | u32 mmu_recycled; | |
dfc5aa00 | 594 | u32 mmu_cache_miss; |
4731d4c7 | 595 | u32 mmu_unsync; |
0711456c | 596 | u32 remote_tlb_flush; |
05da4558 | 597 | u32 lpages; |
0711456c ZX |
598 | }; |
599 | ||
77b4c255 ZX |
600 | struct kvm_vcpu_stat { |
601 | u32 pf_fixed; | |
602 | u32 pf_guest; | |
603 | u32 tlb_flush; | |
604 | u32 invlpg; | |
605 | ||
606 | u32 exits; | |
607 | u32 io_exits; | |
608 | u32 mmio_exits; | |
609 | u32 signal_exits; | |
610 | u32 irq_window_exits; | |
f08864b4 | 611 | u32 nmi_window_exits; |
77b4c255 ZX |
612 | u32 halt_exits; |
613 | u32 halt_wakeup; | |
614 | u32 request_irq_exits; | |
615 | u32 irq_exits; | |
616 | u32 host_state_reload; | |
617 | u32 efer_reload; | |
618 | u32 fpu_reload; | |
619 | u32 insn_emulation; | |
620 | u32 insn_emulation_fail; | |
f11c3a8d | 621 | u32 hypercalls; |
fa89a817 | 622 | u32 irq_injections; |
c4abb7c9 | 623 | u32 nmi_injections; |
77b4c255 | 624 | }; |
ad312c7c | 625 | |
8a76d7f2 JR |
626 | struct x86_instruction_info; |
627 | ||
8fe8ab46 WA |
628 | struct msr_data { |
629 | bool host_initiated; | |
630 | u32 index; | |
631 | u64 data; | |
632 | }; | |
633 | ||
ea4a5ff8 ZX |
634 | struct kvm_x86_ops { |
635 | int (*cpu_has_kvm_support)(void); /* __init */ | |
636 | int (*disabled_by_bios)(void); /* __init */ | |
10474ae8 | 637 | int (*hardware_enable)(void *dummy); |
ea4a5ff8 ZX |
638 | void (*hardware_disable)(void *dummy); |
639 | void (*check_processor_compatibility)(void *rtn); | |
640 | int (*hardware_setup)(void); /* __init */ | |
641 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 642 | bool (*cpu_has_accelerated_tpr)(void); |
0e851880 | 643 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
644 | |
645 | /* Create, but do not attach this VCPU */ | |
646 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
647 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
57f252f2 | 648 | void (*vcpu_reset)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
649 | |
650 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
651 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
652 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 653 | |
c8639010 | 654 | void (*update_db_bp_intercept)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 655 | int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata); |
8fe8ab46 | 656 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
657 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
658 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
659 | struct kvm_segment *var, int seg); | |
2e4d2653 | 660 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
661 | void (*set_segment)(struct kvm_vcpu *vcpu, |
662 | struct kvm_segment *var, int seg); | |
663 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 664 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 665 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
666 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
667 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
668 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 669 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 670 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
671 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
672 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
673 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
674 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
020df079 | 675 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 676 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
677 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
678 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
6b52d186 | 679 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 680 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
681 | |
682 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 683 | |
851ba692 AK |
684 | void (*run)(struct kvm_vcpu *vcpu); |
685 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 686 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 GC |
687 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
688 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); | |
ea4a5ff8 ZX |
689 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
690 | unsigned char *hypercall_addr); | |
66fd3f7f | 691 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 692 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 693 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
694 | bool has_error_code, u32 error_code, |
695 | bool reinject); | |
b463a6f7 | 696 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 697 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 698 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
699 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
700 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
03b28f81 | 701 | int (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
730dca42 | 702 | int (*enable_irq_window)(struct kvm_vcpu *vcpu); |
95ba8273 | 703 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
c7c9c56c YZ |
704 | int (*vm_has_apicv)(struct kvm *kvm); |
705 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); | |
706 | void (*hwapic_isr_update)(struct kvm *kvm, int isr); | |
707 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); | |
8d14695f | 708 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
a20ed54d YZ |
709 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
710 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 711 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 712 | int (*get_tdp_level)(void); |
4b12f0de | 713 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 714 | int (*get_lpage_level)(void); |
4e47c7a6 | 715 | bool (*rdtscp_supported)(void); |
ad756a16 | 716 | bool (*invpcid_supported)(void); |
f1e2b260 | 717 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 718 | |
1c97f0a0 JR |
719 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
720 | ||
d4330ef2 JR |
721 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
722 | ||
f5f48ee1 SY |
723 | bool (*has_wbinvd_exit)(void); |
724 | ||
cc578287 | 725 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
ba904635 | 726 | u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
727 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
728 | ||
857e4099 | 729 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
886b470c | 730 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc); |
857e4099 | 731 | |
586f9607 | 732 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
733 | |
734 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
735 | struct x86_instruction_info *info, | |
736 | enum x86_intercept_stage stage); | |
a547c6db | 737 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
738 | }; |
739 | ||
af585b92 | 740 | struct kvm_arch_async_pf { |
7c90705b | 741 | u32 token; |
af585b92 | 742 | gfn_t gfn; |
fb67e14f | 743 | unsigned long cr3; |
c4806acd | 744 | bool direct_map; |
af585b92 GN |
745 | }; |
746 | ||
97896d04 ZX |
747 | extern struct kvm_x86_ops *kvm_x86_ops; |
748 | ||
f1e2b260 MT |
749 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
750 | s64 adjustment) | |
751 | { | |
752 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
753 | } | |
754 | ||
755 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
756 | { | |
757 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
758 | } | |
759 | ||
54f1585a ZX |
760 | int kvm_mmu_module_init(void); |
761 | void kvm_mmu_module_exit(void); | |
762 | ||
763 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
764 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
765 | int kvm_mmu_setup(struct kvm_vcpu *vcpu); | |
7b52345e | 766 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 767 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a ZX |
768 | |
769 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu); | |
770 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot); | |
5dc99b23 TY |
771 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
772 | struct kvm_memory_slot *slot, | |
773 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 774 | void kvm_mmu_zap_all(struct kvm *kvm); |
f8f55942 | 775 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm); |
3ad82a7e | 776 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
777 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
778 | ||
ff03a073 | 779 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 780 | |
3200f405 | 781 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 782 | const void *val, int bytes); |
4b12f0de | 783 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); |
2f333bcb MT |
784 | |
785 | extern bool tdp_enabled; | |
9f811285 | 786 | |
a3e06bbe LJ |
787 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
788 | ||
92a1f12d JR |
789 | /* control of guest tsc rate supported? */ |
790 | extern bool kvm_has_tsc_control; | |
791 | /* minimum supported tsc_khz for guests */ | |
792 | extern u32 kvm_min_guest_tsc_khz; | |
793 | /* maximum supported tsc_khz for guests */ | |
794 | extern u32 kvm_max_guest_tsc_khz; | |
795 | ||
54f1585a ZX |
796 | enum emulation_result { |
797 | EMULATE_DONE, /* no further processing */ | |
798 | EMULATE_DO_MMIO, /* kvm_run filled with mmio request */ | |
799 | EMULATE_FAIL, /* can't emulate this instruction */ | |
800 | }; | |
801 | ||
571008da SY |
802 | #define EMULTYPE_NO_DECODE (1 << 0) |
803 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 804 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 805 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 806 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
807 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
808 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
809 | |
810 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
811 | int emulation_type) | |
812 | { | |
dc25e89e | 813 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
814 | } |
815 | ||
f2b4b7dd | 816 | void kvm_enable_efer_bits(u64); |
384bb783 | 817 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
54f1585a | 818 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); |
8fe8ab46 | 819 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
820 | |
821 | struct x86_emulate_ctxt; | |
822 | ||
cf8f70bf | 823 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
824 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
825 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
f5f48ee1 | 826 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 827 | |
3e6e0aab | 828 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 829 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
66450a21 | 830 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector); |
3e6e0aab | 831 | |
7f3d35fd KW |
832 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
833 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 834 | |
49a9b07e | 835 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 836 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 837 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 838 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
839 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
840 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
841 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
842 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 843 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 844 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a ZX |
845 | |
846 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); | |
8fe8ab46 | 847 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 848 | |
91586a3b JK |
849 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
850 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 851 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 852 | |
298101da AK |
853 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
854 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
855 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
856 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 857 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
858 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
859 | gfn_t gfn, void *data, int offset, int len, | |
860 | u32 access); | |
6389ee94 | 861 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
0a79b009 | 862 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
298101da | 863 | |
1a577b72 MT |
864 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
865 | int irq_source_id, int level) | |
866 | { | |
867 | /* Logical OR for level trig interrupt */ | |
868 | if (level) | |
869 | __set_bit(irq_source_id, irq_state); | |
870 | else | |
871 | __clear_bit(irq_source_id, irq_state); | |
872 | ||
873 | return !!(*irq_state); | |
874 | } | |
875 | ||
876 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
877 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 878 | |
3419ffc8 SY |
879 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
880 | ||
10ab25cd | 881 | int fx_init(struct kvm_vcpu *vcpu); |
54f1585a | 882 | |
d835dfec | 883 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); |
54f1585a | 884 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 885 | const u8 *new, int bytes); |
1cb3f3ae | 886 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
887 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
888 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
889 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
890 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 891 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
e459e322 | 892 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
ab9ae313 AK |
893 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
894 | struct x86_exception *exception); | |
895 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
896 | struct x86_exception *exception); | |
897 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
898 | struct x86_exception *exception); | |
899 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
900 | struct x86_exception *exception); | |
54f1585a ZX |
901 | |
902 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
903 | ||
dc25e89e AP |
904 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
905 | void *insn, int insn_len); | |
a7052897 | 906 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
34c16eec | 907 | |
18552672 | 908 | void kvm_enable_tdp(void); |
5f4cb662 | 909 | void kvm_disable_tdp(void); |
18552672 | 910 | |
de7d789a | 911 | int complete_pio(struct kvm_vcpu *vcpu); |
f850e2e6 | 912 | bool kvm_check_iopl(struct kvm_vcpu *vcpu); |
ec6d273d | 913 | |
e459e322 XG |
914 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
915 | { | |
916 | return gpa; | |
917 | } | |
918 | ||
ec6d273d ZX |
919 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
920 | { | |
921 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
922 | ||
923 | return (struct kvm_mmu_page *)page_private(page); | |
924 | } | |
925 | ||
d6e88aec | 926 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
927 | { |
928 | u16 ldt; | |
929 | asm("sldt %0" : "=g"(ldt)); | |
930 | return ldt; | |
931 | } | |
932 | ||
d6e88aec | 933 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
934 | { |
935 | asm("lldt %0" : : "rm"(sel)); | |
936 | } | |
ec6d273d | 937 | |
ec6d273d ZX |
938 | #ifdef CONFIG_X86_64 |
939 | static inline unsigned long read_msr(unsigned long msr) | |
940 | { | |
941 | u64 value; | |
942 | ||
943 | rdmsrl(msr, value); | |
944 | return value; | |
945 | } | |
946 | #endif | |
947 | ||
ec6d273d ZX |
948 | static inline u32 get_rdx_init_val(void) |
949 | { | |
950 | return 0x600; /* P6 family */ | |
951 | } | |
952 | ||
c1a5d4f9 AK |
953 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
954 | { | |
955 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
956 | } | |
957 | ||
ec6d273d ZX |
958 | #define TSS_IOPB_BASE_OFFSET 0x66 |
959 | #define TSS_BASE_SIZE 0x68 | |
960 | #define TSS_IOPB_SIZE (65536 / 8) | |
961 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
962 | #define RMODE_TSS_SIZE \ |
963 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 964 | |
37817f29 IE |
965 | enum { |
966 | TASK_SWITCH_CALL = 0, | |
967 | TASK_SWITCH_IRET = 1, | |
968 | TASK_SWITCH_JMP = 2, | |
969 | TASK_SWITCH_GATE = 3, | |
970 | }; | |
971 | ||
1371d904 | 972 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
973 | #define HF_HIF_MASK (1 << 1) |
974 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 975 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 976 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 977 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
1371d904 | 978 | |
4ecac3fd AK |
979 | /* |
980 | * Hardware virtualization extension instructions may fault if a | |
981 | * reboot turns off virtualization while processes are running. | |
982 | * Trap the fault and ignore the instruction if that happens. | |
983 | */ | |
b7c4145b | 984 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 985 | |
5e520e62 | 986 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 987 | "666: " insn "\n\t" \ |
b7c4145b | 988 | "668: \n\t" \ |
18b13e54 | 989 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 990 | "667: \n\t" \ |
5e520e62 | 991 | cleanup_insn "\n\t" \ |
b7c4145b AK |
992 | "cmpb $0, kvm_rebooting \n\t" \ |
993 | "jne 668b \n\t" \ | |
8ceed347 | 994 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 995 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 996 | ".popsection \n\t" \ |
3ee89722 | 997 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 998 | |
5e520e62 AK |
999 | #define __kvm_handle_fault_on_reboot(insn) \ |
1000 | ____kvm_handle_fault_on_reboot(insn, "") | |
1001 | ||
e930bffe AA |
1002 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1003 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1004 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
e930bffe | 1005 | int kvm_age_hva(struct kvm *kvm, unsigned long hva); |
8ee53820 | 1006 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1007 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
82725b20 | 1008 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu); |
c7c9c56c | 1009 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1010 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1011 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1012 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
66450a21 | 1013 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu); |
e930bffe | 1014 | |
18863bdd | 1015 | void kvm_define_shared_msr(unsigned index, u32 msr); |
d5696725 | 1016 | void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1017 | |
f92653ee JK |
1018 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1019 | ||
af585b92 GN |
1020 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1021 | struct kvm_async_pf *work); | |
1022 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1023 | struct kvm_async_pf *work); | |
56028d08 GN |
1024 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1025 | struct kvm_async_pf *work); | |
7c90705b | 1026 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1027 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1028 | ||
db8fcefa AP |
1029 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
1030 | ||
f5132b01 GN |
1031 | int kvm_is_in_guest(void); |
1032 | ||
1033 | void kvm_pmu_init(struct kvm_vcpu *vcpu); | |
1034 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu); | |
1035 | void kvm_pmu_reset(struct kvm_vcpu *vcpu); | |
1036 | void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu); | |
1037 | bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr); | |
1038 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
afd80d85 | 1039 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
f5132b01 GN |
1040 | int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); |
1041 | void kvm_handle_pmu_event(struct kvm_vcpu *vcpu); | |
1042 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu); | |
1043 | ||
1965aae3 | 1044 | #endif /* _ASM_X86_KVM_HOST_H */ |