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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
87276880 | 27 | #include <linux/irqbypass.h> |
5c919412 | 28 | #include <linux/hyperv.h> |
34c16eec | 29 | |
7d669f50 | 30 | #include <asm/apic.h> |
50d0a0f9 | 31 | #include <asm/pvclock-abi.h> |
e01a1b57 | 32 | #include <asm/desc.h> |
0bed3b56 | 33 | #include <asm/mtrr.h> |
9962d032 | 34 | #include <asm/msr-index.h> |
3ee89722 | 35 | #include <asm/asm.h> |
21ebbeda | 36 | #include <asm/kvm_page_track.h> |
5a485803 | 37 | #include <asm/hyperv-tlfs.h> |
e01a1b57 | 38 | |
682f732e | 39 | #define KVM_MAX_VCPUS 288 |
757883de | 40 | #define KVM_SOFT_MAX_VCPUS 240 |
af1bae54 | 41 | #define KVM_MAX_VCPU_ID 1023 |
1d4e7e3c | 42 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
43 | /* memory slots that are not exposed to userspace */ |
44 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 45 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 46 | |
b401ee0b | 47 | #define KVM_HALT_POLL_NS_DEFAULT 200000 |
69a9f69b | 48 | |
8175e5b7 AG |
49 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
50 | ||
2860c4b1 | 51 | /* x86-specific vcpu->requests bit members */ |
2387149e AJ |
52 | #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) |
53 | #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) | |
54 | #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) | |
55 | #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) | |
56 | #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) | |
57 | #define KVM_REQ_EVENT KVM_ARCH_REQ(6) | |
58 | #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) | |
59 | #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) | |
60 | #define KVM_REQ_NMI KVM_ARCH_REQ(9) | |
61 | #define KVM_REQ_PMU KVM_ARCH_REQ(10) | |
62 | #define KVM_REQ_PMI KVM_ARCH_REQ(11) | |
63 | #define KVM_REQ_SMI KVM_ARCH_REQ(12) | |
64 | #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) | |
65 | #define KVM_REQ_MCLOCK_INPROGRESS \ | |
66 | KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
67 | #define KVM_REQ_SCAN_IOAPIC \ | |
68 | KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
69 | #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) | |
70 | #define KVM_REQ_APIC_PAGE_RELOAD \ | |
71 | KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
72 | #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) | |
73 | #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) | |
74 | #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) | |
75 | #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) | |
76 | #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) | |
e40ff1d6 | 77 | #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) |
2860c4b1 | 78 | |
cfec82cb JR |
79 | #define CR0_RESERVED_BITS \ |
80 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
81 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
82 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
83 | ||
cfaa790a | 84 | #define CR3_PCID_INVD BIT_64(63) |
cfec82cb JR |
85 | #define CR4_RESERVED_BITS \ |
86 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
87 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 88 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 89 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
fd8cb433 | 90 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ |
ae3e61e1 | 91 | | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) |
cfec82cb JR |
92 | |
93 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
94 | ||
95 | ||
cd6e8f87 | 96 | |
cd6e8f87 | 97 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
98 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
99 | ||
cd6e8f87 ZX |
100 | #define UNMAPPED_GVA (~(gpa_t)0) |
101 | ||
ec04b260 | 102 | /* KVM Hugepage definitions for x86 */ |
04326caa | 103 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
104 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
105 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
106 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
107 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
108 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 109 | |
6d9d41e5 CD |
110 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
111 | { | |
112 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
113 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
114 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
115 | } | |
116 | ||
d657a98e ZX |
117 | #define KVM_PERMILLE_MMU_PAGES 20 |
118 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
114df303 | 119 | #define KVM_MMU_HASH_SHIFT 12 |
1ae0a13d | 120 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) |
d657a98e ZX |
121 | #define KVM_MIN_FREE_MMU_PAGES 5 |
122 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 123 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 124 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 125 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 126 | |
af585b92 GN |
127 | #define ASYNC_PF_PER_VCPU 64 |
128 | ||
5fdbf976 | 129 | enum kvm_reg { |
2b3ccfa0 ZX |
130 | VCPU_REGS_RAX = 0, |
131 | VCPU_REGS_RCX = 1, | |
132 | VCPU_REGS_RDX = 2, | |
133 | VCPU_REGS_RBX = 3, | |
134 | VCPU_REGS_RSP = 4, | |
135 | VCPU_REGS_RBP = 5, | |
136 | VCPU_REGS_RSI = 6, | |
137 | VCPU_REGS_RDI = 7, | |
138 | #ifdef CONFIG_X86_64 | |
139 | VCPU_REGS_R8 = 8, | |
140 | VCPU_REGS_R9 = 9, | |
141 | VCPU_REGS_R10 = 10, | |
142 | VCPU_REGS_R11 = 11, | |
143 | VCPU_REGS_R12 = 12, | |
144 | VCPU_REGS_R13 = 13, | |
145 | VCPU_REGS_R14 = 14, | |
146 | VCPU_REGS_R15 = 15, | |
147 | #endif | |
5fdbf976 | 148 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
149 | NR_VCPU_REGS |
150 | }; | |
151 | ||
6de4f3ad AK |
152 | enum kvm_reg_ex { |
153 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 154 | VCPU_EXREG_CR3, |
6de12732 | 155 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 156 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
157 | }; |
158 | ||
2b3ccfa0 | 159 | enum { |
81609e3e | 160 | VCPU_SREG_ES, |
2b3ccfa0 | 161 | VCPU_SREG_CS, |
81609e3e | 162 | VCPU_SREG_SS, |
2b3ccfa0 | 163 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
164 | VCPU_SREG_FS, |
165 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
166 | VCPU_SREG_TR, |
167 | VCPU_SREG_LDTR, | |
168 | }; | |
169 | ||
56e82318 | 170 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 171 | |
d657a98e ZX |
172 | #define KVM_NR_MEM_OBJS 40 |
173 | ||
42dbaa5a JK |
174 | #define KVM_NR_DB_REGS 4 |
175 | ||
176 | #define DR6_BD (1 << 13) | |
177 | #define DR6_BS (1 << 14) | |
6f43ed01 NA |
178 | #define DR6_RTM (1 << 16) |
179 | #define DR6_FIXED_1 0xfffe0ff0 | |
180 | #define DR6_INIT 0xffff0ff0 | |
181 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
182 | |
183 | #define DR7_BP_EN_MASK 0x000000ff | |
184 | #define DR7_GE (1 << 9) | |
185 | #define DR7_GD (1 << 13) | |
186 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 187 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 188 | |
c205fb7d NA |
189 | #define PFERR_PRESENT_BIT 0 |
190 | #define PFERR_WRITE_BIT 1 | |
191 | #define PFERR_USER_BIT 2 | |
192 | #define PFERR_RSVD_BIT 3 | |
193 | #define PFERR_FETCH_BIT 4 | |
be94f6b7 | 194 | #define PFERR_PK_BIT 5 |
14727754 TL |
195 | #define PFERR_GUEST_FINAL_BIT 32 |
196 | #define PFERR_GUEST_PAGE_BIT 33 | |
c205fb7d NA |
197 | |
198 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
199 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
200 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
201 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
202 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
be94f6b7 | 203 | #define PFERR_PK_MASK (1U << PFERR_PK_BIT) |
14727754 TL |
204 | #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) |
205 | #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) | |
206 | ||
207 | #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ | |
14727754 TL |
208 | PFERR_WRITE_MASK | \ |
209 | PFERR_PRESENT_MASK) | |
c205fb7d | 210 | |
37f0e8fe JS |
211 | /* |
212 | * The mask used to denote special SPTEs, which can be either MMIO SPTEs or | |
213 | * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting | |
214 | * with the SVE bit in EPT PTEs. | |
215 | */ | |
216 | #define SPTE_SPECIAL_MASK (1ULL << 62) | |
217 | ||
41383771 GN |
218 | /* apic attention bits */ |
219 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
220 | /* |
221 | * The following bit is set with PV-EOI, unset on EOI. | |
222 | * We detect PV-EOI changes by guest by comparing | |
223 | * this bit with PV-EOI in guest memory. | |
224 | * See the implementation in apic_update_pv_eoi. | |
225 | */ | |
226 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 227 | |
d84f1e07 FW |
228 | struct kvm_kernel_irq_routing_entry; |
229 | ||
d657a98e ZX |
230 | /* |
231 | * We don't want allocation failures within the mmu code, so we preallocate | |
232 | * enough memory for a single page fault in a cache. | |
233 | */ | |
234 | struct kvm_mmu_memory_cache { | |
235 | int nobjs; | |
236 | void *objects[KVM_NR_MEM_OBJS]; | |
237 | }; | |
238 | ||
21ebbeda XG |
239 | /* |
240 | * the pages used as guest page table on soft mmu are tracked by | |
241 | * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used | |
242 | * by indirect shadow page can not be more than 15 bits. | |
243 | * | |
244 | * Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access, | |
245 | * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. | |
246 | */ | |
d657a98e ZX |
247 | union kvm_mmu_page_role { |
248 | unsigned word; | |
249 | struct { | |
7d76b4d3 | 250 | unsigned level:4; |
5b7e0102 | 251 | unsigned cr4_pae:1; |
7d76b4d3 | 252 | unsigned quadrant:2; |
f6e2c02b | 253 | unsigned direct:1; |
7d76b4d3 | 254 | unsigned access:3; |
2e53d63a | 255 | unsigned invalid:1; |
9645bb56 | 256 | unsigned nxe:1; |
3dbe1415 | 257 | unsigned cr0_wp:1; |
411c588d | 258 | unsigned smep_andnot_wp:1; |
0be0226f | 259 | unsigned smap_andnot_wp:1; |
ac8d57e5 PF |
260 | unsigned ad_disabled:1; |
261 | unsigned :7; | |
699023e2 PB |
262 | |
263 | /* | |
264 | * This is left at the top of the word so that | |
265 | * kvm_memslots_for_spte_role can extract it with a | |
266 | * simple shift. While there is room, give it a whole | |
267 | * byte so it is also faster to load it from memory. | |
268 | */ | |
269 | unsigned smm:8; | |
d657a98e ZX |
270 | }; |
271 | }; | |
272 | ||
018aabb5 TY |
273 | struct kvm_rmap_head { |
274 | unsigned long val; | |
275 | }; | |
276 | ||
d657a98e ZX |
277 | struct kvm_mmu_page { |
278 | struct list_head link; | |
279 | struct hlist_node hash_link; | |
280 | ||
281 | /* | |
282 | * The following two entries are used to key the shadow page in the | |
283 | * hash table. | |
284 | */ | |
285 | gfn_t gfn; | |
286 | union kvm_mmu_page_role role; | |
287 | ||
288 | u64 *spt; | |
289 | /* hold the gfn of each spte inside spt */ | |
290 | gfn_t *gfns; | |
4731d4c7 | 291 | bool unsync; |
0571d366 | 292 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 293 | unsigned int unsync_children; |
018aabb5 | 294 | struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ |
f6f8adee XG |
295 | |
296 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 297 | unsigned long mmu_valid_gen; |
f6f8adee | 298 | |
0074ff63 | 299 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
300 | |
301 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
302 | /* |
303 | * Used out of the mmu-lock to avoid reading spte values while an | |
304 | * update is in progress; see the comments in __get_spte_lockless(). | |
305 | */ | |
c2a2ac2b XG |
306 | int clear_spte_count; |
307 | #endif | |
308 | ||
0cbf8e43 | 309 | /* Number of writes since the last time traversal visited this page. */ |
e5691a81 | 310 | atomic_t write_flooding_count; |
d657a98e ZX |
311 | }; |
312 | ||
1c08364c AK |
313 | struct kvm_pio_request { |
314 | unsigned long count; | |
1c08364c AK |
315 | int in; |
316 | int port; | |
317 | int size; | |
1c08364c AK |
318 | }; |
319 | ||
855feb67 | 320 | #define PT64_ROOT_MAX_LEVEL 5 |
2a7266a8 | 321 | |
a0a64f50 | 322 | struct rsvd_bits_validate { |
2a7266a8 | 323 | u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; |
a0a64f50 XG |
324 | u64 bad_mt_xwr; |
325 | }; | |
326 | ||
d657a98e | 327 | /* |
855feb67 YZ |
328 | * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, |
329 | * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the | |
330 | * current mmu mode. | |
d657a98e ZX |
331 | */ |
332 | struct kvm_mmu { | |
f43addd4 | 333 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 334 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 335 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
336 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
337 | bool prefault); | |
6389ee94 AK |
338 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
339 | struct x86_exception *fault); | |
1871c602 | 340 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 341 | struct x86_exception *exception); |
54987b7a PB |
342 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
343 | struct x86_exception *exception); | |
e8bc217a | 344 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 345 | struct kvm_mmu_page *sp); |
a7052897 | 346 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 347 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 348 | u64 *spte, const void *pte); |
d657a98e | 349 | hpa_t root_hpa; |
a770f6f2 | 350 | union kvm_mmu_page_role base_role; |
ae1e2d10 PB |
351 | u8 root_level; |
352 | u8 shadow_root_level; | |
353 | u8 ept_ad; | |
c5a78f2b | 354 | bool direct_map; |
d657a98e | 355 | |
97d64b78 AK |
356 | /* |
357 | * Bitmap; bit set = permission fault | |
358 | * Byte index: page fault error code [4:1] | |
359 | * Bit index: pte permissions in ACC_* format | |
360 | */ | |
361 | u8 permissions[16]; | |
362 | ||
2d344105 HH |
363 | /* |
364 | * The pkru_mask indicates if protection key checks are needed. It | |
365 | * consists of 16 domains indexed by page fault error code bits [4:1], | |
366 | * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. | |
367 | * Each domain has 2 bits which are ANDed with AD and WD from PKRU. | |
368 | */ | |
369 | u32 pkru_mask; | |
370 | ||
d657a98e | 371 | u64 *pae_root; |
81407ca5 | 372 | u64 *lm_root; |
c258b62b XG |
373 | |
374 | /* | |
375 | * check zero bits on shadow page table entries, these | |
376 | * bits include not only hardware reserved bits but also | |
377 | * the bits spte never used. | |
378 | */ | |
379 | struct rsvd_bits_validate shadow_zero_check; | |
380 | ||
a0a64f50 | 381 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 382 | |
6bb69c9b PB |
383 | /* Can have large pages at levels 2..last_nonleaf_level-1. */ |
384 | u8 last_nonleaf_level; | |
6fd01b71 | 385 | |
2d48a985 JR |
386 | bool nx; |
387 | ||
ff03a073 | 388 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
389 | }; |
390 | ||
f5132b01 GN |
391 | enum pmc_type { |
392 | KVM_PMC_GP = 0, | |
393 | KVM_PMC_FIXED, | |
394 | }; | |
395 | ||
396 | struct kvm_pmc { | |
397 | enum pmc_type type; | |
398 | u8 idx; | |
399 | u64 counter; | |
400 | u64 eventsel; | |
401 | struct perf_event *perf_event; | |
402 | struct kvm_vcpu *vcpu; | |
403 | }; | |
404 | ||
405 | struct kvm_pmu { | |
406 | unsigned nr_arch_gp_counters; | |
407 | unsigned nr_arch_fixed_counters; | |
408 | unsigned available_event_types; | |
409 | u64 fixed_ctr_ctrl; | |
410 | u64 global_ctrl; | |
411 | u64 global_status; | |
412 | u64 global_ovf_ctrl; | |
413 | u64 counter_bitmask[2]; | |
414 | u64 global_ctrl_mask; | |
103af0a9 | 415 | u64 reserved_bits; |
f5132b01 | 416 | u8 version; |
15c7ad51 RR |
417 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
418 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
419 | struct irq_work irq_work; |
420 | u64 reprogram_pmi; | |
421 | }; | |
422 | ||
25462f7f WH |
423 | struct kvm_pmu_ops; |
424 | ||
360b948d PB |
425 | enum { |
426 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 427 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 428 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
429 | }; |
430 | ||
86fd5270 XG |
431 | struct kvm_mtrr_range { |
432 | u64 base; | |
433 | u64 mask; | |
19efffa2 | 434 | struct list_head node; |
86fd5270 XG |
435 | }; |
436 | ||
70109e7d | 437 | struct kvm_mtrr { |
86fd5270 | 438 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 439 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 440 | u64 deftype; |
19efffa2 XG |
441 | |
442 | struct list_head head; | |
70109e7d XG |
443 | }; |
444 | ||
1f4b34f8 AS |
445 | /* Hyper-V SynIC timer */ |
446 | struct kvm_vcpu_hv_stimer { | |
447 | struct hrtimer timer; | |
448 | int index; | |
449 | u64 config; | |
450 | u64 count; | |
451 | u64 exp_time; | |
452 | struct hv_message msg; | |
453 | bool msg_pending; | |
454 | }; | |
455 | ||
5c919412 AS |
456 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
457 | struct kvm_vcpu_hv_synic { | |
458 | u64 version; | |
459 | u64 control; | |
460 | u64 msg_page; | |
461 | u64 evt_page; | |
462 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
463 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
464 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
465 | DECLARE_BITMAP(vec_bitmap, 256); | |
466 | bool active; | |
efc479e6 | 467 | bool dont_zero_synic_pages; |
5c919412 AS |
468 | }; |
469 | ||
e83d5887 AS |
470 | /* Hyper-V per vcpu emulation context */ |
471 | struct kvm_vcpu_hv { | |
d3457c87 | 472 | u32 vp_index; |
e83d5887 | 473 | u64 hv_vapic; |
9eec50b8 | 474 | s64 runtime_offset; |
5c919412 | 475 | struct kvm_vcpu_hv_synic synic; |
db397571 | 476 | struct kvm_hyperv_exit exit; |
1f4b34f8 AS |
477 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; |
478 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
e83d5887 AS |
479 | }; |
480 | ||
ad312c7c | 481 | struct kvm_vcpu_arch { |
5fdbf976 MT |
482 | /* |
483 | * rip and regs accesses must go through | |
484 | * kvm_{register,rip}_{read,write} functions. | |
485 | */ | |
486 | unsigned long regs[NR_VCPU_REGS]; | |
487 | u32 regs_avail; | |
488 | u32 regs_dirty; | |
34c16eec ZX |
489 | |
490 | unsigned long cr0; | |
e8467fda | 491 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
492 | unsigned long cr2; |
493 | unsigned long cr3; | |
494 | unsigned long cr4; | |
fc78f519 | 495 | unsigned long cr4_guest_owned_bits; |
34c16eec | 496 | unsigned long cr8; |
b9dd21e1 | 497 | u32 pkru; |
1371d904 | 498 | u32 hflags; |
f6801dff | 499 | u64 efer; |
34c16eec ZX |
500 | u64 apic_base; |
501 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 502 | bool apicv_active; |
e40ff1d6 | 503 | bool load_eoi_exitmap_pending; |
6308630b | 504 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 505 | unsigned long apic_attention; |
e1035715 | 506 | int32_t apic_arb_prio; |
34c16eec | 507 | int mp_state; |
34c16eec | 508 | u64 ia32_misc_enable_msr; |
64d60670 | 509 | u64 smbase; |
52797bf9 | 510 | u64 smi_count; |
b209749f | 511 | bool tpr_access_reporting; |
20300099 | 512 | u64 ia32_xss; |
518e7b94 | 513 | u64 microcode_version; |
34c16eec | 514 | |
14dfe855 JR |
515 | /* |
516 | * Paging state of the vcpu | |
517 | * | |
518 | * If the vcpu runs in guest mode with two level paging this still saves | |
519 | * the paging mode of the l1 guest. This context is always used to | |
520 | * handle faults. | |
521 | */ | |
34c16eec | 522 | struct kvm_mmu mmu; |
8df25a32 | 523 | |
6539e738 JR |
524 | /* |
525 | * Paging state of an L2 guest (used for nested npt) | |
526 | * | |
527 | * This context will save all necessary information to walk page tables | |
528 | * of the an L2 guest. This context is only initialized for page table | |
529 | * walking and not for faulting since we never handle l2 page faults on | |
530 | * the host. | |
531 | */ | |
532 | struct kvm_mmu nested_mmu; | |
533 | ||
14dfe855 JR |
534 | /* |
535 | * Pointer to the mmu context currently used for | |
536 | * gva_to_gpa translations. | |
537 | */ | |
538 | struct kvm_mmu *walk_mmu; | |
539 | ||
53c07b18 | 540 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
541 | struct kvm_mmu_memory_cache mmu_page_cache; |
542 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
543 | ||
f775b13e RR |
544 | /* |
545 | * QEMU userspace and the guest each have their own FPU state. | |
546 | * In vcpu_run, we switch between the user and guest FPU contexts. | |
547 | * While running a VCPU, the VCPU thread will have the guest FPU | |
548 | * context. | |
549 | * | |
550 | * Note that while the PKRU state lives inside the fpu registers, | |
551 | * it is switched out separately at VMENTER and VMEXIT time. The | |
552 | * "guest_fpu" state here contains the guest FPU context, with the | |
553 | * host PRKU bits. | |
554 | */ | |
555 | struct fpu user_fpu; | |
98918833 | 556 | struct fpu guest_fpu; |
f775b13e | 557 | |
2acf923e | 558 | u64 xcr0; |
d7876f1b | 559 | u64 guest_supported_xcr0; |
4344ee98 | 560 | u32 guest_xstate_size; |
34c16eec | 561 | |
34c16eec ZX |
562 | struct kvm_pio_request pio; |
563 | void *pio_data; | |
564 | ||
66fd3f7f GN |
565 | u8 event_exit_inst_len; |
566 | ||
298101da AK |
567 | struct kvm_queued_exception { |
568 | bool pending; | |
664f8e26 | 569 | bool injected; |
298101da AK |
570 | bool has_error_code; |
571 | u8 nr; | |
572 | u32 error_code; | |
adfe20fb | 573 | u8 nested_apf; |
298101da AK |
574 | } exception; |
575 | ||
937a7eae | 576 | struct kvm_queued_interrupt { |
04140b41 | 577 | bool injected; |
66fd3f7f | 578 | bool soft; |
937a7eae AK |
579 | u8 nr; |
580 | } interrupt; | |
581 | ||
34c16eec ZX |
582 | int halt_request; /* real mode on Intel only */ |
583 | ||
584 | int cpuid_nent; | |
07716717 | 585 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
586 | |
587 | int maxphyaddr; | |
588 | ||
34c16eec ZX |
589 | /* emulate context */ |
590 | ||
591 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
592 | bool emulate_regs_need_sync_to_vcpu; |
593 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 594 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
595 | |
596 | gpa_t time; | |
50d0a0f9 | 597 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 598 | unsigned int hw_tsc_khz; |
0b79459b AH |
599 | struct gfn_to_hva_cache pv_time; |
600 | bool pv_time_enabled; | |
51d59c6b MT |
601 | /* set guest stopped flag in pvclock flags field */ |
602 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
603 | |
604 | struct { | |
605 | u64 msr_val; | |
606 | u64 last_steal; | |
c9aaa895 GC |
607 | struct gfn_to_hva_cache stime; |
608 | struct kvm_steal_time steal; | |
609 | } st; | |
610 | ||
a545ab6a | 611 | u64 tsc_offset; |
1d5f066e | 612 | u64 last_guest_tsc; |
6f526ec5 | 613 | u64 last_host_tsc; |
0dd6a6ed | 614 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
615 | u64 this_tsc_nsec; |
616 | u64 this_tsc_write; | |
0d3da0d2 | 617 | u64 this_tsc_generation; |
c285545f | 618 | bool tsc_catchup; |
cc578287 ZA |
619 | bool tsc_always_catchup; |
620 | s8 virtual_tsc_shift; | |
621 | u32 virtual_tsc_mult; | |
622 | u32 virtual_tsc_khz; | |
ba904635 | 623 | s64 ia32_tsc_adjust_msr; |
ad721883 | 624 | u64 tsc_scaling_ratio; |
3419ffc8 | 625 | |
7460fb4a AK |
626 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
627 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
628 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 629 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 630 | |
70109e7d | 631 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 632 | u64 pat; |
42dbaa5a | 633 | |
360b948d | 634 | unsigned switch_db_regs; |
42dbaa5a JK |
635 | unsigned long db[KVM_NR_DB_REGS]; |
636 | unsigned long dr6; | |
637 | unsigned long dr7; | |
638 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 639 | unsigned long guest_debug_dr7; |
db2336a8 KH |
640 | u64 msr_platform_info; |
641 | u64 msr_misc_features_enables; | |
890ca9ae HY |
642 | |
643 | u64 mcg_cap; | |
644 | u64 mcg_status; | |
645 | u64 mcg_ctl; | |
c45dcc71 | 646 | u64 mcg_ext_ctl; |
890ca9ae | 647 | u64 *mce_banks; |
94fe45da | 648 | |
bebb106a XG |
649 | /* Cache MMIO info */ |
650 | u64 mmio_gva; | |
651 | unsigned access; | |
652 | gfn_t mmio_gfn; | |
56f17dd3 | 653 | u64 mmio_gen; |
bebb106a | 654 | |
f5132b01 GN |
655 | struct kvm_pmu pmu; |
656 | ||
94fe45da | 657 | /* used for guest single stepping over the given code position */ |
94fe45da | 658 | unsigned long singlestep_rip; |
f92653ee | 659 | |
e83d5887 | 660 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
661 | |
662 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 663 | |
1cb3f3ae XG |
664 | unsigned long last_retry_eip; |
665 | unsigned long last_retry_addr; | |
666 | ||
af585b92 GN |
667 | struct { |
668 | bool halted; | |
669 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
670 | struct gfn_to_hva_cache data; |
671 | u64 msr_val; | |
7c90705b | 672 | u32 id; |
6adba527 | 673 | bool send_user_only; |
1261bfa3 | 674 | u32 host_apf_reason; |
adfe20fb | 675 | unsigned long nested_apf_token; |
52a5c155 | 676 | bool delivery_as_pf_vmexit; |
af585b92 | 677 | } apf; |
2b036c6b BO |
678 | |
679 | /* OSVW MSRs (AMD only) */ | |
680 | struct { | |
681 | u64 length; | |
682 | u64 status; | |
683 | } osvw; | |
ae7a2a3f MT |
684 | |
685 | struct { | |
686 | u64 msr_val; | |
687 | struct gfn_to_hva_cache data; | |
688 | } pv_eoi; | |
93c05d3e XG |
689 | |
690 | /* | |
691 | * Indicate whether the access faults on its page table in guest | |
692 | * which is set when fix page fault and used to detect unhandeable | |
693 | * instruction. | |
694 | */ | |
695 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
696 | |
697 | /* set at EPT violation at this point */ | |
698 | unsigned long exit_qualification; | |
6aef266c SV |
699 | |
700 | /* pv related host specific info */ | |
701 | struct { | |
702 | bool pv_unhalted; | |
703 | } pv; | |
7543a635 SR |
704 | |
705 | int pending_ioapic_eoi; | |
1c1a9ce9 | 706 | int pending_external_vector; |
0f89b207 | 707 | |
618232e2 | 708 | /* GPA available */ |
0f89b207 | 709 | bool gpa_available; |
618232e2 | 710 | gpa_t gpa_val; |
de63ad4c LM |
711 | |
712 | /* be preempted when it's in kernel-mode(cpl=0) */ | |
713 | bool preempted_in_kernel; | |
34c16eec ZX |
714 | }; |
715 | ||
db3fe4eb | 716 | struct kvm_lpage_info { |
92f94f1e | 717 | int disallow_lpage; |
db3fe4eb TY |
718 | }; |
719 | ||
720 | struct kvm_arch_memory_slot { | |
018aabb5 | 721 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb | 722 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
21ebbeda | 723 | unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; |
db3fe4eb TY |
724 | }; |
725 | ||
3548a259 RK |
726 | /* |
727 | * We use as the mode the number of bits allocated in the LDR for the | |
728 | * logical processor ID. It happens that these are all powers of two. | |
729 | * This makes it is very easy to detect cases where the APICs are | |
730 | * configured for multiple modes; in that case, we cannot use the map and | |
731 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
732 | */ | |
733 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
734 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
735 | #define KVM_APIC_MODE_X2APIC 16 | |
736 | ||
1e08ec4a GN |
737 | struct kvm_apic_map { |
738 | struct rcu_head rcu; | |
3548a259 | 739 | u8 mode; |
0ca52e7b | 740 | u32 max_apic_id; |
e45115b6 RK |
741 | union { |
742 | struct kvm_lapic *xapic_flat_map[8]; | |
743 | struct kvm_lapic *xapic_cluster_map[16][4]; | |
744 | }; | |
0ca52e7b | 745 | struct kvm_lapic *phys_map[]; |
1e08ec4a GN |
746 | }; |
747 | ||
e83d5887 AS |
748 | /* Hyper-V emulation context */ |
749 | struct kvm_hv { | |
3f5ad8be | 750 | struct mutex hv_lock; |
e83d5887 AS |
751 | u64 hv_guest_os_id; |
752 | u64 hv_hypercall; | |
753 | u64 hv_tsc_page; | |
e7d9513b AS |
754 | |
755 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
756 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
757 | u64 hv_crash_ctl; | |
095cf55d PB |
758 | |
759 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
faeb7833 RK |
760 | |
761 | struct idr conn_to_evt; | |
a2e164e7 VK |
762 | |
763 | u64 hv_reenlightenment_control; | |
764 | u64 hv_tsc_emulation_control; | |
765 | u64 hv_tsc_emulation_status; | |
e83d5887 AS |
766 | }; |
767 | ||
49776faf RK |
768 | enum kvm_irqchip_mode { |
769 | KVM_IRQCHIP_NONE, | |
770 | KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ | |
771 | KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ | |
772 | }; | |
773 | ||
fef9cce0 | 774 | struct kvm_arch { |
49d5ca26 | 775 | unsigned int n_used_mmu_pages; |
f05e70ac | 776 | unsigned int n_requested_mmu_pages; |
39de71ec | 777 | unsigned int n_max_mmu_pages; |
332b207d | 778 | unsigned int indirect_shadow_pages; |
5304b8d3 | 779 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
780 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
781 | /* | |
782 | * Hash table of struct kvm_mmu_page. | |
783 | */ | |
784 | struct list_head active_mmu_pages; | |
365c8868 | 785 | struct list_head zapped_obsolete_pages; |
13d268ca | 786 | struct kvm_page_track_notifier_node mmu_sp_tracker; |
0eb05bf2 | 787 | struct kvm_page_track_notifier_head track_notifier_head; |
365c8868 | 788 | |
4d5c5d0f | 789 | struct list_head assigned_dev_head; |
19de40a8 | 790 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 791 | bool iommu_noncoherent; |
e0f0bbc5 AW |
792 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
793 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
794 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
795 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
796 | struct kvm_pic *vpic; |
797 | struct kvm_ioapic *vioapic; | |
7837699f | 798 | struct kvm_pit *vpit; |
42720138 | 799 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
800 | struct mutex apic_map_lock; |
801 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 802 | |
c24ae0dc | 803 | bool apic_access_page_done; |
18068523 GOC |
804 | |
805 | gpa_t wall_clock; | |
b7ebfb05 | 806 | |
4d5422ce | 807 | bool mwait_in_guest; |
caa057a2 | 808 | bool hlt_in_guest; |
b31c114b | 809 | bool pause_in_guest; |
4d5422ce | 810 | |
5550af4d | 811 | unsigned long irq_sources_bitmap; |
afbcf7ab | 812 | s64 kvmclock_offset; |
038f8c11 | 813 | raw_spinlock_t tsc_write_lock; |
f38e098f | 814 | u64 last_tsc_nsec; |
f38e098f | 815 | u64 last_tsc_write; |
5d3cb0f6 | 816 | u32 last_tsc_khz; |
e26101b1 ZA |
817 | u64 cur_tsc_nsec; |
818 | u64 cur_tsc_write; | |
819 | u64 cur_tsc_offset; | |
0d3da0d2 | 820 | u64 cur_tsc_generation; |
b48aa97e | 821 | int nr_vcpus_matched_tsc; |
ffde22ac | 822 | |
d828199e MT |
823 | spinlock_t pvclock_gtod_sync_lock; |
824 | bool use_master_clock; | |
825 | u64 master_kernel_ns; | |
a5a1d1c2 | 826 | u64 master_cycle_now; |
7e44e449 | 827 | struct delayed_work kvmclock_update_work; |
332967a3 | 828 | struct delayed_work kvmclock_sync_work; |
d828199e | 829 | |
ffde22ac | 830 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 831 | |
6ef768fa PB |
832 | /* reads protected by irq_srcu, writes by irq_lock */ |
833 | struct hlist_head mask_notifier_list; | |
834 | ||
e83d5887 | 835 | struct kvm_hv hyperv; |
b034cf01 XG |
836 | |
837 | #ifdef CONFIG_KVM_MMU_AUDIT | |
838 | int audit_point; | |
839 | #endif | |
54750f2c | 840 | |
a826faf1 | 841 | bool backwards_tsc_observed; |
54750f2c | 842 | bool boot_vcpu_runs_old_kvmclock; |
d71ba788 | 843 | u32 bsp_vcpu_id; |
90de4a18 NA |
844 | |
845 | u64 disabled_quirks; | |
49df6397 | 846 | |
49776faf | 847 | enum kvm_irqchip_mode irqchip_mode; |
b053b2ae | 848 | u8 nr_reserved_ioapic_pins; |
52004014 FW |
849 | |
850 | bool disabled_lapic_found; | |
44a95dae | 851 | |
37131313 | 852 | bool x2apic_format; |
c519265f | 853 | bool x2apic_broadcast_quirk_disabled; |
d69fb81f ZX |
854 | }; |
855 | ||
0711456c | 856 | struct kvm_vm_stat { |
8a7e75d4 SJS |
857 | ulong mmu_shadow_zapped; |
858 | ulong mmu_pte_write; | |
859 | ulong mmu_pte_updated; | |
860 | ulong mmu_pde_zapped; | |
861 | ulong mmu_flooded; | |
862 | ulong mmu_recycled; | |
863 | ulong mmu_cache_miss; | |
864 | ulong mmu_unsync; | |
865 | ulong remote_tlb_flush; | |
866 | ulong lpages; | |
f3414bc7 | 867 | ulong max_mmu_page_hash_collisions; |
0711456c ZX |
868 | }; |
869 | ||
77b4c255 | 870 | struct kvm_vcpu_stat { |
8a7e75d4 SJS |
871 | u64 pf_fixed; |
872 | u64 pf_guest; | |
873 | u64 tlb_flush; | |
874 | u64 invlpg; | |
875 | ||
876 | u64 exits; | |
877 | u64 io_exits; | |
878 | u64 mmio_exits; | |
879 | u64 signal_exits; | |
880 | u64 irq_window_exits; | |
881 | u64 nmi_window_exits; | |
882 | u64 halt_exits; | |
883 | u64 halt_successful_poll; | |
884 | u64 halt_attempted_poll; | |
885 | u64 halt_poll_invalid; | |
886 | u64 halt_wakeup; | |
887 | u64 request_irq_exits; | |
888 | u64 irq_exits; | |
889 | u64 host_state_reload; | |
8a7e75d4 SJS |
890 | u64 fpu_reload; |
891 | u64 insn_emulation; | |
892 | u64 insn_emulation_fail; | |
893 | u64 hypercalls; | |
894 | u64 irq_injections; | |
895 | u64 nmi_injections; | |
0f1e261e | 896 | u64 req_event; |
77b4c255 | 897 | }; |
ad312c7c | 898 | |
8a76d7f2 JR |
899 | struct x86_instruction_info; |
900 | ||
8fe8ab46 WA |
901 | struct msr_data { |
902 | bool host_initiated; | |
903 | u32 index; | |
904 | u64 data; | |
905 | }; | |
906 | ||
cb5281a5 PB |
907 | struct kvm_lapic_irq { |
908 | u32 vector; | |
b7cb2231 PB |
909 | u16 delivery_mode; |
910 | u16 dest_mode; | |
911 | bool level; | |
912 | u16 trig_mode; | |
cb5281a5 PB |
913 | u32 shorthand; |
914 | u32 dest_id; | |
93bbf0b8 | 915 | bool msi_redir_hint; |
cb5281a5 PB |
916 | }; |
917 | ||
ea4a5ff8 ZX |
918 | struct kvm_x86_ops { |
919 | int (*cpu_has_kvm_support)(void); /* __init */ | |
920 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
921 | int (*hardware_enable)(void); |
922 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
923 | void (*check_processor_compatibility)(void *rtn); |
924 | int (*hardware_setup)(void); /* __init */ | |
925 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 926 | bool (*cpu_has_accelerated_tpr)(void); |
6d396b55 | 927 | bool (*cpu_has_high_real_mode_segbase)(void); |
0e851880 | 928 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 929 | |
434a1e94 SC |
930 | struct kvm *(*vm_alloc)(void); |
931 | void (*vm_free)(struct kvm *); | |
03543133 SS |
932 | int (*vm_init)(struct kvm *kvm); |
933 | void (*vm_destroy)(struct kvm *kvm); | |
934 | ||
ea4a5ff8 ZX |
935 | /* Create, but do not attach this VCPU */ |
936 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
937 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 938 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
939 | |
940 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
941 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
942 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 943 | |
a96036b8 | 944 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 945 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 946 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
947 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
948 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
949 | struct kvm_segment *var, int seg); | |
2e4d2653 | 950 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
951 | void (*set_segment)(struct kvm_vcpu *vcpu, |
952 | struct kvm_segment *var, int seg); | |
953 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 954 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 955 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
956 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
957 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
958 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 959 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 960 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
961 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
962 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
963 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
964 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
965 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
966 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 967 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 968 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 969 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
970 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
971 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
972 | ||
c2ba05cc | 973 | void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); |
ea4a5ff8 | 974 | |
851ba692 AK |
975 | void (*run)(struct kvm_vcpu *vcpu); |
976 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 977 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 978 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 979 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
980 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
981 | unsigned char *hypercall_addr); | |
66fd3f7f | 982 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 983 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
cfcd20e5 | 984 | void (*queue_exception)(struct kvm_vcpu *vcpu); |
b463a6f7 | 985 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 986 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 987 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
988 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
989 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
990 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
991 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 992 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
b2a05fef | 993 | bool (*get_enable_apicv)(struct kvm_vcpu *vcpu); |
d62caabb | 994 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); |
c7c9c56c | 995 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
67c9dddc | 996 | void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); |
6308630b | 997 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d860bbe | 998 | void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); |
4256f43f | 999 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d | 1000 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
76dfafd5 | 1001 | int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1002 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
2ac52ab8 | 1003 | int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); |
855feb67 | 1004 | int (*get_tdp_level)(struct kvm_vcpu *vcpu); |
4b12f0de | 1005 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 1006 | int (*get_lpage_level)(void); |
4e47c7a6 | 1007 | bool (*rdtscp_supported)(void); |
ad756a16 | 1008 | bool (*invpcid_supported)(void); |
344f414f | 1009 | |
1c97f0a0 JR |
1010 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
1011 | ||
d4330ef2 JR |
1012 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
1013 | ||
f5f48ee1 SY |
1014 | bool (*has_wbinvd_exit)(void); |
1015 | ||
e79f245d | 1016 | u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
1017 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
1018 | ||
586f9607 | 1019 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
1020 | |
1021 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
1022 | struct x86_instruction_info *info, | |
1023 | enum x86_intercept_stage stage); | |
a547c6db | 1024 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 1025 | bool (*mpx_supported)(void); |
55412b2e | 1026 | bool (*xsaves_supported)(void); |
66336cab | 1027 | bool (*umip_emulated)(void); |
b6b8a145 JK |
1028 | |
1029 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ae97a3b8 RK |
1030 | |
1031 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
1032 | |
1033 | /* | |
1034 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
1035 | * be valid if the specific arch has hardware-accelerated dirty logging | |
1036 | * mechanism. Currently only for PML on VMX. | |
1037 | * | |
1038 | * - slot_enable_log_dirty: | |
1039 | * called when enabling log dirty mode for the slot. | |
1040 | * - slot_disable_log_dirty: | |
1041 | * called when disabling log dirty mode for the slot. | |
1042 | * also called when slot is created with log dirty disabled. | |
1043 | * - flush_log_dirty: | |
1044 | * called before reporting dirty_bitmap to userspace. | |
1045 | * - enable_log_dirty_pt_masked: | |
1046 | * called when reenabling log dirty for the GFNs in the mask after | |
1047 | * corresponding bits are cleared in slot->dirty_bitmap. | |
1048 | */ | |
1049 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
1050 | struct kvm_memory_slot *slot); | |
1051 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
1052 | struct kvm_memory_slot *slot); | |
1053 | void (*flush_log_dirty)(struct kvm *kvm); | |
1054 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
1055 | struct kvm_memory_slot *slot, | |
1056 | gfn_t offset, unsigned long mask); | |
bab4165e BD |
1057 | int (*write_log_dirty)(struct kvm_vcpu *vcpu); |
1058 | ||
25462f7f WH |
1059 | /* pmu operations of sub-arch */ |
1060 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 | 1061 | |
bf9f6ac8 FW |
1062 | /* |
1063 | * Architecture specific hooks for vCPU blocking due to | |
1064 | * HLT instruction. | |
1065 | * Returns for .pre_block(): | |
1066 | * - 0 means continue to block the vCPU. | |
1067 | * - 1 means we cannot block the vCPU since some event | |
1068 | * happens during this period, such as, 'ON' bit in | |
1069 | * posted-interrupts descriptor is set. | |
1070 | */ | |
1071 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
1072 | void (*post_block)(struct kvm_vcpu *vcpu); | |
d1ed092f SS |
1073 | |
1074 | void (*vcpu_blocking)(struct kvm_vcpu *vcpu); | |
1075 | void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); | |
1076 | ||
efc64404 FW |
1077 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
1078 | uint32_t guest_irq, bool set); | |
be8ca170 | 1079 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); |
ce7a058a YJ |
1080 | |
1081 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc); | |
1082 | void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); | |
c45dcc71 AR |
1083 | |
1084 | void (*setup_mce)(struct kvm_vcpu *vcpu); | |
0234bf88 | 1085 | |
72d7b374 | 1086 | int (*smi_allowed)(struct kvm_vcpu *vcpu); |
0234bf88 LP |
1087 | int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); |
1088 | int (*pre_leave_smm)(struct kvm_vcpu *vcpu, u64 smbase); | |
cc3d967f | 1089 | int (*enable_smi_window)(struct kvm_vcpu *vcpu); |
5acc5c06 BS |
1090 | |
1091 | int (*mem_enc_op)(struct kvm *kvm, void __user *argp); | |
69eaedee BS |
1092 | int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); |
1093 | int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); | |
801e459a TL |
1094 | |
1095 | int (*get_msr_feature)(struct kvm_msr_entry *entry); | |
ea4a5ff8 ZX |
1096 | }; |
1097 | ||
af585b92 | 1098 | struct kvm_arch_async_pf { |
7c90705b | 1099 | u32 token; |
af585b92 | 1100 | gfn_t gfn; |
fb67e14f | 1101 | unsigned long cr3; |
c4806acd | 1102 | bool direct_map; |
af585b92 GN |
1103 | }; |
1104 | ||
97896d04 ZX |
1105 | extern struct kvm_x86_ops *kvm_x86_ops; |
1106 | ||
434a1e94 SC |
1107 | #define __KVM_HAVE_ARCH_VM_ALLOC |
1108 | static inline struct kvm *kvm_arch_alloc_vm(void) | |
1109 | { | |
1110 | return kvm_x86_ops->vm_alloc(); | |
1111 | } | |
1112 | ||
1113 | static inline void kvm_arch_free_vm(struct kvm *kvm) | |
1114 | { | |
1115 | return kvm_x86_ops->vm_free(kvm); | |
1116 | } | |
1117 | ||
54f1585a ZX |
1118 | int kvm_mmu_module_init(void); |
1119 | void kvm_mmu_module_exit(void); | |
1120 | ||
1121 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
1122 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 1123 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
13d268ca XG |
1124 | void kvm_mmu_init_vm(struct kvm *kvm); |
1125 | void kvm_mmu_uninit_vm(struct kvm *kvm); | |
7b52345e | 1126 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 1127 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 1128 | u64 acc_track_mask, u64 me_mask); |
54f1585a | 1129 | |
8a3c1a33 | 1130 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
1131 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
1132 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 1133 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 1134 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
1135 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
1136 | struct kvm_memory_slot *memslot); | |
1137 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
1138 | struct kvm_memory_slot *memslot); | |
1139 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
1140 | struct kvm_memory_slot *memslot); | |
1141 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1142 | struct kvm_memory_slot *slot, | |
1143 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 1144 | void kvm_mmu_zap_all(struct kvm *kvm); |
54bf36aa | 1145 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); |
3ad82a7e | 1146 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
1147 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
1148 | ||
ff03a073 | 1149 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
9ed38ffa | 1150 | bool pdptrs_changed(struct kvm_vcpu *vcpu); |
cc4b6871 | 1151 | |
3200f405 | 1152 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 1153 | const void *val, int bytes); |
2f333bcb | 1154 | |
6ef768fa PB |
1155 | struct kvm_irq_mask_notifier { |
1156 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
1157 | int irq; | |
1158 | struct hlist_node link; | |
1159 | }; | |
1160 | ||
1161 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1162 | struct kvm_irq_mask_notifier *kimn); | |
1163 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1164 | struct kvm_irq_mask_notifier *kimn); | |
1165 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1166 | bool mask); | |
1167 | ||
2f333bcb | 1168 | extern bool tdp_enabled; |
9f811285 | 1169 | |
a3e06bbe LJ |
1170 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
1171 | ||
92a1f12d JR |
1172 | /* control of guest tsc rate supported? */ |
1173 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
1174 | /* maximum supported tsc_khz for guests */ |
1175 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
1176 | /* number of bits of the fractional part of the TSC scaling ratio */ |
1177 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1178 | /* maximum allowed value of TSC scaling ratio */ | |
1179 | extern u64 kvm_max_tsc_scaling_ratio; | |
64672c95 YJ |
1180 | /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ |
1181 | extern u64 kvm_default_tsc_scaling_ratio; | |
92a1f12d | 1182 | |
c45dcc71 | 1183 | extern u64 kvm_mce_cap_supported; |
92a1f12d | 1184 | |
54f1585a | 1185 | enum emulation_result { |
ac0a48c3 PB |
1186 | EMULATE_DONE, /* no further processing */ |
1187 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
1188 | EMULATE_FAIL, /* can't emulate this instruction */ |
1189 | }; | |
1190 | ||
571008da SY |
1191 | #define EMULTYPE_NO_DECODE (1 << 0) |
1192 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1193 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 1194 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 1195 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
e2366171 | 1196 | #define EMULTYPE_NO_UD_ON_FAIL (1 << 5) |
04789b66 | 1197 | #define EMULTYPE_VMWARE (1 << 6) |
dc25e89e AP |
1198 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
1199 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
1200 | |
1201 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
1202 | int emulation_type) | |
1203 | { | |
9b8ae637 LA |
1204 | return x86_emulate_instruction(vcpu, 0, |
1205 | emulation_type | EMULTYPE_NO_REEXECUTE, NULL, 0); | |
51d8b661 AP |
1206 | } |
1207 | ||
f2b4b7dd | 1208 | void kvm_enable_efer_bits(u64); |
384bb783 | 1209 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 1210 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1211 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
1212 | |
1213 | struct x86_emulate_ctxt; | |
1214 | ||
dca7f128 | 1215 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); |
6a908b62 | 1216 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
54f1585a | 1217 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); |
5cb56059 | 1218 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1219 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1220 | |
3e6e0aab | 1221 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1222 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1223 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1224 | |
7f3d35fd KW |
1225 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1226 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1227 | |
49a9b07e | 1228 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1229 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1230 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1231 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1232 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1233 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1234 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1235 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1236 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1237 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1238 | |
609e36d3 | 1239 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1240 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1241 | |
91586a3b JK |
1242 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1243 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1244 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1245 | |
298101da AK |
1246 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1247 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1248 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1249 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1250 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1251 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1252 | gfn_t gfn, void *data, int offset, int len, | |
1253 | u32 access); | |
0a79b009 | 1254 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1255 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1256 | |
1a577b72 MT |
1257 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1258 | int irq_source_id, int level) | |
1259 | { | |
1260 | /* Logical OR for level trig interrupt */ | |
1261 | if (level) | |
1262 | __set_bit(irq_source_id, irq_state); | |
1263 | else | |
1264 | __clear_bit(irq_source_id, irq_state); | |
1265 | ||
1266 | return !!(*irq_state); | |
1267 | } | |
1268 | ||
1269 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1270 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1271 | |
3419ffc8 SY |
1272 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1273 | ||
1cb3f3ae | 1274 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1275 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1276 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1277 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1278 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1279 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
74b566e6 | 1280 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu); |
54987b7a PB |
1281 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1282 | struct x86_exception *exception); | |
ab9ae313 AK |
1283 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1284 | struct x86_exception *exception); | |
1285 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1286 | struct x86_exception *exception); | |
1287 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1288 | struct x86_exception *exception); | |
1289 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1290 | struct x86_exception *exception); | |
54f1585a | 1291 | |
d62caabb AS |
1292 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); |
1293 | ||
54f1585a ZX |
1294 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1295 | ||
14727754 | 1296 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, |
dc25e89e | 1297 | void *insn, int insn_len); |
a7052897 | 1298 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 1299 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 1300 | |
18552672 | 1301 | void kvm_enable_tdp(void); |
5f4cb662 | 1302 | void kvm_disable_tdp(void); |
18552672 | 1303 | |
54987b7a PB |
1304 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1305 | struct x86_exception *exception) | |
e459e322 XG |
1306 | { |
1307 | return gpa; | |
1308 | } | |
1309 | ||
ec6d273d ZX |
1310 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1311 | { | |
1312 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1313 | ||
1314 | return (struct kvm_mmu_page *)page_private(page); | |
1315 | } | |
1316 | ||
d6e88aec | 1317 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1318 | { |
1319 | u16 ldt; | |
1320 | asm("sldt %0" : "=g"(ldt)); | |
1321 | return ldt; | |
1322 | } | |
1323 | ||
d6e88aec | 1324 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1325 | { |
1326 | asm("lldt %0" : : "rm"(sel)); | |
1327 | } | |
ec6d273d | 1328 | |
ec6d273d ZX |
1329 | #ifdef CONFIG_X86_64 |
1330 | static inline unsigned long read_msr(unsigned long msr) | |
1331 | { | |
1332 | u64 value; | |
1333 | ||
1334 | rdmsrl(msr, value); | |
1335 | return value; | |
1336 | } | |
1337 | #endif | |
1338 | ||
ec6d273d ZX |
1339 | static inline u32 get_rdx_init_val(void) |
1340 | { | |
1341 | return 0x600; /* P6 family */ | |
1342 | } | |
1343 | ||
c1a5d4f9 AK |
1344 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1345 | { | |
1346 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1347 | } | |
1348 | ||
ec6d273d ZX |
1349 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1350 | #define TSS_BASE_SIZE 0x68 | |
1351 | #define TSS_IOPB_SIZE (65536 / 8) | |
1352 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1353 | #define RMODE_TSS_SIZE \ |
1354 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1355 | |
37817f29 IE |
1356 | enum { |
1357 | TASK_SWITCH_CALL = 0, | |
1358 | TASK_SWITCH_IRET = 1, | |
1359 | TASK_SWITCH_JMP = 2, | |
1360 | TASK_SWITCH_GATE = 3, | |
1361 | }; | |
1362 | ||
1371d904 | 1363 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1364 | #define HF_HIF_MASK (1 << 1) |
1365 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1366 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1367 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1368 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1369 | #define HF_SMM_MASK (1 << 6) |
1370 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1371 | |
699023e2 PB |
1372 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1373 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1374 | ||
1375 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1376 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1377 | |
4ecac3fd AK |
1378 | /* |
1379 | * Hardware virtualization extension instructions may fault if a | |
1380 | * reboot turns off virtualization while processes are running. | |
1381 | * Trap the fault and ignore the instruction if that happens. | |
1382 | */ | |
b7c4145b | 1383 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1384 | |
5e520e62 | 1385 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1386 | "666: " insn "\n\t" \ |
b7c4145b | 1387 | "668: \n\t" \ |
18b13e54 | 1388 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1389 | "667: \n\t" \ |
5e520e62 | 1390 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1391 | "cmpb $0, kvm_rebooting \n\t" \ |
1392 | "jne 668b \n\t" \ | |
8ceed347 | 1393 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1394 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1395 | ".popsection \n\t" \ |
3ee89722 | 1396 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1397 | |
5e520e62 AK |
1398 | #define __kvm_handle_fault_on_reboot(insn) \ |
1399 | ____kvm_handle_fault_on_reboot(insn, "") | |
1400 | ||
e930bffe AA |
1401 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1402 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1403 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1404 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1405 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1406 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1407 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1408 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1409 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1410 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1411 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1412 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
e930bffe | 1413 | |
18863bdd | 1414 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1415 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1416 | |
35181e86 | 1417 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1418 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1419 | |
82b32774 | 1420 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1421 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1422 | ||
2860c4b1 PB |
1423 | void kvm_make_mclock_inprogress_request(struct kvm *kvm); |
1424 | void kvm_make_scan_ioapic_request(struct kvm *kvm); | |
1425 | ||
af585b92 GN |
1426 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1427 | struct kvm_async_pf *work); | |
1428 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1429 | struct kvm_async_pf *work); | |
56028d08 GN |
1430 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1431 | struct kvm_async_pf *work); | |
7c90705b | 1432 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1433 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1434 | ||
6affcbed KH |
1435 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); |
1436 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); | |
db8fcefa | 1437 | |
f5132b01 GN |
1438 | int kvm_is_in_guest(void); |
1439 | ||
1d8007bd PB |
1440 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); |
1441 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
d71ba788 PB |
1442 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1443 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1444 | |
8feb4a04 FW |
1445 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1446 | struct kvm_vcpu **dest_vcpu); | |
1447 | ||
37131313 | 1448 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 1449 | struct kvm_lapic_irq *irq); |
197a4f4b | 1450 | |
d1ed092f SS |
1451 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) |
1452 | { | |
1453 | if (kvm_x86_ops->vcpu_blocking) | |
1454 | kvm_x86_ops->vcpu_blocking(vcpu); | |
1455 | } | |
1456 | ||
1457 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1458 | { | |
1459 | if (kvm_x86_ops->vcpu_unblocking) | |
1460 | kvm_x86_ops->vcpu_unblocking(vcpu); | |
1461 | } | |
1462 | ||
3491caf2 | 1463 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
3217f7c2 | 1464 | |
7d669f50 SS |
1465 | static inline int kvm_cpu_get_apicid(int mps_cpu) |
1466 | { | |
1467 | #ifdef CONFIG_X86_LOCAL_APIC | |
64063505 | 1468 | return default_cpu_present_to_apicid(mps_cpu); |
7d669f50 SS |
1469 | #else |
1470 | WARN_ON_ONCE(1); | |
1471 | return BAD_APICID; | |
1472 | #endif | |
1473 | } | |
1474 | ||
05cade71 LP |
1475 | #define put_smstate(type, buf, offset, val) \ |
1476 | *(type *)((buf) + (offset) - 0x7e00) = val | |
1477 | ||
1965aae3 | 1478 | #endif /* _ASM_X86_KVM_HOST_H */ |