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20c8ccb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
a656c8ef | 2 | /* |
043405e1 CO |
3 | * Kernel-based Virtual Machine driver for Linux |
4 | * | |
5 | * This header defines architecture specific interfaces, x86 version | |
043405e1 CO |
6 | */ |
7 | ||
1965aae3 PA |
8 | #ifndef _ASM_X86_KVM_HOST_H |
9 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 10 | |
34c16eec ZX |
11 | #include <linux/types.h> |
12 | #include <linux/mm.h> | |
e930bffe | 13 | #include <linux/mmu_notifier.h> |
229456fc | 14 | #include <linux/tracepoint.h> |
f5f48ee1 | 15 | #include <linux/cpumask.h> |
f5132b01 | 16 | #include <linux/irq_work.h> |
447ae316 | 17 | #include <linux/irq.h> |
34c16eec ZX |
18 | |
19 | #include <linux/kvm.h> | |
20 | #include <linux/kvm_para.h> | |
edf88417 | 21 | #include <linux/kvm_types.h> |
f5132b01 | 22 | #include <linux/perf_event.h> |
d828199e MT |
23 | #include <linux/pvclock_gtod.h> |
24 | #include <linux/clocksource.h> | |
87276880 | 25 | #include <linux/irqbypass.h> |
5c919412 | 26 | #include <linux/hyperv.h> |
34c16eec | 27 | |
7d669f50 | 28 | #include <asm/apic.h> |
50d0a0f9 | 29 | #include <asm/pvclock-abi.h> |
e01a1b57 | 30 | #include <asm/desc.h> |
0bed3b56 | 31 | #include <asm/mtrr.h> |
9962d032 | 32 | #include <asm/msr-index.h> |
3ee89722 | 33 | #include <asm/asm.h> |
21ebbeda | 34 | #include <asm/kvm_page_track.h> |
95c7b77d | 35 | #include <asm/kvm_vcpu_regs.h> |
5a485803 | 36 | #include <asm/hyperv-tlfs.h> |
e01a1b57 | 37 | |
741cbbae PB |
38 | #define __KVM_HAVE_ARCH_VCPU_DEBUGFS |
39 | ||
682f732e | 40 | #define KVM_MAX_VCPUS 288 |
757883de | 41 | #define KVM_SOFT_MAX_VCPUS 240 |
af1bae54 | 42 | #define KVM_MAX_VCPU_ID 1023 |
1d4e7e3c | 43 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
44 | /* memory slots that are not exposed to userspace */ |
45 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 46 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 47 | |
b401ee0b | 48 | #define KVM_HALT_POLL_NS_DEFAULT 200000 |
69a9f69b | 49 | |
8175e5b7 AG |
50 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
51 | ||
3c9bd400 JZ |
52 | #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ |
53 | KVM_DIRTY_LOG_INITIALLY_SET) | |
54 | ||
2860c4b1 | 55 | /* x86-specific vcpu->requests bit members */ |
2387149e AJ |
56 | #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) |
57 | #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) | |
58 | #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) | |
59 | #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) | |
60 | #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) | |
6e42782f | 61 | #define KVM_REQ_LOAD_CR3 KVM_ARCH_REQ(5) |
2387149e AJ |
62 | #define KVM_REQ_EVENT KVM_ARCH_REQ(6) |
63 | #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) | |
64 | #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) | |
65 | #define KVM_REQ_NMI KVM_ARCH_REQ(9) | |
66 | #define KVM_REQ_PMU KVM_ARCH_REQ(10) | |
67 | #define KVM_REQ_PMI KVM_ARCH_REQ(11) | |
68 | #define KVM_REQ_SMI KVM_ARCH_REQ(12) | |
69 | #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) | |
70 | #define KVM_REQ_MCLOCK_INPROGRESS \ | |
71 | KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
72 | #define KVM_REQ_SCAN_IOAPIC \ | |
73 | KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
74 | #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) | |
75 | #define KVM_REQ_APIC_PAGE_RELOAD \ | |
76 | KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
77 | #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) | |
78 | #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) | |
79 | #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) | |
80 | #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) | |
81 | #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) | |
e40ff1d6 | 82 | #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) |
7f7f1ba3 | 83 | #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24) |
8df14af4 SS |
84 | #define KVM_REQ_APICV_UPDATE \ |
85 | KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
2860c4b1 | 86 | |
cfec82cb JR |
87 | #define CR0_RESERVED_BITS \ |
88 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
89 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
90 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
91 | ||
cfec82cb JR |
92 | #define CR4_RESERVED_BITS \ |
93 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
94 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 95 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 96 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
fd8cb433 | 97 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ |
ae3e61e1 | 98 | | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) |
cfec82cb JR |
99 | |
100 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
101 | ||
102 | ||
cd6e8f87 | 103 | |
cd6e8f87 | 104 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
105 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
106 | ||
cd6e8f87 ZX |
107 | #define UNMAPPED_GVA (~(gpa_t)0) |
108 | ||
ec04b260 | 109 | /* KVM Hugepage definitions for x86 */ |
4fef0f49 WY |
110 | enum { |
111 | PT_PAGE_TABLE_LEVEL = 1, | |
112 | PT_DIRECTORY_LEVEL = 2, | |
113 | PT_PDPE_LEVEL = 3, | |
114 | /* set max level to the biggest one */ | |
115 | PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL, | |
116 | }; | |
117 | #define KVM_NR_PAGE_SIZES (PT_MAX_HUGEPAGE_LEVEL - \ | |
118 | PT_PAGE_TABLE_LEVEL + 1) | |
82855413 JR |
119 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
120 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
121 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
122 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
123 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 124 | |
6d9d41e5 CD |
125 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
126 | { | |
127 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
128 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
129 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
130 | } | |
131 | ||
d657a98e | 132 | #define KVM_PERMILLE_MMU_PAGES 20 |
bc8a3d89 | 133 | #define KVM_MIN_ALLOC_MMU_PAGES 64UL |
114df303 | 134 | #define KVM_MMU_HASH_SHIFT 12 |
1ae0a13d | 135 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) |
d657a98e ZX |
136 | #define KVM_MIN_FREE_MMU_PAGES 5 |
137 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 138 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 139 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 140 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 141 | |
af585b92 GN |
142 | #define ASYNC_PF_PER_VCPU 64 |
143 | ||
5fdbf976 | 144 | enum kvm_reg { |
95c7b77d SC |
145 | VCPU_REGS_RAX = __VCPU_REGS_RAX, |
146 | VCPU_REGS_RCX = __VCPU_REGS_RCX, | |
147 | VCPU_REGS_RDX = __VCPU_REGS_RDX, | |
148 | VCPU_REGS_RBX = __VCPU_REGS_RBX, | |
149 | VCPU_REGS_RSP = __VCPU_REGS_RSP, | |
150 | VCPU_REGS_RBP = __VCPU_REGS_RBP, | |
151 | VCPU_REGS_RSI = __VCPU_REGS_RSI, | |
152 | VCPU_REGS_RDI = __VCPU_REGS_RDI, | |
2b3ccfa0 | 153 | #ifdef CONFIG_X86_64 |
95c7b77d SC |
154 | VCPU_REGS_R8 = __VCPU_REGS_R8, |
155 | VCPU_REGS_R9 = __VCPU_REGS_R9, | |
156 | VCPU_REGS_R10 = __VCPU_REGS_R10, | |
157 | VCPU_REGS_R11 = __VCPU_REGS_R11, | |
158 | VCPU_REGS_R12 = __VCPU_REGS_R12, | |
159 | VCPU_REGS_R13 = __VCPU_REGS_R13, | |
160 | VCPU_REGS_R14 = __VCPU_REGS_R14, | |
161 | VCPU_REGS_R15 = __VCPU_REGS_R15, | |
2b3ccfa0 | 162 | #endif |
5fdbf976 | 163 | VCPU_REGS_RIP, |
f8845541 | 164 | NR_VCPU_REGS, |
2b3ccfa0 | 165 | |
6de4f3ad | 166 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, |
aff48baa | 167 | VCPU_EXREG_CR3, |
6de12732 | 168 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 169 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
170 | }; |
171 | ||
2b3ccfa0 | 172 | enum { |
81609e3e | 173 | VCPU_SREG_ES, |
2b3ccfa0 | 174 | VCPU_SREG_CS, |
81609e3e | 175 | VCPU_SREG_SS, |
2b3ccfa0 | 176 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
177 | VCPU_SREG_FS, |
178 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
179 | VCPU_SREG_TR, |
180 | VCPU_SREG_LDTR, | |
181 | }; | |
182 | ||
1e9e2622 WL |
183 | enum exit_fastpath_completion { |
184 | EXIT_FASTPATH_NONE, | |
185 | EXIT_FASTPATH_SKIP_EMUL_INS, | |
186 | }; | |
187 | ||
56e82318 | 188 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 189 | |
d657a98e ZX |
190 | #define KVM_NR_MEM_OBJS 40 |
191 | ||
42dbaa5a JK |
192 | #define KVM_NR_DB_REGS 4 |
193 | ||
194 | #define DR6_BD (1 << 13) | |
195 | #define DR6_BS (1 << 14) | |
cfb634fe | 196 | #define DR6_BT (1 << 15) |
6f43ed01 NA |
197 | #define DR6_RTM (1 << 16) |
198 | #define DR6_FIXED_1 0xfffe0ff0 | |
199 | #define DR6_INIT 0xffff0ff0 | |
200 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
201 | |
202 | #define DR7_BP_EN_MASK 0x000000ff | |
203 | #define DR7_GE (1 << 9) | |
204 | #define DR7_GD (1 << 13) | |
205 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 206 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 207 | |
c205fb7d NA |
208 | #define PFERR_PRESENT_BIT 0 |
209 | #define PFERR_WRITE_BIT 1 | |
210 | #define PFERR_USER_BIT 2 | |
211 | #define PFERR_RSVD_BIT 3 | |
212 | #define PFERR_FETCH_BIT 4 | |
be94f6b7 | 213 | #define PFERR_PK_BIT 5 |
14727754 TL |
214 | #define PFERR_GUEST_FINAL_BIT 32 |
215 | #define PFERR_GUEST_PAGE_BIT 33 | |
c205fb7d NA |
216 | |
217 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
218 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
219 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
220 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
221 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
be94f6b7 | 222 | #define PFERR_PK_MASK (1U << PFERR_PK_BIT) |
14727754 TL |
223 | #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) |
224 | #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) | |
225 | ||
226 | #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ | |
14727754 TL |
227 | PFERR_WRITE_MASK | \ |
228 | PFERR_PRESENT_MASK) | |
c205fb7d | 229 | |
41383771 GN |
230 | /* apic attention bits */ |
231 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
232 | /* |
233 | * The following bit is set with PV-EOI, unset on EOI. | |
234 | * We detect PV-EOI changes by guest by comparing | |
235 | * this bit with PV-EOI in guest memory. | |
236 | * See the implementation in apic_update_pv_eoi. | |
237 | */ | |
238 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 239 | |
d84f1e07 FW |
240 | struct kvm_kernel_irq_routing_entry; |
241 | ||
d657a98e ZX |
242 | /* |
243 | * We don't want allocation failures within the mmu code, so we preallocate | |
244 | * enough memory for a single page fault in a cache. | |
245 | */ | |
246 | struct kvm_mmu_memory_cache { | |
247 | int nobjs; | |
248 | void *objects[KVM_NR_MEM_OBJS]; | |
249 | }; | |
250 | ||
21ebbeda XG |
251 | /* |
252 | * the pages used as guest page table on soft mmu are tracked by | |
253 | * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used | |
254 | * by indirect shadow page can not be more than 15 bits. | |
255 | * | |
47c42e6b | 256 | * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, |
21ebbeda XG |
257 | * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. |
258 | */ | |
d657a98e | 259 | union kvm_mmu_page_role { |
36d9594d | 260 | u32 word; |
d657a98e | 261 | struct { |
7d76b4d3 | 262 | unsigned level:4; |
47c42e6b | 263 | unsigned gpte_is_8_bytes:1; |
7d76b4d3 | 264 | unsigned quadrant:2; |
f6e2c02b | 265 | unsigned direct:1; |
7d76b4d3 | 266 | unsigned access:3; |
2e53d63a | 267 | unsigned invalid:1; |
9645bb56 | 268 | unsigned nxe:1; |
3dbe1415 | 269 | unsigned cr0_wp:1; |
411c588d | 270 | unsigned smep_andnot_wp:1; |
0be0226f | 271 | unsigned smap_andnot_wp:1; |
ac8d57e5 | 272 | unsigned ad_disabled:1; |
1313cc2b JM |
273 | unsigned guest_mode:1; |
274 | unsigned :6; | |
699023e2 PB |
275 | |
276 | /* | |
277 | * This is left at the top of the word so that | |
278 | * kvm_memslots_for_spte_role can extract it with a | |
279 | * simple shift. While there is room, give it a whole | |
280 | * byte so it is also faster to load it from memory. | |
281 | */ | |
282 | unsigned smm:8; | |
d657a98e ZX |
283 | }; |
284 | }; | |
285 | ||
36d9594d | 286 | union kvm_mmu_extended_role { |
a336282d VK |
287 | /* |
288 | * This structure complements kvm_mmu_page_role caching everything needed for | |
289 | * MMU configuration. If nothing in both these structures changed, MMU | |
290 | * re-configuration can be skipped. @valid bit is set on first usage so we don't | |
291 | * treat all-zero structure as valid data. | |
292 | */ | |
36d9594d | 293 | u32 word; |
a336282d VK |
294 | struct { |
295 | unsigned int valid:1; | |
296 | unsigned int execonly:1; | |
7dcd5755 | 297 | unsigned int cr0_pg:1; |
0699c64a | 298 | unsigned int cr4_pae:1; |
a336282d VK |
299 | unsigned int cr4_pse:1; |
300 | unsigned int cr4_pke:1; | |
301 | unsigned int cr4_smap:1; | |
302 | unsigned int cr4_smep:1; | |
de3ccd26 | 303 | unsigned int maxphyaddr:6; |
a336282d | 304 | }; |
36d9594d VK |
305 | }; |
306 | ||
307 | union kvm_mmu_role { | |
308 | u64 as_u64; | |
309 | struct { | |
310 | union kvm_mmu_page_role base; | |
311 | union kvm_mmu_extended_role ext; | |
312 | }; | |
313 | }; | |
314 | ||
018aabb5 TY |
315 | struct kvm_rmap_head { |
316 | unsigned long val; | |
317 | }; | |
318 | ||
d657a98e ZX |
319 | struct kvm_mmu_page { |
320 | struct list_head link; | |
321 | struct hlist_node hash_link; | |
1aa9b957 JS |
322 | struct list_head lpage_disallowed_link; |
323 | ||
3ff519f2 | 324 | bool unsync; |
ca333add | 325 | u8 mmu_valid_gen; |
4771450c | 326 | bool mmio_cached; |
b8e8c830 | 327 | bool lpage_disallowed; /* Can't be replaced by an equiv large page */ |
d657a98e ZX |
328 | |
329 | /* | |
330 | * The following two entries are used to key the shadow page in the | |
331 | * hash table. | |
332 | */ | |
d657a98e | 333 | union kvm_mmu_page_role role; |
3ff519f2 | 334 | gfn_t gfn; |
d657a98e ZX |
335 | |
336 | u64 *spt; | |
337 | /* hold the gfn of each spte inside spt */ | |
338 | gfn_t *gfns; | |
0571d366 | 339 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 340 | unsigned int unsync_children; |
018aabb5 | 341 | struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ |
0074ff63 | 342 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
343 | |
344 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
345 | /* |
346 | * Used out of the mmu-lock to avoid reading spte values while an | |
347 | * update is in progress; see the comments in __get_spte_lockless(). | |
348 | */ | |
c2a2ac2b XG |
349 | int clear_spte_count; |
350 | #endif | |
351 | ||
0cbf8e43 | 352 | /* Number of writes since the last time traversal visited this page. */ |
e5691a81 | 353 | atomic_t write_flooding_count; |
d657a98e ZX |
354 | }; |
355 | ||
1c08364c | 356 | struct kvm_pio_request { |
45def77e | 357 | unsigned long linear_rip; |
1c08364c | 358 | unsigned long count; |
1c08364c AK |
359 | int in; |
360 | int port; | |
361 | int size; | |
1c08364c AK |
362 | }; |
363 | ||
855feb67 | 364 | #define PT64_ROOT_MAX_LEVEL 5 |
2a7266a8 | 365 | |
a0a64f50 | 366 | struct rsvd_bits_validate { |
2a7266a8 | 367 | u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; |
a0a64f50 XG |
368 | u64 bad_mt_xwr; |
369 | }; | |
370 | ||
7c390d35 JS |
371 | struct kvm_mmu_root_info { |
372 | gpa_t cr3; | |
373 | hpa_t hpa; | |
374 | }; | |
375 | ||
376 | #define KVM_MMU_ROOT_INFO_INVALID \ | |
377 | ((struct kvm_mmu_root_info) { .cr3 = INVALID_PAGE, .hpa = INVALID_PAGE }) | |
378 | ||
b94742c9 JS |
379 | #define KVM_MMU_NUM_PREV_ROOTS 3 |
380 | ||
d657a98e | 381 | /* |
855feb67 YZ |
382 | * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, |
383 | * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the | |
384 | * current mmu mode. | |
d657a98e ZX |
385 | */ |
386 | struct kvm_mmu { | |
f43addd4 | 387 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 388 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 389 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
736c291c | 390 | int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err, |
78b2c54a | 391 | bool prefault); |
6389ee94 AK |
392 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
393 | struct x86_exception *fault); | |
736c291c SC |
394 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa, |
395 | u32 access, struct x86_exception *exception); | |
54987b7a PB |
396 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
397 | struct x86_exception *exception); | |
e8bc217a | 398 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 399 | struct kvm_mmu_page *sp); |
7eb77e9f | 400 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); |
0f53b5b1 | 401 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 402 | u64 *spte, const void *pte); |
d657a98e | 403 | hpa_t root_hpa; |
ad7dc69a | 404 | gpa_t root_cr3; |
36d9594d | 405 | union kvm_mmu_role mmu_role; |
ae1e2d10 PB |
406 | u8 root_level; |
407 | u8 shadow_root_level; | |
408 | u8 ept_ad; | |
c5a78f2b | 409 | bool direct_map; |
b94742c9 | 410 | struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; |
d657a98e | 411 | |
97d64b78 AK |
412 | /* |
413 | * Bitmap; bit set = permission fault | |
414 | * Byte index: page fault error code [4:1] | |
415 | * Bit index: pte permissions in ACC_* format | |
416 | */ | |
417 | u8 permissions[16]; | |
418 | ||
2d344105 HH |
419 | /* |
420 | * The pkru_mask indicates if protection key checks are needed. It | |
421 | * consists of 16 domains indexed by page fault error code bits [4:1], | |
422 | * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. | |
423 | * Each domain has 2 bits which are ANDed with AD and WD from PKRU. | |
424 | */ | |
425 | u32 pkru_mask; | |
426 | ||
d657a98e | 427 | u64 *pae_root; |
81407ca5 | 428 | u64 *lm_root; |
c258b62b XG |
429 | |
430 | /* | |
431 | * check zero bits on shadow page table entries, these | |
432 | * bits include not only hardware reserved bits but also | |
433 | * the bits spte never used. | |
434 | */ | |
435 | struct rsvd_bits_validate shadow_zero_check; | |
436 | ||
a0a64f50 | 437 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 438 | |
6bb69c9b PB |
439 | /* Can have large pages at levels 2..last_nonleaf_level-1. */ |
440 | u8 last_nonleaf_level; | |
6fd01b71 | 441 | |
2d48a985 JR |
442 | bool nx; |
443 | ||
ff03a073 | 444 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
445 | }; |
446 | ||
a49b9635 LT |
447 | struct kvm_tlb_range { |
448 | u64 start_gfn; | |
449 | u64 pages; | |
450 | }; | |
451 | ||
f5132b01 GN |
452 | enum pmc_type { |
453 | KVM_PMC_GP = 0, | |
454 | KVM_PMC_FIXED, | |
455 | }; | |
456 | ||
457 | struct kvm_pmc { | |
458 | enum pmc_type type; | |
459 | u8 idx; | |
460 | u64 counter; | |
461 | u64 eventsel; | |
462 | struct perf_event *perf_event; | |
463 | struct kvm_vcpu *vcpu; | |
a6da0d77 LX |
464 | /* |
465 | * eventsel value for general purpose counters, | |
466 | * ctrl value for fixed counters. | |
467 | */ | |
468 | u64 current_config; | |
f5132b01 GN |
469 | }; |
470 | ||
471 | struct kvm_pmu { | |
472 | unsigned nr_arch_gp_counters; | |
473 | unsigned nr_arch_fixed_counters; | |
474 | unsigned available_event_types; | |
475 | u64 fixed_ctr_ctrl; | |
476 | u64 global_ctrl; | |
477 | u64 global_status; | |
478 | u64 global_ovf_ctrl; | |
479 | u64 counter_bitmask[2]; | |
480 | u64 global_ctrl_mask; | |
c715eb9f | 481 | u64 global_ovf_ctrl_mask; |
103af0a9 | 482 | u64 reserved_bits; |
f5132b01 | 483 | u8 version; |
15c7ad51 RR |
484 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
485 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 | 486 | struct irq_work irq_work; |
4be94672 | 487 | DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); |
b35e5548 LX |
488 | DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); |
489 | DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); | |
490 | ||
491 | /* | |
492 | * The gate to release perf_events not marked in | |
493 | * pmc_in_use only once in a vcpu time slice. | |
494 | */ | |
495 | bool need_cleanup; | |
496 | ||
497 | /* | |
498 | * The total number of programmed perf_events and it helps to avoid | |
499 | * redundant check before cleanup if guest don't use vPMU at all. | |
500 | */ | |
501 | u8 event_count; | |
f5132b01 GN |
502 | }; |
503 | ||
25462f7f WH |
504 | struct kvm_pmu_ops; |
505 | ||
360b948d PB |
506 | enum { |
507 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 508 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 509 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
510 | }; |
511 | ||
86fd5270 XG |
512 | struct kvm_mtrr_range { |
513 | u64 base; | |
514 | u64 mask; | |
19efffa2 | 515 | struct list_head node; |
86fd5270 XG |
516 | }; |
517 | ||
70109e7d | 518 | struct kvm_mtrr { |
86fd5270 | 519 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 520 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 521 | u64 deftype; |
19efffa2 XG |
522 | |
523 | struct list_head head; | |
70109e7d XG |
524 | }; |
525 | ||
1f4b34f8 AS |
526 | /* Hyper-V SynIC timer */ |
527 | struct kvm_vcpu_hv_stimer { | |
528 | struct hrtimer timer; | |
529 | int index; | |
6a058a1e | 530 | union hv_stimer_config config; |
1f4b34f8 AS |
531 | u64 count; |
532 | u64 exp_time; | |
533 | struct hv_message msg; | |
534 | bool msg_pending; | |
535 | }; | |
536 | ||
5c919412 AS |
537 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
538 | struct kvm_vcpu_hv_synic { | |
539 | u64 version; | |
540 | u64 control; | |
541 | u64 msg_page; | |
542 | u64 evt_page; | |
543 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
544 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
545 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
546 | DECLARE_BITMAP(vec_bitmap, 256); | |
547 | bool active; | |
efc479e6 | 548 | bool dont_zero_synic_pages; |
5c919412 AS |
549 | }; |
550 | ||
e83d5887 AS |
551 | /* Hyper-V per vcpu emulation context */ |
552 | struct kvm_vcpu_hv { | |
d3457c87 | 553 | u32 vp_index; |
e83d5887 | 554 | u64 hv_vapic; |
9eec50b8 | 555 | s64 runtime_offset; |
5c919412 | 556 | struct kvm_vcpu_hv_synic synic; |
db397571 | 557 | struct kvm_hyperv_exit exit; |
1f4b34f8 AS |
558 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; |
559 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
e6b6c483 | 560 | cpumask_t tlb_flush; |
e83d5887 AS |
561 | }; |
562 | ||
ad312c7c | 563 | struct kvm_vcpu_arch { |
5fdbf976 MT |
564 | /* |
565 | * rip and regs accesses must go through | |
566 | * kvm_{register,rip}_{read,write} functions. | |
567 | */ | |
568 | unsigned long regs[NR_VCPU_REGS]; | |
569 | u32 regs_avail; | |
570 | u32 regs_dirty; | |
34c16eec ZX |
571 | |
572 | unsigned long cr0; | |
e8467fda | 573 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
574 | unsigned long cr2; |
575 | unsigned long cr3; | |
576 | unsigned long cr4; | |
fc78f519 | 577 | unsigned long cr4_guest_owned_bits; |
34c16eec | 578 | unsigned long cr8; |
b9dd21e1 | 579 | u32 pkru; |
1371d904 | 580 | u32 hflags; |
f6801dff | 581 | u64 efer; |
34c16eec ZX |
582 | u64 apic_base; |
583 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 584 | bool apicv_active; |
e40ff1d6 | 585 | bool load_eoi_exitmap_pending; |
6308630b | 586 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 587 | unsigned long apic_attention; |
e1035715 | 588 | int32_t apic_arb_prio; |
34c16eec | 589 | int mp_state; |
34c16eec | 590 | u64 ia32_misc_enable_msr; |
64d60670 | 591 | u64 smbase; |
52797bf9 | 592 | u64 smi_count; |
b209749f | 593 | bool tpr_access_reporting; |
7204160e | 594 | bool xsaves_enabled; |
20300099 | 595 | u64 ia32_xss; |
518e7b94 | 596 | u64 microcode_version; |
0cf9135b | 597 | u64 arch_capabilities; |
34c16eec | 598 | |
14dfe855 JR |
599 | /* |
600 | * Paging state of the vcpu | |
601 | * | |
602 | * If the vcpu runs in guest mode with two level paging this still saves | |
603 | * the paging mode of the l1 guest. This context is always used to | |
604 | * handle faults. | |
605 | */ | |
44dd3ffa VK |
606 | struct kvm_mmu *mmu; |
607 | ||
608 | /* Non-nested MMU for L1 */ | |
609 | struct kvm_mmu root_mmu; | |
8df25a32 | 610 | |
14c07ad8 VK |
611 | /* L1 MMU when running nested */ |
612 | struct kvm_mmu guest_mmu; | |
613 | ||
6539e738 JR |
614 | /* |
615 | * Paging state of an L2 guest (used for nested npt) | |
616 | * | |
617 | * This context will save all necessary information to walk page tables | |
311497e0 | 618 | * of an L2 guest. This context is only initialized for page table |
6539e738 JR |
619 | * walking and not for faulting since we never handle l2 page faults on |
620 | * the host. | |
621 | */ | |
622 | struct kvm_mmu nested_mmu; | |
623 | ||
14dfe855 JR |
624 | /* |
625 | * Pointer to the mmu context currently used for | |
626 | * gva_to_gpa translations. | |
627 | */ | |
628 | struct kvm_mmu *walk_mmu; | |
629 | ||
53c07b18 | 630 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
631 | struct kvm_mmu_memory_cache mmu_page_cache; |
632 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
633 | ||
f775b13e RR |
634 | /* |
635 | * QEMU userspace and the guest each have their own FPU state. | |
ec269475 PB |
636 | * In vcpu_run, we switch between the user and guest FPU contexts. |
637 | * While running a VCPU, the VCPU thread will have the guest FPU | |
638 | * context. | |
f775b13e RR |
639 | * |
640 | * Note that while the PKRU state lives inside the fpu registers, | |
641 | * it is switched out separately at VMENTER and VMEXIT time. The | |
642 | * "guest_fpu" state here contains the guest FPU context, with the | |
643 | * host PRKU bits. | |
644 | */ | |
d9a710e5 | 645 | struct fpu *user_fpu; |
b666a4b6 | 646 | struct fpu *guest_fpu; |
f775b13e | 647 | |
2acf923e | 648 | u64 xcr0; |
d7876f1b | 649 | u64 guest_supported_xcr0; |
4344ee98 | 650 | u32 guest_xstate_size; |
34c16eec | 651 | |
34c16eec ZX |
652 | struct kvm_pio_request pio; |
653 | void *pio_data; | |
654 | ||
66fd3f7f GN |
655 | u8 event_exit_inst_len; |
656 | ||
298101da AK |
657 | struct kvm_queued_exception { |
658 | bool pending; | |
664f8e26 | 659 | bool injected; |
298101da AK |
660 | bool has_error_code; |
661 | u8 nr; | |
662 | u32 error_code; | |
c851436a JM |
663 | unsigned long payload; |
664 | bool has_payload; | |
adfe20fb | 665 | u8 nested_apf; |
298101da AK |
666 | } exception; |
667 | ||
937a7eae | 668 | struct kvm_queued_interrupt { |
04140b41 | 669 | bool injected; |
66fd3f7f | 670 | bool soft; |
937a7eae AK |
671 | u8 nr; |
672 | } interrupt; | |
673 | ||
34c16eec ZX |
674 | int halt_request; /* real mode on Intel only */ |
675 | ||
676 | int cpuid_nent; | |
07716717 | 677 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
678 | |
679 | int maxphyaddr; | |
680 | ||
34c16eec ZX |
681 | /* emulate context */ |
682 | ||
683 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
684 | bool emulate_regs_need_sync_to_vcpu; |
685 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 686 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
687 | |
688 | gpa_t time; | |
50d0a0f9 | 689 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 690 | unsigned int hw_tsc_khz; |
0b79459b AH |
691 | struct gfn_to_hva_cache pv_time; |
692 | bool pv_time_enabled; | |
51d59c6b MT |
693 | /* set guest stopped flag in pvclock flags field */ |
694 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
695 | |
696 | struct { | |
a6bd811f | 697 | u8 preempted; |
c9aaa895 GC |
698 | u64 msr_val; |
699 | u64 last_steal; | |
91724814 | 700 | struct gfn_to_pfn_cache cache; |
c9aaa895 GC |
701 | } st; |
702 | ||
a545ab6a | 703 | u64 tsc_offset; |
1d5f066e | 704 | u64 last_guest_tsc; |
6f526ec5 | 705 | u64 last_host_tsc; |
0dd6a6ed | 706 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
707 | u64 this_tsc_nsec; |
708 | u64 this_tsc_write; | |
0d3da0d2 | 709 | u64 this_tsc_generation; |
c285545f | 710 | bool tsc_catchup; |
cc578287 ZA |
711 | bool tsc_always_catchup; |
712 | s8 virtual_tsc_shift; | |
713 | u32 virtual_tsc_mult; | |
714 | u32 virtual_tsc_khz; | |
ba904635 | 715 | s64 ia32_tsc_adjust_msr; |
73f624f4 | 716 | u64 msr_ia32_power_ctl; |
ad721883 | 717 | u64 tsc_scaling_ratio; |
3419ffc8 | 718 | |
7460fb4a AK |
719 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
720 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
721 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 722 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 723 | |
70109e7d | 724 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 725 | u64 pat; |
42dbaa5a | 726 | |
360b948d | 727 | unsigned switch_db_regs; |
42dbaa5a JK |
728 | unsigned long db[KVM_NR_DB_REGS]; |
729 | unsigned long dr6; | |
730 | unsigned long dr7; | |
731 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 732 | unsigned long guest_debug_dr7; |
db2336a8 KH |
733 | u64 msr_platform_info; |
734 | u64 msr_misc_features_enables; | |
890ca9ae HY |
735 | |
736 | u64 mcg_cap; | |
737 | u64 mcg_status; | |
738 | u64 mcg_ctl; | |
c45dcc71 | 739 | u64 mcg_ext_ctl; |
890ca9ae | 740 | u64 *mce_banks; |
94fe45da | 741 | |
bebb106a XG |
742 | /* Cache MMIO info */ |
743 | u64 mmio_gva; | |
871bd034 | 744 | unsigned mmio_access; |
bebb106a | 745 | gfn_t mmio_gfn; |
56f17dd3 | 746 | u64 mmio_gen; |
bebb106a | 747 | |
f5132b01 GN |
748 | struct kvm_pmu pmu; |
749 | ||
94fe45da | 750 | /* used for guest single stepping over the given code position */ |
94fe45da | 751 | unsigned long singlestep_rip; |
f92653ee | 752 | |
e83d5887 | 753 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
754 | |
755 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 756 | |
1cb3f3ae XG |
757 | unsigned long last_retry_eip; |
758 | unsigned long last_retry_addr; | |
759 | ||
af585b92 GN |
760 | struct { |
761 | bool halted; | |
762 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
763 | struct gfn_to_hva_cache data; |
764 | u64 msr_val; | |
7c90705b | 765 | u32 id; |
6adba527 | 766 | bool send_user_only; |
1261bfa3 | 767 | u32 host_apf_reason; |
adfe20fb | 768 | unsigned long nested_apf_token; |
52a5c155 | 769 | bool delivery_as_pf_vmexit; |
af585b92 | 770 | } apf; |
2b036c6b BO |
771 | |
772 | /* OSVW MSRs (AMD only) */ | |
773 | struct { | |
774 | u64 length; | |
775 | u64 status; | |
776 | } osvw; | |
ae7a2a3f MT |
777 | |
778 | struct { | |
779 | u64 msr_val; | |
780 | struct gfn_to_hva_cache data; | |
781 | } pv_eoi; | |
93c05d3e | 782 | |
2d5ba19b MT |
783 | u64 msr_kvm_poll_control; |
784 | ||
93c05d3e | 785 | /* |
ffdbd50d ML |
786 | * Indicates the guest is trying to write a gfn that contains one or |
787 | * more of the PTEs used to translate the write itself, i.e. the access | |
788 | * is changing its own translation in the guest page tables. KVM exits | |
789 | * to userspace if emulation of the faulting instruction fails and this | |
790 | * flag is set, as KVM cannot make forward progress. | |
791 | * | |
792 | * If emulation fails for a write to guest page tables, KVM unprotects | |
793 | * (zaps) the shadow page for the target gfn and resumes the guest to | |
794 | * retry the non-emulatable instruction (on hardware). Unprotecting the | |
795 | * gfn doesn't allow forward progress for a self-changing access because | |
796 | * doing so also zaps the translation for the gfn, i.e. retrying the | |
797 | * instruction will hit a !PRESENT fault, which results in a new shadow | |
798 | * page and sends KVM back to square one. | |
93c05d3e XG |
799 | */ |
800 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
801 | |
802 | /* set at EPT violation at this point */ | |
803 | unsigned long exit_qualification; | |
6aef266c SV |
804 | |
805 | /* pv related host specific info */ | |
806 | struct { | |
807 | bool pv_unhalted; | |
808 | } pv; | |
7543a635 SR |
809 | |
810 | int pending_ioapic_eoi; | |
1c1a9ce9 | 811 | int pending_external_vector; |
0f89b207 | 812 | |
de63ad4c LM |
813 | /* be preempted when it's in kernel-mode(cpl=0) */ |
814 | bool preempted_in_kernel; | |
c595ceee PB |
815 | |
816 | /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ | |
817 | bool l1tf_flush_l1d; | |
191c8137 BP |
818 | |
819 | /* AMD MSRC001_0015 Hardware Configuration */ | |
820 | u64 msr_hwcr; | |
34c16eec ZX |
821 | }; |
822 | ||
db3fe4eb | 823 | struct kvm_lpage_info { |
92f94f1e | 824 | int disallow_lpage; |
db3fe4eb TY |
825 | }; |
826 | ||
827 | struct kvm_arch_memory_slot { | |
018aabb5 | 828 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb | 829 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
21ebbeda | 830 | unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; |
db3fe4eb TY |
831 | }; |
832 | ||
3548a259 RK |
833 | /* |
834 | * We use as the mode the number of bits allocated in the LDR for the | |
835 | * logical processor ID. It happens that these are all powers of two. | |
836 | * This makes it is very easy to detect cases where the APICs are | |
837 | * configured for multiple modes; in that case, we cannot use the map and | |
838 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
839 | */ | |
840 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
841 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
842 | #define KVM_APIC_MODE_X2APIC 16 | |
843 | ||
1e08ec4a GN |
844 | struct kvm_apic_map { |
845 | struct rcu_head rcu; | |
3548a259 | 846 | u8 mode; |
0ca52e7b | 847 | u32 max_apic_id; |
e45115b6 RK |
848 | union { |
849 | struct kvm_lapic *xapic_flat_map[8]; | |
850 | struct kvm_lapic *xapic_cluster_map[16][4]; | |
851 | }; | |
0ca52e7b | 852 | struct kvm_lapic *phys_map[]; |
1e08ec4a GN |
853 | }; |
854 | ||
e83d5887 AS |
855 | /* Hyper-V emulation context */ |
856 | struct kvm_hv { | |
3f5ad8be | 857 | struct mutex hv_lock; |
e83d5887 AS |
858 | u64 hv_guest_os_id; |
859 | u64 hv_hypercall; | |
860 | u64 hv_tsc_page; | |
e7d9513b AS |
861 | |
862 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
863 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
864 | u64 hv_crash_ctl; | |
095cf55d PB |
865 | |
866 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
faeb7833 RK |
867 | |
868 | struct idr conn_to_evt; | |
a2e164e7 VK |
869 | |
870 | u64 hv_reenlightenment_control; | |
871 | u64 hv_tsc_emulation_control; | |
872 | u64 hv_tsc_emulation_status; | |
87ee613d VK |
873 | |
874 | /* How many vCPUs have VP index != vCPU index */ | |
875 | atomic_t num_mismatched_vp_indexes; | |
6f6a657c VK |
876 | |
877 | struct hv_partition_assist_pg *hv_pa_pg; | |
e83d5887 AS |
878 | }; |
879 | ||
49776faf RK |
880 | enum kvm_irqchip_mode { |
881 | KVM_IRQCHIP_NONE, | |
882 | KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ | |
883 | KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ | |
884 | }; | |
885 | ||
4e19c36f | 886 | #define APICV_INHIBIT_REASON_DISABLE 0 |
f4fdc0a2 | 887 | #define APICV_INHIBIT_REASON_HYPERV 1 |
9a0bf054 | 888 | #define APICV_INHIBIT_REASON_NESTED 2 |
f3515dc3 | 889 | #define APICV_INHIBIT_REASON_IRQWIN 3 |
e2ed4078 | 890 | #define APICV_INHIBIT_REASON_PIT_REINJ 4 |
cc7f5577 | 891 | #define APICV_INHIBIT_REASON_X2APIC 5 |
4e19c36f | 892 | |
fef9cce0 | 893 | struct kvm_arch { |
bc8a3d89 BG |
894 | unsigned long n_used_mmu_pages; |
895 | unsigned long n_requested_mmu_pages; | |
896 | unsigned long n_max_mmu_pages; | |
332b207d | 897 | unsigned int indirect_shadow_pages; |
ca333add | 898 | u8 mmu_valid_gen; |
f05e70ac ZX |
899 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
900 | /* | |
901 | * Hash table of struct kvm_mmu_page. | |
902 | */ | |
903 | struct list_head active_mmu_pages; | |
31741eb1 | 904 | struct list_head zapped_obsolete_pages; |
1aa9b957 | 905 | struct list_head lpage_disallowed_mmu_pages; |
13d268ca | 906 | struct kvm_page_track_notifier_node mmu_sp_tracker; |
0eb05bf2 | 907 | struct kvm_page_track_notifier_head track_notifier_head; |
365c8868 | 908 | |
4d5c5d0f | 909 | struct list_head assigned_dev_head; |
19de40a8 | 910 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 911 | bool iommu_noncoherent; |
e0f0bbc5 AW |
912 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
913 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
914 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
915 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
916 | struct kvm_pic *vpic; |
917 | struct kvm_ioapic *vioapic; | |
7837699f | 918 | struct kvm_pit *vpit; |
42720138 | 919 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
920 | struct mutex apic_map_lock; |
921 | struct kvm_apic_map *apic_map; | |
4abaffce | 922 | bool apic_map_dirty; |
bfc6d222 | 923 | |
c24ae0dc | 924 | bool apic_access_page_done; |
4e19c36f | 925 | unsigned long apicv_inhibit_reasons; |
18068523 GOC |
926 | |
927 | gpa_t wall_clock; | |
b7ebfb05 | 928 | |
4d5422ce | 929 | bool mwait_in_guest; |
caa057a2 | 930 | bool hlt_in_guest; |
b31c114b | 931 | bool pause_in_guest; |
b5170063 | 932 | bool cstate_in_guest; |
4d5422ce | 933 | |
5550af4d | 934 | unsigned long irq_sources_bitmap; |
afbcf7ab | 935 | s64 kvmclock_offset; |
038f8c11 | 936 | raw_spinlock_t tsc_write_lock; |
f38e098f | 937 | u64 last_tsc_nsec; |
f38e098f | 938 | u64 last_tsc_write; |
5d3cb0f6 | 939 | u32 last_tsc_khz; |
e26101b1 ZA |
940 | u64 cur_tsc_nsec; |
941 | u64 cur_tsc_write; | |
942 | u64 cur_tsc_offset; | |
0d3da0d2 | 943 | u64 cur_tsc_generation; |
b48aa97e | 944 | int nr_vcpus_matched_tsc; |
ffde22ac | 945 | |
d828199e MT |
946 | spinlock_t pvclock_gtod_sync_lock; |
947 | bool use_master_clock; | |
948 | u64 master_kernel_ns; | |
a5a1d1c2 | 949 | u64 master_cycle_now; |
7e44e449 | 950 | struct delayed_work kvmclock_update_work; |
332967a3 | 951 | struct delayed_work kvmclock_sync_work; |
d828199e | 952 | |
ffde22ac | 953 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 954 | |
6ef768fa PB |
955 | /* reads protected by irq_srcu, writes by irq_lock */ |
956 | struct hlist_head mask_notifier_list; | |
957 | ||
e83d5887 | 958 | struct kvm_hv hyperv; |
b034cf01 XG |
959 | |
960 | #ifdef CONFIG_KVM_MMU_AUDIT | |
961 | int audit_point; | |
962 | #endif | |
54750f2c | 963 | |
a826faf1 | 964 | bool backwards_tsc_observed; |
54750f2c | 965 | bool boot_vcpu_runs_old_kvmclock; |
d71ba788 | 966 | u32 bsp_vcpu_id; |
90de4a18 NA |
967 | |
968 | u64 disabled_quirks; | |
49df6397 | 969 | |
49776faf | 970 | enum kvm_irqchip_mode irqchip_mode; |
b053b2ae | 971 | u8 nr_reserved_ioapic_pins; |
52004014 FW |
972 | |
973 | bool disabled_lapic_found; | |
44a95dae | 974 | |
37131313 | 975 | bool x2apic_format; |
c519265f | 976 | bool x2apic_broadcast_quirk_disabled; |
6fbbde9a DS |
977 | |
978 | bool guest_can_read_msr_platform_info; | |
59073aaf | 979 | bool exception_payload_enabled; |
66bb8a06 EH |
980 | |
981 | struct kvm_pmu_event_filter *pmu_event_filter; | |
1aa9b957 | 982 | struct task_struct *nx_lpage_recovery_thread; |
d69fb81f ZX |
983 | }; |
984 | ||
0711456c | 985 | struct kvm_vm_stat { |
8a7e75d4 SJS |
986 | ulong mmu_shadow_zapped; |
987 | ulong mmu_pte_write; | |
988 | ulong mmu_pte_updated; | |
989 | ulong mmu_pde_zapped; | |
990 | ulong mmu_flooded; | |
991 | ulong mmu_recycled; | |
992 | ulong mmu_cache_miss; | |
993 | ulong mmu_unsync; | |
994 | ulong remote_tlb_flush; | |
995 | ulong lpages; | |
b8e8c830 | 996 | ulong nx_lpage_splits; |
f3414bc7 | 997 | ulong max_mmu_page_hash_collisions; |
0711456c ZX |
998 | }; |
999 | ||
77b4c255 | 1000 | struct kvm_vcpu_stat { |
8a7e75d4 SJS |
1001 | u64 pf_fixed; |
1002 | u64 pf_guest; | |
1003 | u64 tlb_flush; | |
1004 | u64 invlpg; | |
1005 | ||
1006 | u64 exits; | |
1007 | u64 io_exits; | |
1008 | u64 mmio_exits; | |
1009 | u64 signal_exits; | |
1010 | u64 irq_window_exits; | |
1011 | u64 nmi_window_exits; | |
c595ceee | 1012 | u64 l1d_flush; |
8a7e75d4 SJS |
1013 | u64 halt_exits; |
1014 | u64 halt_successful_poll; | |
1015 | u64 halt_attempted_poll; | |
1016 | u64 halt_poll_invalid; | |
1017 | u64 halt_wakeup; | |
1018 | u64 request_irq_exits; | |
1019 | u64 irq_exits; | |
1020 | u64 host_state_reload; | |
8a7e75d4 SJS |
1021 | u64 fpu_reload; |
1022 | u64 insn_emulation; | |
1023 | u64 insn_emulation_fail; | |
1024 | u64 hypercalls; | |
1025 | u64 irq_injections; | |
1026 | u64 nmi_injections; | |
0f1e261e | 1027 | u64 req_event; |
77b4c255 | 1028 | }; |
ad312c7c | 1029 | |
8a76d7f2 JR |
1030 | struct x86_instruction_info; |
1031 | ||
8fe8ab46 WA |
1032 | struct msr_data { |
1033 | bool host_initiated; | |
1034 | u32 index; | |
1035 | u64 data; | |
1036 | }; | |
1037 | ||
cb5281a5 PB |
1038 | struct kvm_lapic_irq { |
1039 | u32 vector; | |
b7cb2231 PB |
1040 | u16 delivery_mode; |
1041 | u16 dest_mode; | |
1042 | bool level; | |
1043 | u16 trig_mode; | |
cb5281a5 PB |
1044 | u32 shorthand; |
1045 | u32 dest_id; | |
93bbf0b8 | 1046 | bool msi_redir_hint; |
cb5281a5 PB |
1047 | }; |
1048 | ||
c96001c5 PX |
1049 | static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) |
1050 | { | |
1051 | return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; | |
1052 | } | |
1053 | ||
ea4a5ff8 ZX |
1054 | struct kvm_x86_ops { |
1055 | int (*cpu_has_kvm_support)(void); /* __init */ | |
1056 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
1057 | int (*hardware_enable)(void); |
1058 | void (*hardware_disable)(void); | |
f257d6dc | 1059 | int (*check_processor_compatibility)(void);/* __init */ |
ea4a5ff8 ZX |
1060 | int (*hardware_setup)(void); /* __init */ |
1061 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 1062 | bool (*cpu_has_accelerated_tpr)(void); |
bc226f07 | 1063 | bool (*has_emulated_msr)(int index); |
0e851880 | 1064 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1065 | |
562b6b08 | 1066 | unsigned int vm_size; |
03543133 SS |
1067 | int (*vm_init)(struct kvm *kvm); |
1068 | void (*vm_destroy)(struct kvm *kvm); | |
1069 | ||
ea4a5ff8 | 1070 | /* Create, but do not attach this VCPU */ |
987b2594 | 1071 | int (*vcpu_create)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1072 | void (*vcpu_free)(struct kvm_vcpu *vcpu); |
d28bc9dd | 1073 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
1074 | |
1075 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
1076 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
1077 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 1078 | |
a96036b8 | 1079 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 1080 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1081 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
1082 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
1083 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
1084 | struct kvm_segment *var, int seg); | |
2e4d2653 | 1085 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1086 | void (*set_segment)(struct kvm_vcpu *vcpu, |
1087 | struct kvm_segment *var, int seg); | |
1088 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 1089 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1090 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
1091 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
1092 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 1093 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 1094 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
1095 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
1096 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
1097 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
1098 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
1099 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
1100 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 1101 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 1102 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 1103 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
1104 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
1105 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
1106 | ||
c2ba05cc | 1107 | void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); |
b08660e5 | 1108 | int (*tlb_remote_flush)(struct kvm *kvm); |
a49b9635 LT |
1109 | int (*tlb_remote_flush_with_range)(struct kvm *kvm, |
1110 | struct kvm_tlb_range *range); | |
ea4a5ff8 | 1111 | |
faff8758 JS |
1112 | /* |
1113 | * Flush any TLB entries associated with the given GVA. | |
1114 | * Does not need to flush GPA->HPA mappings. | |
1115 | * Can potentially get non-canonical addresses through INVLPGs, which | |
1116 | * the implementation may choose to ignore if appropriate. | |
1117 | */ | |
1118 | void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); | |
ea4a5ff8 | 1119 | |
851ba692 | 1120 | void (*run)(struct kvm_vcpu *vcpu); |
1e9e2622 WL |
1121 | int (*handle_exit)(struct kvm_vcpu *vcpu, |
1122 | enum exit_fastpath_completion exit_fastpath); | |
f8ea7c60 | 1123 | int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
5ef8acbd | 1124 | void (*update_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 1125 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 1126 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1127 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
1128 | unsigned char *hypercall_addr); | |
66fd3f7f | 1129 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 1130 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
cfcd20e5 | 1131 | void (*queue_exception)(struct kvm_vcpu *vcpu); |
b463a6f7 | 1132 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 1133 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 1134 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
1135 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
1136 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
1137 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
1138 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 1139 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
ef8efd7a | 1140 | bool (*check_apicv_inhibit_reasons)(ulong bit); |
2de9d0cc | 1141 | void (*pre_update_apicv_exec_ctrl)(struct kvm *kvm, bool activate); |
d62caabb | 1142 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); |
c7c9c56c | 1143 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
67c9dddc | 1144 | void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); |
e6c67d8c | 1145 | bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); |
6308630b | 1146 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d860bbe | 1147 | void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); |
4256f43f | 1148 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
91a5f413 | 1149 | int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
76dfafd5 | 1150 | int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1151 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
2ac52ab8 | 1152 | int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); |
855feb67 | 1153 | int (*get_tdp_level)(struct kvm_vcpu *vcpu); |
4b12f0de | 1154 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 1155 | int (*get_lpage_level)(void); |
4e47c7a6 | 1156 | bool (*rdtscp_supported)(void); |
ad756a16 | 1157 | bool (*invpcid_supported)(void); |
344f414f | 1158 | |
1c97f0a0 JR |
1159 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
1160 | ||
d4330ef2 JR |
1161 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
1162 | ||
f5f48ee1 SY |
1163 | bool (*has_wbinvd_exit)(void); |
1164 | ||
e79f245d | 1165 | u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu); |
326e7425 LS |
1166 | /* Returns actual tsc_offset set in active VMCS */ |
1167 | u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); | |
99e3e30a | 1168 | |
586f9607 | 1169 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
1170 | |
1171 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
1172 | struct x86_instruction_info *info, | |
1173 | enum x86_intercept_stage stage); | |
1e9e2622 WL |
1174 | void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu, |
1175 | enum exit_fastpath_completion *exit_fastpath); | |
da8999d3 | 1176 | bool (*mpx_supported)(void); |
55412b2e | 1177 | bool (*xsaves_supported)(void); |
66336cab | 1178 | bool (*umip_emulated)(void); |
86f5201d | 1179 | bool (*pt_supported)(void); |
a47970ed | 1180 | bool (*pku_supported)(void); |
b6b8a145 | 1181 | |
a1c77abb | 1182 | int (*check_nested_events)(struct kvm_vcpu *vcpu); |
d264ee0c | 1183 | void (*request_immediate_exit)(struct kvm_vcpu *vcpu); |
ae97a3b8 RK |
1184 | |
1185 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
1186 | |
1187 | /* | |
1188 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
1189 | * be valid if the specific arch has hardware-accelerated dirty logging | |
1190 | * mechanism. Currently only for PML on VMX. | |
1191 | * | |
1192 | * - slot_enable_log_dirty: | |
1193 | * called when enabling log dirty mode for the slot. | |
1194 | * - slot_disable_log_dirty: | |
1195 | * called when disabling log dirty mode for the slot. | |
1196 | * also called when slot is created with log dirty disabled. | |
1197 | * - flush_log_dirty: | |
1198 | * called before reporting dirty_bitmap to userspace. | |
1199 | * - enable_log_dirty_pt_masked: | |
1200 | * called when reenabling log dirty for the GFNs in the mask after | |
1201 | * corresponding bits are cleared in slot->dirty_bitmap. | |
1202 | */ | |
1203 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
1204 | struct kvm_memory_slot *slot); | |
1205 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
1206 | struct kvm_memory_slot *slot); | |
1207 | void (*flush_log_dirty)(struct kvm *kvm); | |
1208 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
1209 | struct kvm_memory_slot *slot, | |
1210 | gfn_t offset, unsigned long mask); | |
bab4165e BD |
1211 | int (*write_log_dirty)(struct kvm_vcpu *vcpu); |
1212 | ||
25462f7f WH |
1213 | /* pmu operations of sub-arch */ |
1214 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 | 1215 | |
bf9f6ac8 FW |
1216 | /* |
1217 | * Architecture specific hooks for vCPU blocking due to | |
1218 | * HLT instruction. | |
1219 | * Returns for .pre_block(): | |
1220 | * - 0 means continue to block the vCPU. | |
1221 | * - 1 means we cannot block the vCPU since some event | |
1222 | * happens during this period, such as, 'ON' bit in | |
1223 | * posted-interrupts descriptor is set. | |
1224 | */ | |
1225 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
1226 | void (*post_block)(struct kvm_vcpu *vcpu); | |
d1ed092f SS |
1227 | |
1228 | void (*vcpu_blocking)(struct kvm_vcpu *vcpu); | |
1229 | void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); | |
1230 | ||
efc64404 FW |
1231 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
1232 | uint32_t guest_irq, bool set); | |
be8ca170 | 1233 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); |
17e433b5 | 1234 | bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); |
ce7a058a | 1235 | |
f9927982 SC |
1236 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, |
1237 | bool *expired); | |
ce7a058a | 1238 | void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); |
c45dcc71 AR |
1239 | |
1240 | void (*setup_mce)(struct kvm_vcpu *vcpu); | |
0234bf88 | 1241 | |
8fcc4b59 JM |
1242 | int (*get_nested_state)(struct kvm_vcpu *vcpu, |
1243 | struct kvm_nested_state __user *user_kvm_nested_state, | |
1244 | unsigned user_data_size); | |
1245 | int (*set_nested_state)(struct kvm_vcpu *vcpu, | |
1246 | struct kvm_nested_state __user *user_kvm_nested_state, | |
1247 | struct kvm_nested_state *kvm_state); | |
671ddc70 | 1248 | bool (*get_vmcs12_pages)(struct kvm_vcpu *vcpu); |
7f7f1ba3 | 1249 | |
72d7b374 | 1250 | int (*smi_allowed)(struct kvm_vcpu *vcpu); |
0234bf88 | 1251 | int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); |
ed19321f | 1252 | int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); |
cc3d967f | 1253 | int (*enable_smi_window)(struct kvm_vcpu *vcpu); |
5acc5c06 BS |
1254 | |
1255 | int (*mem_enc_op)(struct kvm *kvm, void __user *argp); | |
69eaedee BS |
1256 | int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); |
1257 | int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); | |
801e459a TL |
1258 | |
1259 | int (*get_msr_feature)(struct kvm_msr_entry *entry); | |
57b119da VK |
1260 | |
1261 | int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu, | |
1262 | uint16_t *vmcs_version); | |
e2e871ab | 1263 | uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu); |
05d5a486 SB |
1264 | |
1265 | bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); | |
4b9852f4 LA |
1266 | |
1267 | bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); | |
344c6c80 | 1268 | int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1269 | }; |
1270 | ||
af585b92 | 1271 | struct kvm_arch_async_pf { |
7c90705b | 1272 | u32 token; |
af585b92 | 1273 | gfn_t gfn; |
fb67e14f | 1274 | unsigned long cr3; |
c4806acd | 1275 | bool direct_map; |
af585b92 GN |
1276 | }; |
1277 | ||
97896d04 | 1278 | extern struct kvm_x86_ops *kvm_x86_ops; |
b666a4b6 | 1279 | extern struct kmem_cache *x86_fpu_cache; |
97896d04 | 1280 | |
434a1e94 SC |
1281 | #define __KVM_HAVE_ARCH_VM_ALLOC |
1282 | static inline struct kvm *kvm_arch_alloc_vm(void) | |
1283 | { | |
562b6b08 SC |
1284 | return __vmalloc(kvm_x86_ops->vm_size, |
1285 | GFP_KERNEL_ACCOUNT | __GFP_ZERO, PAGE_KERNEL); | |
434a1e94 | 1286 | } |
562b6b08 | 1287 | void kvm_arch_free_vm(struct kvm *kvm); |
434a1e94 | 1288 | |
b08660e5 TL |
1289 | #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB |
1290 | static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) | |
1291 | { | |
1292 | if (kvm_x86_ops->tlb_remote_flush && | |
1293 | !kvm_x86_ops->tlb_remote_flush(kvm)) | |
1294 | return 0; | |
1295 | else | |
1296 | return -ENOTSUPP; | |
1297 | } | |
1298 | ||
54f1585a ZX |
1299 | int kvm_mmu_module_init(void); |
1300 | void kvm_mmu_module_exit(void); | |
1301 | ||
1302 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
1303 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
13d268ca XG |
1304 | void kvm_mmu_init_vm(struct kvm *kvm); |
1305 | void kvm_mmu_uninit_vm(struct kvm *kvm); | |
7b52345e | 1306 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 1307 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 1308 | u64 acc_track_mask, u64 me_mask); |
54f1585a | 1309 | |
8a3c1a33 | 1310 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 | 1311 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
1312 | struct kvm_memory_slot *memslot, |
1313 | int start_level); | |
3ea3b7fa | 1314 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 1315 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
1316 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
1317 | struct kvm_memory_slot *memslot); | |
1318 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
1319 | struct kvm_memory_slot *memslot); | |
1320 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
1321 | struct kvm_memory_slot *memslot); | |
1322 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1323 | struct kvm_memory_slot *slot, | |
1324 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 1325 | void kvm_mmu_zap_all(struct kvm *kvm); |
15248258 | 1326 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); |
bc8a3d89 BG |
1327 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); |
1328 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); | |
54f1585a | 1329 | |
ff03a073 | 1330 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
9ed38ffa | 1331 | bool pdptrs_changed(struct kvm_vcpu *vcpu); |
cc4b6871 | 1332 | |
3200f405 | 1333 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 1334 | const void *val, int bytes); |
2f333bcb | 1335 | |
6ef768fa PB |
1336 | struct kvm_irq_mask_notifier { |
1337 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
1338 | int irq; | |
1339 | struct hlist_node link; | |
1340 | }; | |
1341 | ||
1342 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1343 | struct kvm_irq_mask_notifier *kimn); | |
1344 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1345 | struct kvm_irq_mask_notifier *kimn); | |
1346 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1347 | bool mask); | |
1348 | ||
2f333bcb | 1349 | extern bool tdp_enabled; |
9f811285 | 1350 | |
a3e06bbe LJ |
1351 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
1352 | ||
92a1f12d JR |
1353 | /* control of guest tsc rate supported? */ |
1354 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
1355 | /* maximum supported tsc_khz for guests */ |
1356 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
1357 | /* number of bits of the fractional part of the TSC scaling ratio */ |
1358 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1359 | /* maximum allowed value of TSC scaling ratio */ | |
1360 | extern u64 kvm_max_tsc_scaling_ratio; | |
64672c95 YJ |
1361 | /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ |
1362 | extern u64 kvm_default_tsc_scaling_ratio; | |
92a1f12d | 1363 | |
c45dcc71 | 1364 | extern u64 kvm_mce_cap_supported; |
92a1f12d | 1365 | |
41577ab8 SC |
1366 | /* |
1367 | * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing | |
1368 | * userspace I/O) to indicate that the emulation context | |
1369 | * should be resued as is, i.e. skip initialization of | |
1370 | * emulation context, instruction fetch and decode. | |
1371 | * | |
1372 | * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. | |
1373 | * Indicates that only select instructions (tagged with | |
1374 | * EmulateOnUD) should be emulated (to minimize the emulator | |
1375 | * attack surface). See also EMULTYPE_TRAP_UD_FORCED. | |
1376 | * | |
1377 | * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to | |
1378 | * decode the instruction length. For use *only* by | |
1379 | * kvm_x86_ops->skip_emulated_instruction() implementations. | |
1380 | * | |
92daa48b SC |
1381 | * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to |
1382 | * retry native execution under certain conditions, | |
1383 | * Can only be set in conjunction with EMULTYPE_PF. | |
41577ab8 SC |
1384 | * |
1385 | * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was | |
1386 | * triggered by KVM's magic "force emulation" prefix, | |
1387 | * which is opt in via module param (off by default). | |
1388 | * Bypasses EmulateOnUD restriction despite emulating | |
1389 | * due to an intercepted #UD (see EMULTYPE_TRAP_UD). | |
1390 | * Used to test the full emulator from userspace. | |
1391 | * | |
1392 | * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware | |
1393 | * backdoor emulation, which is opt in via module param. | |
1394 | * VMware backoor emulation handles select instructions | |
1395 | * and reinjects the #GP for all other cases. | |
92daa48b SC |
1396 | * |
1397 | * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which | |
1398 | * case the CR2/GPA value pass on the stack is valid. | |
41577ab8 | 1399 | */ |
571008da SY |
1400 | #define EMULTYPE_NO_DECODE (1 << 0) |
1401 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1402 | #define EMULTYPE_SKIP (1 << 2) |
92daa48b | 1403 | #define EMULTYPE_ALLOW_RETRY_PF (1 << 3) |
b4000606 | 1404 | #define EMULTYPE_TRAP_UD_FORCED (1 << 4) |
42cbf068 | 1405 | #define EMULTYPE_VMWARE_GP (1 << 5) |
92daa48b SC |
1406 | #define EMULTYPE_PF (1 << 6) |
1407 | ||
c60658d1 SC |
1408 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); |
1409 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
1410 | void *insn, int insn_len); | |
35be0ade | 1411 | |
f2b4b7dd | 1412 | void kvm_enable_efer_bits(u64); |
384bb783 | 1413 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
edef5c36 | 1414 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); |
f20935d8 SC |
1415 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); |
1416 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); | |
1edce0a9 SC |
1417 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); |
1418 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); | |
54f1585a ZX |
1419 | |
1420 | struct x86_emulate_ctxt; | |
1421 | ||
dca7f128 | 1422 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); |
6a908b62 | 1423 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
54f1585a | 1424 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); |
5cb56059 | 1425 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1426 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1427 | |
3e6e0aab | 1428 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1429 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1430 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1431 | |
7f3d35fd KW |
1432 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1433 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1434 | |
49a9b07e | 1435 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1436 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1437 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1438 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1439 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1440 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1441 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1442 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1443 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1444 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1445 | |
609e36d3 | 1446 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1447 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1448 | |
91586a3b JK |
1449 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1450 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1451 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1452 | |
298101da AK |
1453 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1454 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1455 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1456 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1457 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1458 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1459 | gfn_t gfn, void *data, int offset, int len, | |
1460 | u32 access); | |
0a79b009 | 1461 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1462 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1463 | |
1a577b72 MT |
1464 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1465 | int irq_source_id, int level) | |
1466 | { | |
1467 | /* Logical OR for level trig interrupt */ | |
1468 | if (level) | |
1469 | __set_bit(irq_source_id, irq_state); | |
1470 | else | |
1471 | __clear_bit(irq_source_id, irq_state); | |
1472 | ||
1473 | return !!(*irq_state); | |
1474 | } | |
1475 | ||
b94742c9 JS |
1476 | #define KVM_MMU_ROOT_CURRENT BIT(0) |
1477 | #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) | |
1478 | #define KVM_MMU_ROOTS_ALL (~0UL) | |
08fb59d8 | 1479 | |
1a577b72 MT |
1480 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); |
1481 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1482 | |
3419ffc8 SY |
1483 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1484 | ||
1cb3f3ae | 1485 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1486 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1487 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1488 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1489 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1490 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
6a82cd1c VK |
1491 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1492 | ulong roots_to_free); | |
54987b7a PB |
1493 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1494 | struct x86_exception *exception); | |
ab9ae313 AK |
1495 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1496 | struct x86_exception *exception); | |
1497 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1498 | struct x86_exception *exception); | |
1499 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1500 | struct x86_exception *exception); | |
1501 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1502 | struct x86_exception *exception); | |
54f1585a | 1503 | |
4e19c36f SS |
1504 | bool kvm_apicv_activated(struct kvm *kvm); |
1505 | void kvm_apicv_init(struct kvm *kvm, bool enable); | |
8df14af4 SS |
1506 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu); |
1507 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, | |
1508 | unsigned long bit); | |
d62caabb | 1509 | |
54f1585a ZX |
1510 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1511 | ||
736c291c | 1512 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 1513 | void *insn, int insn_len); |
a7052897 | 1514 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
eb4b248e | 1515 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); |
ade61e28 | 1516 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush); |
34c16eec | 1517 | |
18552672 | 1518 | void kvm_enable_tdp(void); |
5f4cb662 | 1519 | void kvm_disable_tdp(void); |
18552672 | 1520 | |
54987b7a PB |
1521 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1522 | struct x86_exception *exception) | |
e459e322 XG |
1523 | { |
1524 | return gpa; | |
1525 | } | |
1526 | ||
ec6d273d ZX |
1527 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1528 | { | |
1529 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1530 | ||
1531 | return (struct kvm_mmu_page *)page_private(page); | |
1532 | } | |
1533 | ||
d6e88aec | 1534 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1535 | { |
1536 | u16 ldt; | |
1537 | asm("sldt %0" : "=g"(ldt)); | |
1538 | return ldt; | |
1539 | } | |
1540 | ||
d6e88aec | 1541 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1542 | { |
1543 | asm("lldt %0" : : "rm"(sel)); | |
1544 | } | |
ec6d273d | 1545 | |
ec6d273d ZX |
1546 | #ifdef CONFIG_X86_64 |
1547 | static inline unsigned long read_msr(unsigned long msr) | |
1548 | { | |
1549 | u64 value; | |
1550 | ||
1551 | rdmsrl(msr, value); | |
1552 | return value; | |
1553 | } | |
1554 | #endif | |
1555 | ||
ec6d273d ZX |
1556 | static inline u32 get_rdx_init_val(void) |
1557 | { | |
1558 | return 0x600; /* P6 family */ | |
1559 | } | |
1560 | ||
c1a5d4f9 AK |
1561 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1562 | { | |
1563 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1564 | } | |
1565 | ||
ec6d273d ZX |
1566 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1567 | #define TSS_BASE_SIZE 0x68 | |
1568 | #define TSS_IOPB_SIZE (65536 / 8) | |
1569 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1570 | #define RMODE_TSS_SIZE \ |
1571 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1572 | |
37817f29 IE |
1573 | enum { |
1574 | TASK_SWITCH_CALL = 0, | |
1575 | TASK_SWITCH_IRET = 1, | |
1576 | TASK_SWITCH_JMP = 2, | |
1577 | TASK_SWITCH_GATE = 3, | |
1578 | }; | |
1579 | ||
1371d904 | 1580 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1581 | #define HF_HIF_MASK (1 << 1) |
1582 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1583 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1584 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1585 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1586 | #define HF_SMM_MASK (1 << 6) |
1587 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1588 | |
699023e2 PB |
1589 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1590 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1591 | ||
1592 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1593 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1594 | |
4b526de5 | 1595 | asmlinkage void kvm_spurious_fault(void); |
3901336e | 1596 | |
4ecac3fd AK |
1597 | /* |
1598 | * Hardware virtualization extension instructions may fault if a | |
1599 | * reboot turns off virtualization while processes are running. | |
3901336e JP |
1600 | * Usually after catching the fault we just panic; during reboot |
1601 | * instead the instruction is ignored. | |
4ecac3fd | 1602 | */ |
98cd382d | 1603 | #define __kvm_handle_fault_on_reboot(insn) \ |
3901336e JP |
1604 | "666: \n\t" \ |
1605 | insn "\n\t" \ | |
1606 | "jmp 668f \n\t" \ | |
1607 | "667: \n\t" \ | |
1608 | "call kvm_spurious_fault \n\t" \ | |
1609 | "668: \n\t" \ | |
f209a26d | 1610 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1611 | |
e930bffe | 1612 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
b3ae2096 | 1613 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1614 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1615 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
748c0e31 | 1616 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1617 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1618 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1619 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1620 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1621 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1622 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
e930bffe | 1623 | |
4180bf1b | 1624 | int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, |
bdf7ffc8 | 1625 | unsigned long ipi_bitmap_high, u32 min, |
4180bf1b WL |
1626 | unsigned long icr, int op_64_bit); |
1627 | ||
18863bdd | 1628 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1629 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1630 | |
35181e86 | 1631 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1632 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1633 | |
82b32774 | 1634 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1635 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1636 | ||
2860c4b1 PB |
1637 | void kvm_make_mclock_inprogress_request(struct kvm *kvm); |
1638 | void kvm_make_scan_ioapic_request(struct kvm *kvm); | |
7ee30bc1 NNL |
1639 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
1640 | unsigned long *vcpu_bitmap); | |
2860c4b1 | 1641 | |
af585b92 GN |
1642 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1643 | struct kvm_async_pf *work); | |
1644 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1645 | struct kvm_async_pf *work); | |
56028d08 GN |
1646 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1647 | struct kvm_async_pf *work); | |
7c90705b | 1648 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1649 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1650 | ||
6affcbed KH |
1651 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); |
1652 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); | |
d264ee0c | 1653 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); |
db8fcefa | 1654 | |
f5132b01 GN |
1655 | int kvm_is_in_guest(void); |
1656 | ||
1d8007bd | 1657 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); |
d71ba788 PB |
1658 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1659 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1660 | |
8feb4a04 FW |
1661 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1662 | struct kvm_vcpu **dest_vcpu); | |
1663 | ||
37131313 | 1664 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 1665 | struct kvm_lapic_irq *irq); |
197a4f4b | 1666 | |
fdcf7562 AG |
1667 | static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) |
1668 | { | |
1669 | /* We can only post Fixed and LowPrio IRQs */ | |
1670 | return (irq->delivery_mode == dest_Fixed || | |
1671 | irq->delivery_mode == dest_LowestPrio); | |
1672 | } | |
1673 | ||
d1ed092f SS |
1674 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) |
1675 | { | |
1676 | if (kvm_x86_ops->vcpu_blocking) | |
1677 | kvm_x86_ops->vcpu_blocking(vcpu); | |
1678 | } | |
1679 | ||
1680 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1681 | { | |
1682 | if (kvm_x86_ops->vcpu_unblocking) | |
1683 | kvm_x86_ops->vcpu_unblocking(vcpu); | |
1684 | } | |
1685 | ||
3491caf2 | 1686 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
3217f7c2 | 1687 | |
7d669f50 SS |
1688 | static inline int kvm_cpu_get_apicid(int mps_cpu) |
1689 | { | |
1690 | #ifdef CONFIG_X86_LOCAL_APIC | |
64063505 | 1691 | return default_cpu_present_to_apicid(mps_cpu); |
7d669f50 SS |
1692 | #else |
1693 | WARN_ON_ONCE(1); | |
1694 | return BAD_APICID; | |
1695 | #endif | |
1696 | } | |
1697 | ||
05cade71 LP |
1698 | #define put_smstate(type, buf, offset, val) \ |
1699 | *(type *)((buf) + (offset) - 0x7e00) = val | |
1700 | ||
ed19321f SC |
1701 | #define GET_SMSTATE(type, buf, offset) \ |
1702 | (*(type *)((buf) + (offset) - 0x7e00)) | |
1703 | ||
1965aae3 | 1704 | #endif /* _ASM_X86_KVM_HOST_H */ |