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Commit | Line | Data |
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a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
34c16eec | 27 | |
50d0a0f9 | 28 | #include <asm/pvclock-abi.h> |
e01a1b57 | 29 | #include <asm/desc.h> |
0bed3b56 | 30 | #include <asm/mtrr.h> |
9962d032 | 31 | #include <asm/msr-index.h> |
3ee89722 | 32 | #include <asm/asm.h> |
e01a1b57 | 33 | |
cbf64358 | 34 | #define KVM_MAX_VCPUS 255 |
a59cb29e | 35 | #define KVM_SOFT_MAX_VCPUS 160 |
1d4e7e3c | 36 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
37 | /* memory slots that are not exposed to userspace */ |
38 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 39 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 40 | |
69a9f69b | 41 | #define KVM_PIO_PAGE_OFFSET 1 |
542472b5 | 42 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
920552b2 | 43 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
69a9f69b | 44 | |
8175e5b7 AG |
45 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
46 | ||
cfec82cb JR |
47 | #define CR0_RESERVED_BITS \ |
48 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
49 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
50 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
51 | ||
346874c9 | 52 | #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL |
cfaa790a | 53 | #define CR3_PCID_INVD BIT_64(63) |
cfec82cb JR |
54 | #define CR4_RESERVED_BITS \ |
55 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
56 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 57 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 58 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
56d6efc2 | 59 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP)) |
cfec82cb JR |
60 | |
61 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
62 | ||
63 | ||
cd6e8f87 | 64 | |
cd6e8f87 | 65 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
66 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
67 | ||
cd6e8f87 ZX |
68 | #define UNMAPPED_GVA (~(gpa_t)0) |
69 | ||
ec04b260 | 70 | /* KVM Hugepage definitions for x86 */ |
04326caa | 71 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
72 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
73 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
74 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
75 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
76 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 77 | |
6d9d41e5 CD |
78 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
79 | { | |
80 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
81 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
82 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
83 | } | |
84 | ||
d657a98e ZX |
85 | #define KVM_PERMILLE_MMU_PAGES 20 |
86 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
87 | #define KVM_MMU_HASH_SHIFT 10 |
88 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
89 | #define KVM_MIN_FREE_MMU_PAGES 5 |
90 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 91 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 92 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 93 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 94 | |
af585b92 GN |
95 | #define ASYNC_PF_PER_VCPU 64 |
96 | ||
5fdbf976 | 97 | enum kvm_reg { |
2b3ccfa0 ZX |
98 | VCPU_REGS_RAX = 0, |
99 | VCPU_REGS_RCX = 1, | |
100 | VCPU_REGS_RDX = 2, | |
101 | VCPU_REGS_RBX = 3, | |
102 | VCPU_REGS_RSP = 4, | |
103 | VCPU_REGS_RBP = 5, | |
104 | VCPU_REGS_RSI = 6, | |
105 | VCPU_REGS_RDI = 7, | |
106 | #ifdef CONFIG_X86_64 | |
107 | VCPU_REGS_R8 = 8, | |
108 | VCPU_REGS_R9 = 9, | |
109 | VCPU_REGS_R10 = 10, | |
110 | VCPU_REGS_R11 = 11, | |
111 | VCPU_REGS_R12 = 12, | |
112 | VCPU_REGS_R13 = 13, | |
113 | VCPU_REGS_R14 = 14, | |
114 | VCPU_REGS_R15 = 15, | |
115 | #endif | |
5fdbf976 | 116 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
117 | NR_VCPU_REGS |
118 | }; | |
119 | ||
6de4f3ad AK |
120 | enum kvm_reg_ex { |
121 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 122 | VCPU_EXREG_CR3, |
6de12732 | 123 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 124 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
125 | }; |
126 | ||
2b3ccfa0 | 127 | enum { |
81609e3e | 128 | VCPU_SREG_ES, |
2b3ccfa0 | 129 | VCPU_SREG_CS, |
81609e3e | 130 | VCPU_SREG_SS, |
2b3ccfa0 | 131 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
132 | VCPU_SREG_FS, |
133 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
134 | VCPU_SREG_TR, |
135 | VCPU_SREG_LDTR, | |
136 | }; | |
137 | ||
56e82318 | 138 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 139 | |
d657a98e ZX |
140 | #define KVM_NR_MEM_OBJS 40 |
141 | ||
42dbaa5a JK |
142 | #define KVM_NR_DB_REGS 4 |
143 | ||
144 | #define DR6_BD (1 << 13) | |
145 | #define DR6_BS (1 << 14) | |
6f43ed01 NA |
146 | #define DR6_RTM (1 << 16) |
147 | #define DR6_FIXED_1 0xfffe0ff0 | |
148 | #define DR6_INIT 0xffff0ff0 | |
149 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
150 | |
151 | #define DR7_BP_EN_MASK 0x000000ff | |
152 | #define DR7_GE (1 << 9) | |
153 | #define DR7_GD (1 << 13) | |
154 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 155 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 156 | |
c205fb7d NA |
157 | #define PFERR_PRESENT_BIT 0 |
158 | #define PFERR_WRITE_BIT 1 | |
159 | #define PFERR_USER_BIT 2 | |
160 | #define PFERR_RSVD_BIT 3 | |
161 | #define PFERR_FETCH_BIT 4 | |
162 | ||
163 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
164 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
165 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
166 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
167 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
168 | ||
41383771 GN |
169 | /* apic attention bits */ |
170 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
171 | /* |
172 | * The following bit is set with PV-EOI, unset on EOI. | |
173 | * We detect PV-EOI changes by guest by comparing | |
174 | * this bit with PV-EOI in guest memory. | |
175 | * See the implementation in apic_update_pv_eoi. | |
176 | */ | |
177 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 178 | |
d84f1e07 FW |
179 | struct kvm_kernel_irq_routing_entry; |
180 | ||
d657a98e ZX |
181 | /* |
182 | * We don't want allocation failures within the mmu code, so we preallocate | |
183 | * enough memory for a single page fault in a cache. | |
184 | */ | |
185 | struct kvm_mmu_memory_cache { | |
186 | int nobjs; | |
187 | void *objects[KVM_NR_MEM_OBJS]; | |
188 | }; | |
189 | ||
d657a98e ZX |
190 | union kvm_mmu_page_role { |
191 | unsigned word; | |
192 | struct { | |
7d76b4d3 | 193 | unsigned level:4; |
5b7e0102 | 194 | unsigned cr4_pae:1; |
7d76b4d3 | 195 | unsigned quadrant:2; |
f6e2c02b | 196 | unsigned direct:1; |
7d76b4d3 | 197 | unsigned access:3; |
2e53d63a | 198 | unsigned invalid:1; |
9645bb56 | 199 | unsigned nxe:1; |
3dbe1415 | 200 | unsigned cr0_wp:1; |
411c588d | 201 | unsigned smep_andnot_wp:1; |
0be0226f | 202 | unsigned smap_andnot_wp:1; |
699023e2 PB |
203 | unsigned :8; |
204 | ||
205 | /* | |
206 | * This is left at the top of the word so that | |
207 | * kvm_memslots_for_spte_role can extract it with a | |
208 | * simple shift. While there is room, give it a whole | |
209 | * byte so it is also faster to load it from memory. | |
210 | */ | |
211 | unsigned smm:8; | |
d657a98e ZX |
212 | }; |
213 | }; | |
214 | ||
215 | struct kvm_mmu_page { | |
216 | struct list_head link; | |
217 | struct hlist_node hash_link; | |
218 | ||
219 | /* | |
220 | * The following two entries are used to key the shadow page in the | |
221 | * hash table. | |
222 | */ | |
223 | gfn_t gfn; | |
224 | union kvm_mmu_page_role role; | |
225 | ||
226 | u64 *spt; | |
227 | /* hold the gfn of each spte inside spt */ | |
228 | gfn_t *gfns; | |
4731d4c7 | 229 | bool unsync; |
0571d366 | 230 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 231 | unsigned int unsync_children; |
67052b35 | 232 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
f6f8adee XG |
233 | |
234 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 235 | unsigned long mmu_valid_gen; |
f6f8adee | 236 | |
0074ff63 | 237 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
238 | |
239 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
240 | /* |
241 | * Used out of the mmu-lock to avoid reading spte values while an | |
242 | * update is in progress; see the comments in __get_spte_lockless(). | |
243 | */ | |
c2a2ac2b XG |
244 | int clear_spte_count; |
245 | #endif | |
246 | ||
0cbf8e43 | 247 | /* Number of writes since the last time traversal visited this page. */ |
a30f47cb | 248 | int write_flooding_count; |
d657a98e ZX |
249 | }; |
250 | ||
1c08364c AK |
251 | struct kvm_pio_request { |
252 | unsigned long count; | |
1c08364c AK |
253 | int in; |
254 | int port; | |
255 | int size; | |
1c08364c AK |
256 | }; |
257 | ||
a0a64f50 XG |
258 | struct rsvd_bits_validate { |
259 | u64 rsvd_bits_mask[2][4]; | |
260 | u64 bad_mt_xwr; | |
261 | }; | |
262 | ||
d657a98e ZX |
263 | /* |
264 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
265 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
266 | * mode. | |
267 | */ | |
268 | struct kvm_mmu { | |
f43addd4 | 269 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 270 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 271 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
272 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
273 | bool prefault); | |
6389ee94 AK |
274 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
275 | struct x86_exception *fault); | |
1871c602 | 276 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 277 | struct x86_exception *exception); |
54987b7a PB |
278 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
279 | struct x86_exception *exception); | |
e8bc217a | 280 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 281 | struct kvm_mmu_page *sp); |
a7052897 | 282 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 283 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 284 | u64 *spte, const void *pte); |
d657a98e ZX |
285 | hpa_t root_hpa; |
286 | int root_level; | |
287 | int shadow_root_level; | |
a770f6f2 | 288 | union kvm_mmu_page_role base_role; |
c5a78f2b | 289 | bool direct_map; |
d657a98e | 290 | |
97d64b78 AK |
291 | /* |
292 | * Bitmap; bit set = permission fault | |
293 | * Byte index: page fault error code [4:1] | |
294 | * Bit index: pte permissions in ACC_* format | |
295 | */ | |
296 | u8 permissions[16]; | |
297 | ||
d657a98e | 298 | u64 *pae_root; |
81407ca5 | 299 | u64 *lm_root; |
c258b62b XG |
300 | |
301 | /* | |
302 | * check zero bits on shadow page table entries, these | |
303 | * bits include not only hardware reserved bits but also | |
304 | * the bits spte never used. | |
305 | */ | |
306 | struct rsvd_bits_validate shadow_zero_check; | |
307 | ||
a0a64f50 | 308 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 309 | |
6fd01b71 AK |
310 | /* |
311 | * Bitmap: bit set = last pte in walk | |
312 | * index[0:1]: level (zero-based) | |
313 | * index[2]: pte.ps | |
314 | */ | |
315 | u8 last_pte_bitmap; | |
316 | ||
2d48a985 JR |
317 | bool nx; |
318 | ||
ff03a073 | 319 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
320 | }; |
321 | ||
f5132b01 GN |
322 | enum pmc_type { |
323 | KVM_PMC_GP = 0, | |
324 | KVM_PMC_FIXED, | |
325 | }; | |
326 | ||
327 | struct kvm_pmc { | |
328 | enum pmc_type type; | |
329 | u8 idx; | |
330 | u64 counter; | |
331 | u64 eventsel; | |
332 | struct perf_event *perf_event; | |
333 | struct kvm_vcpu *vcpu; | |
334 | }; | |
335 | ||
336 | struct kvm_pmu { | |
337 | unsigned nr_arch_gp_counters; | |
338 | unsigned nr_arch_fixed_counters; | |
339 | unsigned available_event_types; | |
340 | u64 fixed_ctr_ctrl; | |
341 | u64 global_ctrl; | |
342 | u64 global_status; | |
343 | u64 global_ovf_ctrl; | |
344 | u64 counter_bitmask[2]; | |
345 | u64 global_ctrl_mask; | |
103af0a9 | 346 | u64 reserved_bits; |
f5132b01 | 347 | u8 version; |
15c7ad51 RR |
348 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
349 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
350 | struct irq_work irq_work; |
351 | u64 reprogram_pmi; | |
352 | }; | |
353 | ||
25462f7f WH |
354 | struct kvm_pmu_ops; |
355 | ||
360b948d PB |
356 | enum { |
357 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 358 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 359 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
360 | }; |
361 | ||
86fd5270 XG |
362 | struct kvm_mtrr_range { |
363 | u64 base; | |
364 | u64 mask; | |
19efffa2 | 365 | struct list_head node; |
86fd5270 XG |
366 | }; |
367 | ||
70109e7d | 368 | struct kvm_mtrr { |
86fd5270 | 369 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 370 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 371 | u64 deftype; |
19efffa2 XG |
372 | |
373 | struct list_head head; | |
70109e7d XG |
374 | }; |
375 | ||
e83d5887 AS |
376 | /* Hyper-V per vcpu emulation context */ |
377 | struct kvm_vcpu_hv { | |
378 | u64 hv_vapic; | |
9eec50b8 | 379 | s64 runtime_offset; |
e83d5887 AS |
380 | }; |
381 | ||
ad312c7c | 382 | struct kvm_vcpu_arch { |
5fdbf976 MT |
383 | /* |
384 | * rip and regs accesses must go through | |
385 | * kvm_{register,rip}_{read,write} functions. | |
386 | */ | |
387 | unsigned long regs[NR_VCPU_REGS]; | |
388 | u32 regs_avail; | |
389 | u32 regs_dirty; | |
34c16eec ZX |
390 | |
391 | unsigned long cr0; | |
e8467fda | 392 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
393 | unsigned long cr2; |
394 | unsigned long cr3; | |
395 | unsigned long cr4; | |
fc78f519 | 396 | unsigned long cr4_guest_owned_bits; |
34c16eec | 397 | unsigned long cr8; |
1371d904 | 398 | u32 hflags; |
f6801dff | 399 | u64 efer; |
34c16eec ZX |
400 | u64 apic_base; |
401 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
3bb345f3 | 402 | u64 eoi_exit_bitmap[4]; |
41383771 | 403 | unsigned long apic_attention; |
e1035715 | 404 | int32_t apic_arb_prio; |
34c16eec | 405 | int mp_state; |
34c16eec | 406 | u64 ia32_misc_enable_msr; |
64d60670 | 407 | u64 smbase; |
b209749f | 408 | bool tpr_access_reporting; |
20300099 | 409 | u64 ia32_xss; |
34c16eec | 410 | |
14dfe855 JR |
411 | /* |
412 | * Paging state of the vcpu | |
413 | * | |
414 | * If the vcpu runs in guest mode with two level paging this still saves | |
415 | * the paging mode of the l1 guest. This context is always used to | |
416 | * handle faults. | |
417 | */ | |
34c16eec | 418 | struct kvm_mmu mmu; |
8df25a32 | 419 | |
6539e738 JR |
420 | /* |
421 | * Paging state of an L2 guest (used for nested npt) | |
422 | * | |
423 | * This context will save all necessary information to walk page tables | |
424 | * of the an L2 guest. This context is only initialized for page table | |
425 | * walking and not for faulting since we never handle l2 page faults on | |
426 | * the host. | |
427 | */ | |
428 | struct kvm_mmu nested_mmu; | |
429 | ||
14dfe855 JR |
430 | /* |
431 | * Pointer to the mmu context currently used for | |
432 | * gva_to_gpa translations. | |
433 | */ | |
434 | struct kvm_mmu *walk_mmu; | |
435 | ||
53c07b18 | 436 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
437 | struct kvm_mmu_memory_cache mmu_page_cache; |
438 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
439 | ||
98918833 | 440 | struct fpu guest_fpu; |
c447e76b | 441 | bool eager_fpu; |
2acf923e | 442 | u64 xcr0; |
d7876f1b | 443 | u64 guest_supported_xcr0; |
4344ee98 | 444 | u32 guest_xstate_size; |
34c16eec | 445 | |
34c16eec ZX |
446 | struct kvm_pio_request pio; |
447 | void *pio_data; | |
448 | ||
66fd3f7f GN |
449 | u8 event_exit_inst_len; |
450 | ||
298101da AK |
451 | struct kvm_queued_exception { |
452 | bool pending; | |
453 | bool has_error_code; | |
ce7ddec4 | 454 | bool reinject; |
298101da AK |
455 | u8 nr; |
456 | u32 error_code; | |
457 | } exception; | |
458 | ||
937a7eae AK |
459 | struct kvm_queued_interrupt { |
460 | bool pending; | |
66fd3f7f | 461 | bool soft; |
937a7eae AK |
462 | u8 nr; |
463 | } interrupt; | |
464 | ||
34c16eec ZX |
465 | int halt_request; /* real mode on Intel only */ |
466 | ||
467 | int cpuid_nent; | |
07716717 | 468 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
469 | |
470 | int maxphyaddr; | |
471 | ||
34c16eec ZX |
472 | /* emulate context */ |
473 | ||
474 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
475 | bool emulate_regs_need_sync_to_vcpu; |
476 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 477 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
478 | |
479 | gpa_t time; | |
50d0a0f9 | 480 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 481 | unsigned int hw_tsc_khz; |
0b79459b AH |
482 | struct gfn_to_hva_cache pv_time; |
483 | bool pv_time_enabled; | |
51d59c6b MT |
484 | /* set guest stopped flag in pvclock flags field */ |
485 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
486 | |
487 | struct { | |
488 | u64 msr_val; | |
489 | u64 last_steal; | |
490 | u64 accum_steal; | |
491 | struct gfn_to_hva_cache stime; | |
492 | struct kvm_steal_time steal; | |
493 | } st; | |
494 | ||
1d5f066e | 495 | u64 last_guest_tsc; |
6f526ec5 | 496 | u64 last_host_tsc; |
0dd6a6ed | 497 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
498 | u64 this_tsc_nsec; |
499 | u64 this_tsc_write; | |
0d3da0d2 | 500 | u64 this_tsc_generation; |
c285545f | 501 | bool tsc_catchup; |
cc578287 ZA |
502 | bool tsc_always_catchup; |
503 | s8 virtual_tsc_shift; | |
504 | u32 virtual_tsc_mult; | |
505 | u32 virtual_tsc_khz; | |
ba904635 | 506 | s64 ia32_tsc_adjust_msr; |
3419ffc8 | 507 | |
7460fb4a AK |
508 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
509 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
510 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 511 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 512 | |
70109e7d | 513 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 514 | u64 pat; |
42dbaa5a | 515 | |
360b948d | 516 | unsigned switch_db_regs; |
42dbaa5a JK |
517 | unsigned long db[KVM_NR_DB_REGS]; |
518 | unsigned long dr6; | |
519 | unsigned long dr7; | |
520 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 521 | unsigned long guest_debug_dr7; |
890ca9ae HY |
522 | |
523 | u64 mcg_cap; | |
524 | u64 mcg_status; | |
525 | u64 mcg_ctl; | |
526 | u64 *mce_banks; | |
94fe45da | 527 | |
bebb106a XG |
528 | /* Cache MMIO info */ |
529 | u64 mmio_gva; | |
530 | unsigned access; | |
531 | gfn_t mmio_gfn; | |
56f17dd3 | 532 | u64 mmio_gen; |
bebb106a | 533 | |
f5132b01 GN |
534 | struct kvm_pmu pmu; |
535 | ||
94fe45da | 536 | /* used for guest single stepping over the given code position */ |
94fe45da | 537 | unsigned long singlestep_rip; |
f92653ee | 538 | |
e83d5887 | 539 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
540 | |
541 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 542 | |
1cb3f3ae XG |
543 | unsigned long last_retry_eip; |
544 | unsigned long last_retry_addr; | |
545 | ||
af585b92 GN |
546 | struct { |
547 | bool halted; | |
548 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
549 | struct gfn_to_hva_cache data; |
550 | u64 msr_val; | |
7c90705b | 551 | u32 id; |
6adba527 | 552 | bool send_user_only; |
af585b92 | 553 | } apf; |
2b036c6b BO |
554 | |
555 | /* OSVW MSRs (AMD only) */ | |
556 | struct { | |
557 | u64 length; | |
558 | u64 status; | |
559 | } osvw; | |
ae7a2a3f MT |
560 | |
561 | struct { | |
562 | u64 msr_val; | |
563 | struct gfn_to_hva_cache data; | |
564 | } pv_eoi; | |
93c05d3e XG |
565 | |
566 | /* | |
567 | * Indicate whether the access faults on its page table in guest | |
568 | * which is set when fix page fault and used to detect unhandeable | |
569 | * instruction. | |
570 | */ | |
571 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
572 | |
573 | /* set at EPT violation at this point */ | |
574 | unsigned long exit_qualification; | |
6aef266c SV |
575 | |
576 | /* pv related host specific info */ | |
577 | struct { | |
578 | bool pv_unhalted; | |
579 | } pv; | |
7543a635 SR |
580 | |
581 | int pending_ioapic_eoi; | |
1c1a9ce9 | 582 | int pending_external_vector; |
34c16eec ZX |
583 | }; |
584 | ||
db3fe4eb | 585 | struct kvm_lpage_info { |
db3fe4eb TY |
586 | int write_count; |
587 | }; | |
588 | ||
589 | struct kvm_arch_memory_slot { | |
d89cc617 | 590 | unsigned long *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
591 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
592 | }; | |
593 | ||
3548a259 RK |
594 | /* |
595 | * We use as the mode the number of bits allocated in the LDR for the | |
596 | * logical processor ID. It happens that these are all powers of two. | |
597 | * This makes it is very easy to detect cases where the APICs are | |
598 | * configured for multiple modes; in that case, we cannot use the map and | |
599 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
600 | */ | |
601 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
602 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
603 | #define KVM_APIC_MODE_X2APIC 16 | |
604 | ||
1e08ec4a GN |
605 | struct kvm_apic_map { |
606 | struct rcu_head rcu; | |
3548a259 | 607 | u8 mode; |
1e08ec4a GN |
608 | struct kvm_lapic *phys_map[256]; |
609 | /* first index is cluster id second is cpu id in a cluster */ | |
610 | struct kvm_lapic *logical_map[16][16]; | |
611 | }; | |
612 | ||
e83d5887 AS |
613 | /* Hyper-V emulation context */ |
614 | struct kvm_hv { | |
615 | u64 hv_guest_os_id; | |
616 | u64 hv_hypercall; | |
617 | u64 hv_tsc_page; | |
e7d9513b AS |
618 | |
619 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
620 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
621 | u64 hv_crash_ctl; | |
e83d5887 AS |
622 | }; |
623 | ||
fef9cce0 | 624 | struct kvm_arch { |
49d5ca26 | 625 | unsigned int n_used_mmu_pages; |
f05e70ac | 626 | unsigned int n_requested_mmu_pages; |
39de71ec | 627 | unsigned int n_max_mmu_pages; |
332b207d | 628 | unsigned int indirect_shadow_pages; |
5304b8d3 | 629 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
630 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
631 | /* | |
632 | * Hash table of struct kvm_mmu_page. | |
633 | */ | |
634 | struct list_head active_mmu_pages; | |
365c8868 XG |
635 | struct list_head zapped_obsolete_pages; |
636 | ||
4d5c5d0f | 637 | struct list_head assigned_dev_head; |
19de40a8 | 638 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 639 | bool iommu_noncoherent; |
e0f0bbc5 AW |
640 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
641 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
642 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
643 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
644 | struct kvm_pic *vpic; |
645 | struct kvm_ioapic *vioapic; | |
7837699f | 646 | struct kvm_pit *vpit; |
42720138 | 647 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
648 | struct mutex apic_map_lock; |
649 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 650 | |
bfc6d222 | 651 | unsigned int tss_addr; |
c24ae0dc | 652 | bool apic_access_page_done; |
18068523 GOC |
653 | |
654 | gpa_t wall_clock; | |
b7ebfb05 | 655 | |
b7ebfb05 | 656 | bool ept_identity_pagetable_done; |
b927a3ce | 657 | gpa_t ept_identity_map_addr; |
5550af4d SY |
658 | |
659 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 660 | s64 kvmclock_offset; |
038f8c11 | 661 | raw_spinlock_t tsc_write_lock; |
f38e098f | 662 | u64 last_tsc_nsec; |
f38e098f | 663 | u64 last_tsc_write; |
5d3cb0f6 | 664 | u32 last_tsc_khz; |
e26101b1 ZA |
665 | u64 cur_tsc_nsec; |
666 | u64 cur_tsc_write; | |
667 | u64 cur_tsc_offset; | |
0d3da0d2 | 668 | u64 cur_tsc_generation; |
b48aa97e | 669 | int nr_vcpus_matched_tsc; |
ffde22ac | 670 | |
d828199e MT |
671 | spinlock_t pvclock_gtod_sync_lock; |
672 | bool use_master_clock; | |
673 | u64 master_kernel_ns; | |
674 | cycle_t master_cycle_now; | |
7e44e449 | 675 | struct delayed_work kvmclock_update_work; |
332967a3 | 676 | struct delayed_work kvmclock_sync_work; |
d828199e | 677 | |
ffde22ac | 678 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 679 | |
6ef768fa PB |
680 | /* reads protected by irq_srcu, writes by irq_lock */ |
681 | struct hlist_head mask_notifier_list; | |
682 | ||
e83d5887 | 683 | struct kvm_hv hyperv; |
b034cf01 XG |
684 | |
685 | #ifdef CONFIG_KVM_MMU_AUDIT | |
686 | int audit_point; | |
687 | #endif | |
54750f2c MT |
688 | |
689 | bool boot_vcpu_runs_old_kvmclock; | |
d71ba788 | 690 | u32 bsp_vcpu_id; |
90de4a18 NA |
691 | |
692 | u64 disabled_quirks; | |
49df6397 SR |
693 | |
694 | bool irqchip_split; | |
b053b2ae | 695 | u8 nr_reserved_ioapic_pins; |
d69fb81f ZX |
696 | }; |
697 | ||
0711456c ZX |
698 | struct kvm_vm_stat { |
699 | u32 mmu_shadow_zapped; | |
700 | u32 mmu_pte_write; | |
701 | u32 mmu_pte_updated; | |
702 | u32 mmu_pde_zapped; | |
703 | u32 mmu_flooded; | |
704 | u32 mmu_recycled; | |
dfc5aa00 | 705 | u32 mmu_cache_miss; |
4731d4c7 | 706 | u32 mmu_unsync; |
0711456c | 707 | u32 remote_tlb_flush; |
05da4558 | 708 | u32 lpages; |
0711456c ZX |
709 | }; |
710 | ||
77b4c255 ZX |
711 | struct kvm_vcpu_stat { |
712 | u32 pf_fixed; | |
713 | u32 pf_guest; | |
714 | u32 tlb_flush; | |
715 | u32 invlpg; | |
716 | ||
717 | u32 exits; | |
718 | u32 io_exits; | |
719 | u32 mmio_exits; | |
720 | u32 signal_exits; | |
721 | u32 irq_window_exits; | |
f08864b4 | 722 | u32 nmi_window_exits; |
77b4c255 | 723 | u32 halt_exits; |
f7819512 | 724 | u32 halt_successful_poll; |
62bea5bf | 725 | u32 halt_attempted_poll; |
77b4c255 ZX |
726 | u32 halt_wakeup; |
727 | u32 request_irq_exits; | |
728 | u32 irq_exits; | |
729 | u32 host_state_reload; | |
730 | u32 efer_reload; | |
731 | u32 fpu_reload; | |
732 | u32 insn_emulation; | |
733 | u32 insn_emulation_fail; | |
f11c3a8d | 734 | u32 hypercalls; |
fa89a817 | 735 | u32 irq_injections; |
c4abb7c9 | 736 | u32 nmi_injections; |
77b4c255 | 737 | }; |
ad312c7c | 738 | |
8a76d7f2 JR |
739 | struct x86_instruction_info; |
740 | ||
8fe8ab46 WA |
741 | struct msr_data { |
742 | bool host_initiated; | |
743 | u32 index; | |
744 | u64 data; | |
745 | }; | |
746 | ||
cb5281a5 PB |
747 | struct kvm_lapic_irq { |
748 | u32 vector; | |
b7cb2231 PB |
749 | u16 delivery_mode; |
750 | u16 dest_mode; | |
751 | bool level; | |
752 | u16 trig_mode; | |
cb5281a5 PB |
753 | u32 shorthand; |
754 | u32 dest_id; | |
93bbf0b8 | 755 | bool msi_redir_hint; |
cb5281a5 PB |
756 | }; |
757 | ||
ea4a5ff8 ZX |
758 | struct kvm_x86_ops { |
759 | int (*cpu_has_kvm_support)(void); /* __init */ | |
760 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
761 | int (*hardware_enable)(void); |
762 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
763 | void (*check_processor_compatibility)(void *rtn); |
764 | int (*hardware_setup)(void); /* __init */ | |
765 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 766 | bool (*cpu_has_accelerated_tpr)(void); |
6d396b55 | 767 | bool (*cpu_has_high_real_mode_segbase)(void); |
0e851880 | 768 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
769 | |
770 | /* Create, but do not attach this VCPU */ | |
771 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
772 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 773 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
774 | |
775 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
776 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
777 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 778 | |
c8639010 | 779 | void (*update_db_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 780 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 781 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
782 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
783 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
784 | struct kvm_segment *var, int seg); | |
2e4d2653 | 785 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
786 | void (*set_segment)(struct kvm_vcpu *vcpu, |
787 | struct kvm_segment *var, int seg); | |
788 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 789 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 790 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
791 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
792 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
793 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 794 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 795 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
796 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
797 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
798 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
799 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
800 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
801 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 802 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 803 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 804 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
805 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
806 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
0fdd74f7 | 807 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 808 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
809 | |
810 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 811 | |
851ba692 AK |
812 | void (*run)(struct kvm_vcpu *vcpu); |
813 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 814 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 815 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 816 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
817 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
818 | unsigned char *hypercall_addr); | |
66fd3f7f | 819 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 820 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 821 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
822 | bool has_error_code, u32 error_code, |
823 | bool reinject); | |
b463a6f7 | 824 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 825 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 826 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
827 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
828 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
829 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
830 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 831 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
d50ab6c1 | 832 | int (*cpu_uses_apicv)(struct kvm_vcpu *vcpu); |
c7c9c56c YZ |
833 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
834 | void (*hwapic_isr_update)(struct kvm *kvm, int isr); | |
3bb345f3 | 835 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu); |
8d14695f | 836 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
4256f43f | 837 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d YZ |
838 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
839 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 840 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 841 | int (*get_tdp_level)(void); |
4b12f0de | 842 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 843 | int (*get_lpage_level)(void); |
4e47c7a6 | 844 | bool (*rdtscp_supported)(void); |
ad756a16 | 845 | bool (*invpcid_supported)(void); |
f1e2b260 | 846 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 847 | |
1c97f0a0 JR |
848 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
849 | ||
d4330ef2 JR |
850 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
851 | ||
f5f48ee1 SY |
852 | bool (*has_wbinvd_exit)(void); |
853 | ||
cc578287 | 854 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
ba904635 | 855 | u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
856 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
857 | ||
857e4099 | 858 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
886b470c | 859 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc); |
857e4099 | 860 | |
586f9607 | 861 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
862 | |
863 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
864 | struct x86_instruction_info *info, | |
865 | enum x86_intercept_stage stage); | |
a547c6db | 866 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 867 | bool (*mpx_supported)(void); |
55412b2e | 868 | bool (*xsaves_supported)(void); |
b6b8a145 JK |
869 | |
870 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ae97a3b8 RK |
871 | |
872 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
873 | |
874 | /* | |
875 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
876 | * be valid if the specific arch has hardware-accelerated dirty logging | |
877 | * mechanism. Currently only for PML on VMX. | |
878 | * | |
879 | * - slot_enable_log_dirty: | |
880 | * called when enabling log dirty mode for the slot. | |
881 | * - slot_disable_log_dirty: | |
882 | * called when disabling log dirty mode for the slot. | |
883 | * also called when slot is created with log dirty disabled. | |
884 | * - flush_log_dirty: | |
885 | * called before reporting dirty_bitmap to userspace. | |
886 | * - enable_log_dirty_pt_masked: | |
887 | * called when reenabling log dirty for the GFNs in the mask after | |
888 | * corresponding bits are cleared in slot->dirty_bitmap. | |
889 | */ | |
890 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
891 | struct kvm_memory_slot *slot); | |
892 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
893 | struct kvm_memory_slot *slot); | |
894 | void (*flush_log_dirty)(struct kvm *kvm); | |
895 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
896 | struct kvm_memory_slot *slot, | |
897 | gfn_t offset, unsigned long mask); | |
25462f7f WH |
898 | /* pmu operations of sub-arch */ |
899 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 FW |
900 | |
901 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, | |
902 | uint32_t guest_irq, bool set); | |
ea4a5ff8 ZX |
903 | }; |
904 | ||
af585b92 | 905 | struct kvm_arch_async_pf { |
7c90705b | 906 | u32 token; |
af585b92 | 907 | gfn_t gfn; |
fb67e14f | 908 | unsigned long cr3; |
c4806acd | 909 | bool direct_map; |
af585b92 GN |
910 | }; |
911 | ||
97896d04 ZX |
912 | extern struct kvm_x86_ops *kvm_x86_ops; |
913 | ||
f1e2b260 MT |
914 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
915 | s64 adjustment) | |
916 | { | |
917 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
918 | } | |
919 | ||
920 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
921 | { | |
922 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
923 | } | |
924 | ||
54f1585a ZX |
925 | int kvm_mmu_module_init(void); |
926 | void kvm_mmu_module_exit(void); | |
927 | ||
928 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
929 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 930 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
7b52345e | 931 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 932 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a | 933 | |
8a3c1a33 | 934 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
935 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
936 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 937 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 938 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
939 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
940 | struct kvm_memory_slot *memslot); | |
941 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
942 | struct kvm_memory_slot *memslot); | |
943 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
944 | struct kvm_memory_slot *memslot); | |
945 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
946 | struct kvm_memory_slot *slot, | |
947 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 948 | void kvm_mmu_zap_all(struct kvm *kvm); |
54bf36aa | 949 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); |
3ad82a7e | 950 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
951 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
952 | ||
ff03a073 | 953 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 954 | |
3200f405 | 955 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 956 | const void *val, int bytes); |
2f333bcb | 957 | |
6ef768fa PB |
958 | struct kvm_irq_mask_notifier { |
959 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
960 | int irq; | |
961 | struct hlist_node link; | |
962 | }; | |
963 | ||
964 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
965 | struct kvm_irq_mask_notifier *kimn); | |
966 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
967 | struct kvm_irq_mask_notifier *kimn); | |
968 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
969 | bool mask); | |
970 | ||
2f333bcb | 971 | extern bool tdp_enabled; |
9f811285 | 972 | |
a3e06bbe LJ |
973 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
974 | ||
92a1f12d JR |
975 | /* control of guest tsc rate supported? */ |
976 | extern bool kvm_has_tsc_control; | |
977 | /* minimum supported tsc_khz for guests */ | |
978 | extern u32 kvm_min_guest_tsc_khz; | |
979 | /* maximum supported tsc_khz for guests */ | |
980 | extern u32 kvm_max_guest_tsc_khz; | |
981 | ||
54f1585a | 982 | enum emulation_result { |
ac0a48c3 PB |
983 | EMULATE_DONE, /* no further processing */ |
984 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
985 | EMULATE_FAIL, /* can't emulate this instruction */ |
986 | }; | |
987 | ||
571008da SY |
988 | #define EMULTYPE_NO_DECODE (1 << 0) |
989 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 990 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 991 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 992 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
993 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
994 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
995 | |
996 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
997 | int emulation_type) | |
998 | { | |
dc25e89e | 999 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
1000 | } |
1001 | ||
f2b4b7dd | 1002 | void kvm_enable_efer_bits(u64); |
384bb783 | 1003 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 1004 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1005 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
1006 | |
1007 | struct x86_emulate_ctxt; | |
1008 | ||
cf8f70bf | 1009 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
1010 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
1011 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
5cb56059 | 1012 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1013 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1014 | |
3e6e0aab | 1015 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1016 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1017 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1018 | |
7f3d35fd KW |
1019 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1020 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1021 | |
49a9b07e | 1022 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1023 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1024 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1025 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1026 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1027 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1028 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1029 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1030 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1031 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1032 | |
609e36d3 | 1033 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1034 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1035 | |
91586a3b JK |
1036 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1037 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1038 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1039 | |
298101da AK |
1040 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1041 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1042 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1043 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1044 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1045 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1046 | gfn_t gfn, void *data, int offset, int len, | |
1047 | u32 access); | |
0a79b009 | 1048 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1049 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1050 | |
1a577b72 MT |
1051 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1052 | int irq_source_id, int level) | |
1053 | { | |
1054 | /* Logical OR for level trig interrupt */ | |
1055 | if (level) | |
1056 | __set_bit(irq_source_id, irq_state); | |
1057 | else | |
1058 | __clear_bit(irq_source_id, irq_state); | |
1059 | ||
1060 | return !!(*irq_state); | |
1061 | } | |
1062 | ||
1063 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1064 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1065 | |
3419ffc8 SY |
1066 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1067 | ||
54f1585a | 1068 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 1069 | const u8 *new, int bytes); |
1cb3f3ae | 1070 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1071 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1072 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1073 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1074 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1075 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
54987b7a PB |
1076 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1077 | struct x86_exception *exception); | |
ab9ae313 AK |
1078 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1079 | struct x86_exception *exception); | |
1080 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1081 | struct x86_exception *exception); | |
1082 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1083 | struct x86_exception *exception); | |
1084 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1085 | struct x86_exception *exception); | |
54f1585a ZX |
1086 | |
1087 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
1088 | ||
dc25e89e AP |
1089 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
1090 | void *insn, int insn_len); | |
a7052897 | 1091 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 1092 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 1093 | |
18552672 | 1094 | void kvm_enable_tdp(void); |
5f4cb662 | 1095 | void kvm_disable_tdp(void); |
18552672 | 1096 | |
54987b7a PB |
1097 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1098 | struct x86_exception *exception) | |
e459e322 XG |
1099 | { |
1100 | return gpa; | |
1101 | } | |
1102 | ||
ec6d273d ZX |
1103 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1104 | { | |
1105 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1106 | ||
1107 | return (struct kvm_mmu_page *)page_private(page); | |
1108 | } | |
1109 | ||
d6e88aec | 1110 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1111 | { |
1112 | u16 ldt; | |
1113 | asm("sldt %0" : "=g"(ldt)); | |
1114 | return ldt; | |
1115 | } | |
1116 | ||
d6e88aec | 1117 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1118 | { |
1119 | asm("lldt %0" : : "rm"(sel)); | |
1120 | } | |
ec6d273d | 1121 | |
ec6d273d ZX |
1122 | #ifdef CONFIG_X86_64 |
1123 | static inline unsigned long read_msr(unsigned long msr) | |
1124 | { | |
1125 | u64 value; | |
1126 | ||
1127 | rdmsrl(msr, value); | |
1128 | return value; | |
1129 | } | |
1130 | #endif | |
1131 | ||
ec6d273d ZX |
1132 | static inline u32 get_rdx_init_val(void) |
1133 | { | |
1134 | return 0x600; /* P6 family */ | |
1135 | } | |
1136 | ||
c1a5d4f9 AK |
1137 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1138 | { | |
1139 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1140 | } | |
1141 | ||
854e8bb1 NA |
1142 | static inline u64 get_canonical(u64 la) |
1143 | { | |
1144 | return ((int64_t)la << 16) >> 16; | |
1145 | } | |
1146 | ||
1147 | static inline bool is_noncanonical_address(u64 la) | |
1148 | { | |
1149 | #ifdef CONFIG_X86_64 | |
1150 | return get_canonical(la) != la; | |
1151 | #else | |
1152 | return false; | |
1153 | #endif | |
1154 | } | |
1155 | ||
ec6d273d ZX |
1156 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1157 | #define TSS_BASE_SIZE 0x68 | |
1158 | #define TSS_IOPB_SIZE (65536 / 8) | |
1159 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1160 | #define RMODE_TSS_SIZE \ |
1161 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1162 | |
37817f29 IE |
1163 | enum { |
1164 | TASK_SWITCH_CALL = 0, | |
1165 | TASK_SWITCH_IRET = 1, | |
1166 | TASK_SWITCH_JMP = 2, | |
1167 | TASK_SWITCH_GATE = 3, | |
1168 | }; | |
1169 | ||
1371d904 | 1170 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1171 | #define HF_HIF_MASK (1 << 1) |
1172 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1173 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1174 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1175 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1176 | #define HF_SMM_MASK (1 << 6) |
1177 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1178 | |
699023e2 PB |
1179 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1180 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1181 | ||
1182 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1183 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1184 | |
4ecac3fd AK |
1185 | /* |
1186 | * Hardware virtualization extension instructions may fault if a | |
1187 | * reboot turns off virtualization while processes are running. | |
1188 | * Trap the fault and ignore the instruction if that happens. | |
1189 | */ | |
b7c4145b | 1190 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1191 | |
5e520e62 | 1192 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1193 | "666: " insn "\n\t" \ |
b7c4145b | 1194 | "668: \n\t" \ |
18b13e54 | 1195 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1196 | "667: \n\t" \ |
5e520e62 | 1197 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1198 | "cmpb $0, kvm_rebooting \n\t" \ |
1199 | "jne 668b \n\t" \ | |
8ceed347 | 1200 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1201 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1202 | ".popsection \n\t" \ |
3ee89722 | 1203 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1204 | |
5e520e62 AK |
1205 | #define __kvm_handle_fault_on_reboot(insn) \ |
1206 | ____kvm_handle_fault_on_reboot(insn, "") | |
1207 | ||
e930bffe AA |
1208 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1209 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1210 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1211 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1212 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1213 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1214 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1215 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1216 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1217 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1218 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1219 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
fe71557a TC |
1220 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
1221 | unsigned long address); | |
e930bffe | 1222 | |
18863bdd | 1223 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1224 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1225 | |
82b32774 | 1226 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1227 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1228 | ||
af585b92 GN |
1229 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1230 | struct kvm_async_pf *work); | |
1231 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1232 | struct kvm_async_pf *work); | |
56028d08 GN |
1233 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1234 | struct kvm_async_pf *work); | |
7c90705b | 1235 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1236 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1237 | ||
db8fcefa AP |
1238 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
1239 | ||
f5132b01 GN |
1240 | int kvm_is_in_guest(void); |
1241 | ||
9da0e4d5 PB |
1242 | int __x86_set_memory_region(struct kvm *kvm, |
1243 | const struct kvm_userspace_memory_region *mem); | |
1244 | int x86_set_memory_region(struct kvm *kvm, | |
1245 | const struct kvm_userspace_memory_region *mem); | |
d71ba788 PB |
1246 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1247 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1248 | |
8feb4a04 FW |
1249 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1250 | struct kvm_vcpu **dest_vcpu); | |
1251 | ||
d84f1e07 FW |
1252 | void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e, |
1253 | struct kvm_lapic_irq *irq); | |
1965aae3 | 1254 | #endif /* _ASM_X86_KVM_HOST_H */ |