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20c8ccb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
a656c8ef | 2 | /* |
043405e1 CO |
3 | * Kernel-based Virtual Machine driver for Linux |
4 | * | |
5 | * This header defines architecture specific interfaces, x86 version | |
043405e1 CO |
6 | */ |
7 | ||
1965aae3 PA |
8 | #ifndef _ASM_X86_KVM_HOST_H |
9 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 10 | |
34c16eec ZX |
11 | #include <linux/types.h> |
12 | #include <linux/mm.h> | |
e930bffe | 13 | #include <linux/mmu_notifier.h> |
229456fc | 14 | #include <linux/tracepoint.h> |
f5f48ee1 | 15 | #include <linux/cpumask.h> |
f5132b01 | 16 | #include <linux/irq_work.h> |
447ae316 | 17 | #include <linux/irq.h> |
34c16eec ZX |
18 | |
19 | #include <linux/kvm.h> | |
20 | #include <linux/kvm_para.h> | |
edf88417 | 21 | #include <linux/kvm_types.h> |
f5132b01 | 22 | #include <linux/perf_event.h> |
d828199e MT |
23 | #include <linux/pvclock_gtod.h> |
24 | #include <linux/clocksource.h> | |
87276880 | 25 | #include <linux/irqbypass.h> |
5c919412 | 26 | #include <linux/hyperv.h> |
34c16eec | 27 | |
7d669f50 | 28 | #include <asm/apic.h> |
50d0a0f9 | 29 | #include <asm/pvclock-abi.h> |
e01a1b57 | 30 | #include <asm/desc.h> |
0bed3b56 | 31 | #include <asm/mtrr.h> |
9962d032 | 32 | #include <asm/msr-index.h> |
3ee89722 | 33 | #include <asm/asm.h> |
21ebbeda | 34 | #include <asm/kvm_page_track.h> |
95c7b77d | 35 | #include <asm/kvm_vcpu_regs.h> |
5a485803 | 36 | #include <asm/hyperv-tlfs.h> |
e01a1b57 | 37 | |
741cbbae PB |
38 | #define __KVM_HAVE_ARCH_VCPU_DEBUGFS |
39 | ||
682f732e | 40 | #define KVM_MAX_VCPUS 288 |
757883de | 41 | #define KVM_SOFT_MAX_VCPUS 240 |
af1bae54 | 42 | #define KVM_MAX_VCPU_ID 1023 |
1d4e7e3c | 43 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
44 | /* memory slots that are not exposed to userspace */ |
45 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 46 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 47 | |
b401ee0b | 48 | #define KVM_HALT_POLL_NS_DEFAULT 200000 |
69a9f69b | 49 | |
8175e5b7 AG |
50 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
51 | ||
3c9bd400 JZ |
52 | #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ |
53 | KVM_DIRTY_LOG_INITIALLY_SET) | |
54 | ||
2860c4b1 | 55 | /* x86-specific vcpu->requests bit members */ |
2387149e AJ |
56 | #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) |
57 | #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) | |
58 | #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) | |
59 | #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) | |
60 | #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) | |
727a7e27 | 61 | #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5) |
2387149e AJ |
62 | #define KVM_REQ_EVENT KVM_ARCH_REQ(6) |
63 | #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) | |
64 | #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) | |
65 | #define KVM_REQ_NMI KVM_ARCH_REQ(9) | |
66 | #define KVM_REQ_PMU KVM_ARCH_REQ(10) | |
67 | #define KVM_REQ_PMI KVM_ARCH_REQ(11) | |
68 | #define KVM_REQ_SMI KVM_ARCH_REQ(12) | |
69 | #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) | |
70 | #define KVM_REQ_MCLOCK_INPROGRESS \ | |
71 | KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
72 | #define KVM_REQ_SCAN_IOAPIC \ | |
73 | KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
74 | #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) | |
75 | #define KVM_REQ_APIC_PAGE_RELOAD \ | |
76 | KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
77 | #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) | |
78 | #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) | |
79 | #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) | |
80 | #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) | |
81 | #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) | |
e40ff1d6 | 82 | #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) |
729c15c2 | 83 | #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24) |
8df14af4 SS |
84 | #define KVM_REQ_APICV_UPDATE \ |
85 | KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
eeeb4f67 | 86 | #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26) |
0baedd79 | 87 | #define KVM_REQ_HV_TLB_FLUSH \ |
eeeb4f67 | 88 | KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_NO_WAKEUP) |
557a961a | 89 | #define KVM_REQ_APF_READY KVM_ARCH_REQ(28) |
1a155254 | 90 | #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29) |
2860c4b1 | 91 | |
cfec82cb JR |
92 | #define CR0_RESERVED_BITS \ |
93 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
94 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
95 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
96 | ||
cfec82cb JR |
97 | #define CR4_RESERVED_BITS \ |
98 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
99 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 100 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 101 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
fd8cb433 | 102 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ |
ae3e61e1 | 103 | | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) |
cfec82cb JR |
104 | |
105 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
106 | ||
107 | ||
cd6e8f87 | 108 | |
cd6e8f87 | 109 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
110 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
111 | ||
cd6e8f87 ZX |
112 | #define UNMAPPED_GVA (~(gpa_t)0) |
113 | ||
ec04b260 | 114 | /* KVM Hugepage definitions for x86 */ |
3bae0459 SC |
115 | #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G |
116 | #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1) | |
82855413 JR |
117 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
118 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
119 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
120 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
121 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 122 | |
6d9d41e5 CD |
123 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
124 | { | |
3bae0459 | 125 | /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ |
6d9d41e5 CD |
126 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
127 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
128 | } | |
129 | ||
d657a98e | 130 | #define KVM_PERMILLE_MMU_PAGES 20 |
bc8a3d89 | 131 | #define KVM_MIN_ALLOC_MMU_PAGES 64UL |
114df303 | 132 | #define KVM_MMU_HASH_SHIFT 12 |
1ae0a13d | 133 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) |
d657a98e ZX |
134 | #define KVM_MIN_FREE_MMU_PAGES 5 |
135 | #define KVM_REFILL_PAGES 25 | |
3f4e3eb4 | 136 | #define KVM_MAX_CPUID_ENTRIES 256 |
0bed3b56 | 137 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 138 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 139 | |
af585b92 GN |
140 | #define ASYNC_PF_PER_VCPU 64 |
141 | ||
5fdbf976 | 142 | enum kvm_reg { |
95c7b77d SC |
143 | VCPU_REGS_RAX = __VCPU_REGS_RAX, |
144 | VCPU_REGS_RCX = __VCPU_REGS_RCX, | |
145 | VCPU_REGS_RDX = __VCPU_REGS_RDX, | |
146 | VCPU_REGS_RBX = __VCPU_REGS_RBX, | |
147 | VCPU_REGS_RSP = __VCPU_REGS_RSP, | |
148 | VCPU_REGS_RBP = __VCPU_REGS_RBP, | |
149 | VCPU_REGS_RSI = __VCPU_REGS_RSI, | |
150 | VCPU_REGS_RDI = __VCPU_REGS_RDI, | |
2b3ccfa0 | 151 | #ifdef CONFIG_X86_64 |
95c7b77d SC |
152 | VCPU_REGS_R8 = __VCPU_REGS_R8, |
153 | VCPU_REGS_R9 = __VCPU_REGS_R9, | |
154 | VCPU_REGS_R10 = __VCPU_REGS_R10, | |
155 | VCPU_REGS_R11 = __VCPU_REGS_R11, | |
156 | VCPU_REGS_R12 = __VCPU_REGS_R12, | |
157 | VCPU_REGS_R13 = __VCPU_REGS_R13, | |
158 | VCPU_REGS_R14 = __VCPU_REGS_R14, | |
159 | VCPU_REGS_R15 = __VCPU_REGS_R15, | |
2b3ccfa0 | 160 | #endif |
5fdbf976 | 161 | VCPU_REGS_RIP, |
f8845541 | 162 | NR_VCPU_REGS, |
2b3ccfa0 | 163 | |
6de4f3ad | 164 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, |
bd31fe49 | 165 | VCPU_EXREG_CR0, |
aff48baa | 166 | VCPU_EXREG_CR3, |
f98c1e77 | 167 | VCPU_EXREG_CR4, |
6de12732 | 168 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 169 | VCPU_EXREG_SEGMENTS, |
5addc235 | 170 | VCPU_EXREG_EXIT_INFO_1, |
87915858 | 171 | VCPU_EXREG_EXIT_INFO_2, |
6de4f3ad AK |
172 | }; |
173 | ||
2b3ccfa0 | 174 | enum { |
81609e3e | 175 | VCPU_SREG_ES, |
2b3ccfa0 | 176 | VCPU_SREG_CS, |
81609e3e | 177 | VCPU_SREG_SS, |
2b3ccfa0 | 178 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
179 | VCPU_SREG_FS, |
180 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
181 | VCPU_SREG_TR, |
182 | VCPU_SREG_LDTR, | |
183 | }; | |
184 | ||
1e9e2622 WL |
185 | enum exit_fastpath_completion { |
186 | EXIT_FASTPATH_NONE, | |
404d5d7b WL |
187 | EXIT_FASTPATH_REENTER_GUEST, |
188 | EXIT_FASTPATH_EXIT_HANDLED, | |
1e9e2622 | 189 | }; |
404d5d7b | 190 | typedef enum exit_fastpath_completion fastpath_t; |
1e9e2622 | 191 | |
2f728d66 SC |
192 | struct x86_emulate_ctxt; |
193 | struct x86_exception; | |
194 | enum x86_intercept; | |
195 | enum x86_intercept_stage; | |
2b3ccfa0 | 196 | |
42dbaa5a JK |
197 | #define KVM_NR_DB_REGS 4 |
198 | ||
199 | #define DR6_BD (1 << 13) | |
200 | #define DR6_BS (1 << 14) | |
cfb634fe | 201 | #define DR6_BT (1 << 15) |
6f43ed01 NA |
202 | #define DR6_RTM (1 << 16) |
203 | #define DR6_FIXED_1 0xfffe0ff0 | |
204 | #define DR6_INIT 0xffff0ff0 | |
205 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
206 | |
207 | #define DR7_BP_EN_MASK 0x000000ff | |
208 | #define DR7_GE (1 << 9) | |
209 | #define DR7_GD (1 << 13) | |
210 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 211 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 212 | |
c205fb7d NA |
213 | #define PFERR_PRESENT_BIT 0 |
214 | #define PFERR_WRITE_BIT 1 | |
215 | #define PFERR_USER_BIT 2 | |
216 | #define PFERR_RSVD_BIT 3 | |
217 | #define PFERR_FETCH_BIT 4 | |
be94f6b7 | 218 | #define PFERR_PK_BIT 5 |
14727754 TL |
219 | #define PFERR_GUEST_FINAL_BIT 32 |
220 | #define PFERR_GUEST_PAGE_BIT 33 | |
c205fb7d NA |
221 | |
222 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
223 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
224 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
225 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
226 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
be94f6b7 | 227 | #define PFERR_PK_MASK (1U << PFERR_PK_BIT) |
14727754 TL |
228 | #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) |
229 | #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) | |
230 | ||
231 | #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ | |
14727754 TL |
232 | PFERR_WRITE_MASK | \ |
233 | PFERR_PRESENT_MASK) | |
c205fb7d | 234 | |
41383771 GN |
235 | /* apic attention bits */ |
236 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
237 | /* |
238 | * The following bit is set with PV-EOI, unset on EOI. | |
239 | * We detect PV-EOI changes by guest by comparing | |
240 | * this bit with PV-EOI in guest memory. | |
241 | * See the implementation in apic_update_pv_eoi. | |
242 | */ | |
243 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 244 | |
d84f1e07 FW |
245 | struct kvm_kernel_irq_routing_entry; |
246 | ||
21ebbeda XG |
247 | /* |
248 | * the pages used as guest page table on soft mmu are tracked by | |
249 | * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used | |
250 | * by indirect shadow page can not be more than 15 bits. | |
251 | * | |
47c42e6b | 252 | * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, |
21ebbeda XG |
253 | * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. |
254 | */ | |
d657a98e | 255 | union kvm_mmu_page_role { |
36d9594d | 256 | u32 word; |
d657a98e | 257 | struct { |
7d76b4d3 | 258 | unsigned level:4; |
47c42e6b | 259 | unsigned gpte_is_8_bytes:1; |
7d76b4d3 | 260 | unsigned quadrant:2; |
f6e2c02b | 261 | unsigned direct:1; |
7d76b4d3 | 262 | unsigned access:3; |
2e53d63a | 263 | unsigned invalid:1; |
9645bb56 | 264 | unsigned nxe:1; |
3dbe1415 | 265 | unsigned cr0_wp:1; |
411c588d | 266 | unsigned smep_andnot_wp:1; |
0be0226f | 267 | unsigned smap_andnot_wp:1; |
ac8d57e5 | 268 | unsigned ad_disabled:1; |
1313cc2b JM |
269 | unsigned guest_mode:1; |
270 | unsigned :6; | |
699023e2 PB |
271 | |
272 | /* | |
273 | * This is left at the top of the word so that | |
274 | * kvm_memslots_for_spte_role can extract it with a | |
275 | * simple shift. While there is room, give it a whole | |
276 | * byte so it is also faster to load it from memory. | |
277 | */ | |
278 | unsigned smm:8; | |
d657a98e ZX |
279 | }; |
280 | }; | |
281 | ||
36d9594d | 282 | union kvm_mmu_extended_role { |
a336282d VK |
283 | /* |
284 | * This structure complements kvm_mmu_page_role caching everything needed for | |
285 | * MMU configuration. If nothing in both these structures changed, MMU | |
286 | * re-configuration can be skipped. @valid bit is set on first usage so we don't | |
287 | * treat all-zero structure as valid data. | |
288 | */ | |
36d9594d | 289 | u32 word; |
a336282d VK |
290 | struct { |
291 | unsigned int valid:1; | |
292 | unsigned int execonly:1; | |
7dcd5755 | 293 | unsigned int cr0_pg:1; |
0699c64a | 294 | unsigned int cr4_pae:1; |
a336282d VK |
295 | unsigned int cr4_pse:1; |
296 | unsigned int cr4_pke:1; | |
297 | unsigned int cr4_smap:1; | |
298 | unsigned int cr4_smep:1; | |
de3ccd26 | 299 | unsigned int maxphyaddr:6; |
a336282d | 300 | }; |
36d9594d VK |
301 | }; |
302 | ||
303 | union kvm_mmu_role { | |
304 | u64 as_u64; | |
305 | struct { | |
306 | union kvm_mmu_page_role base; | |
307 | union kvm_mmu_extended_role ext; | |
308 | }; | |
309 | }; | |
310 | ||
018aabb5 TY |
311 | struct kvm_rmap_head { |
312 | unsigned long val; | |
313 | }; | |
314 | ||
1c08364c | 315 | struct kvm_pio_request { |
45def77e | 316 | unsigned long linear_rip; |
1c08364c | 317 | unsigned long count; |
1c08364c AK |
318 | int in; |
319 | int port; | |
320 | int size; | |
1c08364c AK |
321 | }; |
322 | ||
855feb67 | 323 | #define PT64_ROOT_MAX_LEVEL 5 |
2a7266a8 | 324 | |
a0a64f50 | 325 | struct rsvd_bits_validate { |
2a7266a8 | 326 | u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; |
a0a64f50 XG |
327 | u64 bad_mt_xwr; |
328 | }; | |
329 | ||
7c390d35 | 330 | struct kvm_mmu_root_info { |
be01e8e2 | 331 | gpa_t pgd; |
7c390d35 JS |
332 | hpa_t hpa; |
333 | }; | |
334 | ||
335 | #define KVM_MMU_ROOT_INFO_INVALID \ | |
be01e8e2 | 336 | ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE }) |
7c390d35 | 337 | |
b94742c9 JS |
338 | #define KVM_MMU_NUM_PREV_ROOTS 3 |
339 | ||
985ab278 SC |
340 | struct kvm_mmu_page; |
341 | ||
d657a98e | 342 | /* |
855feb67 YZ |
343 | * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, |
344 | * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the | |
345 | * current mmu mode. | |
d657a98e ZX |
346 | */ |
347 | struct kvm_mmu { | |
d8dd54e0 | 348 | unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu); |
e4e517b4 | 349 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
736c291c | 350 | int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err, |
78b2c54a | 351 | bool prefault); |
6389ee94 AK |
352 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
353 | struct x86_exception *fault); | |
736c291c SC |
354 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa, |
355 | u32 access, struct x86_exception *exception); | |
54987b7a PB |
356 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
357 | struct x86_exception *exception); | |
e8bc217a | 358 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 359 | struct kvm_mmu_page *sp); |
7eb77e9f | 360 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); |
0f53b5b1 | 361 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 362 | u64 *spte, const void *pte); |
d657a98e | 363 | hpa_t root_hpa; |
be01e8e2 | 364 | gpa_t root_pgd; |
36d9594d | 365 | union kvm_mmu_role mmu_role; |
ae1e2d10 PB |
366 | u8 root_level; |
367 | u8 shadow_root_level; | |
368 | u8 ept_ad; | |
c5a78f2b | 369 | bool direct_map; |
b94742c9 | 370 | struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; |
d657a98e | 371 | |
97d64b78 AK |
372 | /* |
373 | * Bitmap; bit set = permission fault | |
374 | * Byte index: page fault error code [4:1] | |
375 | * Bit index: pte permissions in ACC_* format | |
376 | */ | |
377 | u8 permissions[16]; | |
378 | ||
2d344105 HH |
379 | /* |
380 | * The pkru_mask indicates if protection key checks are needed. It | |
381 | * consists of 16 domains indexed by page fault error code bits [4:1], | |
382 | * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. | |
383 | * Each domain has 2 bits which are ANDed with AD and WD from PKRU. | |
384 | */ | |
385 | u32 pkru_mask; | |
386 | ||
d657a98e | 387 | u64 *pae_root; |
81407ca5 | 388 | u64 *lm_root; |
c258b62b XG |
389 | |
390 | /* | |
391 | * check zero bits on shadow page table entries, these | |
392 | * bits include not only hardware reserved bits but also | |
393 | * the bits spte never used. | |
394 | */ | |
395 | struct rsvd_bits_validate shadow_zero_check; | |
396 | ||
a0a64f50 | 397 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 398 | |
6bb69c9b PB |
399 | /* Can have large pages at levels 2..last_nonleaf_level-1. */ |
400 | u8 last_nonleaf_level; | |
6fd01b71 | 401 | |
2d48a985 JR |
402 | bool nx; |
403 | ||
ff03a073 | 404 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
405 | }; |
406 | ||
a49b9635 LT |
407 | struct kvm_tlb_range { |
408 | u64 start_gfn; | |
409 | u64 pages; | |
410 | }; | |
411 | ||
f5132b01 GN |
412 | enum pmc_type { |
413 | KVM_PMC_GP = 0, | |
414 | KVM_PMC_FIXED, | |
415 | }; | |
416 | ||
417 | struct kvm_pmc { | |
418 | enum pmc_type type; | |
419 | u8 idx; | |
420 | u64 counter; | |
421 | u64 eventsel; | |
422 | struct perf_event *perf_event; | |
423 | struct kvm_vcpu *vcpu; | |
a6da0d77 LX |
424 | /* |
425 | * eventsel value for general purpose counters, | |
426 | * ctrl value for fixed counters. | |
427 | */ | |
428 | u64 current_config; | |
f5132b01 GN |
429 | }; |
430 | ||
431 | struct kvm_pmu { | |
432 | unsigned nr_arch_gp_counters; | |
433 | unsigned nr_arch_fixed_counters; | |
434 | unsigned available_event_types; | |
435 | u64 fixed_ctr_ctrl; | |
436 | u64 global_ctrl; | |
437 | u64 global_status; | |
438 | u64 global_ovf_ctrl; | |
439 | u64 counter_bitmask[2]; | |
440 | u64 global_ctrl_mask; | |
c715eb9f | 441 | u64 global_ovf_ctrl_mask; |
103af0a9 | 442 | u64 reserved_bits; |
f5132b01 | 443 | u8 version; |
15c7ad51 RR |
444 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
445 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 | 446 | struct irq_work irq_work; |
4be94672 | 447 | DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); |
b35e5548 LX |
448 | DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); |
449 | DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); | |
450 | ||
451 | /* | |
452 | * The gate to release perf_events not marked in | |
453 | * pmc_in_use only once in a vcpu time slice. | |
454 | */ | |
455 | bool need_cleanup; | |
456 | ||
457 | /* | |
458 | * The total number of programmed perf_events and it helps to avoid | |
459 | * redundant check before cleanup if guest don't use vPMU at all. | |
460 | */ | |
461 | u8 event_count; | |
f5132b01 GN |
462 | }; |
463 | ||
25462f7f WH |
464 | struct kvm_pmu_ops; |
465 | ||
360b948d PB |
466 | enum { |
467 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 468 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 469 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
470 | }; |
471 | ||
86fd5270 XG |
472 | struct kvm_mtrr_range { |
473 | u64 base; | |
474 | u64 mask; | |
19efffa2 | 475 | struct list_head node; |
86fd5270 XG |
476 | }; |
477 | ||
70109e7d | 478 | struct kvm_mtrr { |
86fd5270 | 479 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 480 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 481 | u64 deftype; |
19efffa2 XG |
482 | |
483 | struct list_head head; | |
70109e7d XG |
484 | }; |
485 | ||
1f4b34f8 AS |
486 | /* Hyper-V SynIC timer */ |
487 | struct kvm_vcpu_hv_stimer { | |
488 | struct hrtimer timer; | |
489 | int index; | |
6a058a1e | 490 | union hv_stimer_config config; |
1f4b34f8 AS |
491 | u64 count; |
492 | u64 exp_time; | |
493 | struct hv_message msg; | |
494 | bool msg_pending; | |
495 | }; | |
496 | ||
5c919412 AS |
497 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
498 | struct kvm_vcpu_hv_synic { | |
499 | u64 version; | |
500 | u64 control; | |
501 | u64 msg_page; | |
502 | u64 evt_page; | |
503 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
504 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
505 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
506 | DECLARE_BITMAP(vec_bitmap, 256); | |
507 | bool active; | |
efc479e6 | 508 | bool dont_zero_synic_pages; |
5c919412 AS |
509 | }; |
510 | ||
e83d5887 AS |
511 | /* Hyper-V per vcpu emulation context */ |
512 | struct kvm_vcpu_hv { | |
d3457c87 | 513 | u32 vp_index; |
e83d5887 | 514 | u64 hv_vapic; |
9eec50b8 | 515 | s64 runtime_offset; |
5c919412 | 516 | struct kvm_vcpu_hv_synic synic; |
db397571 | 517 | struct kvm_hyperv_exit exit; |
1f4b34f8 AS |
518 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; |
519 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
e6b6c483 | 520 | cpumask_t tlb_flush; |
e83d5887 AS |
521 | }; |
522 | ||
ad312c7c | 523 | struct kvm_vcpu_arch { |
5fdbf976 MT |
524 | /* |
525 | * rip and regs accesses must go through | |
526 | * kvm_{register,rip}_{read,write} functions. | |
527 | */ | |
528 | unsigned long regs[NR_VCPU_REGS]; | |
529 | u32 regs_avail; | |
530 | u32 regs_dirty; | |
34c16eec ZX |
531 | |
532 | unsigned long cr0; | |
e8467fda | 533 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
534 | unsigned long cr2; |
535 | unsigned long cr3; | |
536 | unsigned long cr4; | |
fc78f519 | 537 | unsigned long cr4_guest_owned_bits; |
b899c132 | 538 | unsigned long cr4_guest_rsvd_bits; |
34c16eec | 539 | unsigned long cr8; |
37486135 | 540 | u32 host_pkru; |
b9dd21e1 | 541 | u32 pkru; |
1371d904 | 542 | u32 hflags; |
f6801dff | 543 | u64 efer; |
34c16eec ZX |
544 | u64 apic_base; |
545 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 546 | bool apicv_active; |
e40ff1d6 | 547 | bool load_eoi_exitmap_pending; |
6308630b | 548 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 549 | unsigned long apic_attention; |
e1035715 | 550 | int32_t apic_arb_prio; |
34c16eec | 551 | int mp_state; |
34c16eec | 552 | u64 ia32_misc_enable_msr; |
64d60670 | 553 | u64 smbase; |
52797bf9 | 554 | u64 smi_count; |
b209749f | 555 | bool tpr_access_reporting; |
7204160e | 556 | bool xsaves_enabled; |
20300099 | 557 | u64 ia32_xss; |
518e7b94 | 558 | u64 microcode_version; |
0cf9135b | 559 | u64 arch_capabilities; |
27461da3 | 560 | u64 perf_capabilities; |
34c16eec | 561 | |
14dfe855 JR |
562 | /* |
563 | * Paging state of the vcpu | |
564 | * | |
565 | * If the vcpu runs in guest mode with two level paging this still saves | |
566 | * the paging mode of the l1 guest. This context is always used to | |
567 | * handle faults. | |
568 | */ | |
44dd3ffa VK |
569 | struct kvm_mmu *mmu; |
570 | ||
571 | /* Non-nested MMU for L1 */ | |
572 | struct kvm_mmu root_mmu; | |
8df25a32 | 573 | |
14c07ad8 VK |
574 | /* L1 MMU when running nested */ |
575 | struct kvm_mmu guest_mmu; | |
576 | ||
6539e738 JR |
577 | /* |
578 | * Paging state of an L2 guest (used for nested npt) | |
579 | * | |
580 | * This context will save all necessary information to walk page tables | |
311497e0 | 581 | * of an L2 guest. This context is only initialized for page table |
6539e738 JR |
582 | * walking and not for faulting since we never handle l2 page faults on |
583 | * the host. | |
584 | */ | |
585 | struct kvm_mmu nested_mmu; | |
586 | ||
14dfe855 JR |
587 | /* |
588 | * Pointer to the mmu context currently used for | |
589 | * gva_to_gpa translations. | |
590 | */ | |
591 | struct kvm_mmu *walk_mmu; | |
592 | ||
53c07b18 | 593 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
171a90d7 SC |
594 | struct kvm_mmu_memory_cache mmu_shadow_page_cache; |
595 | struct kvm_mmu_memory_cache mmu_gfn_array_cache; | |
34c16eec ZX |
596 | struct kvm_mmu_memory_cache mmu_page_header_cache; |
597 | ||
f775b13e RR |
598 | /* |
599 | * QEMU userspace and the guest each have their own FPU state. | |
ec269475 PB |
600 | * In vcpu_run, we switch between the user and guest FPU contexts. |
601 | * While running a VCPU, the VCPU thread will have the guest FPU | |
602 | * context. | |
f775b13e RR |
603 | * |
604 | * Note that while the PKRU state lives inside the fpu registers, | |
605 | * it is switched out separately at VMENTER and VMEXIT time. The | |
606 | * "guest_fpu" state here contains the guest FPU context, with the | |
607 | * host PRKU bits. | |
608 | */ | |
d9a710e5 | 609 | struct fpu *user_fpu; |
b666a4b6 | 610 | struct fpu *guest_fpu; |
f775b13e | 611 | |
2acf923e | 612 | u64 xcr0; |
d7876f1b | 613 | u64 guest_supported_xcr0; |
34c16eec | 614 | |
34c16eec ZX |
615 | struct kvm_pio_request pio; |
616 | void *pio_data; | |
7ed9abfe | 617 | void *guest_ins_data; |
34c16eec | 618 | |
66fd3f7f GN |
619 | u8 event_exit_inst_len; |
620 | ||
298101da AK |
621 | struct kvm_queued_exception { |
622 | bool pending; | |
664f8e26 | 623 | bool injected; |
298101da AK |
624 | bool has_error_code; |
625 | u8 nr; | |
626 | u32 error_code; | |
c851436a JM |
627 | unsigned long payload; |
628 | bool has_payload; | |
adfe20fb | 629 | u8 nested_apf; |
298101da AK |
630 | } exception; |
631 | ||
937a7eae | 632 | struct kvm_queued_interrupt { |
04140b41 | 633 | bool injected; |
66fd3f7f | 634 | bool soft; |
937a7eae AK |
635 | u8 nr; |
636 | } interrupt; | |
637 | ||
34c16eec ZX |
638 | int halt_request; /* real mode on Intel only */ |
639 | ||
640 | int cpuid_nent; | |
255cbecf | 641 | struct kvm_cpuid_entry2 *cpuid_entries; |
5a4f55cd | 642 | |
0107973a | 643 | unsigned long cr3_lm_rsvd_bits; |
5a4f55cd | 644 | int maxphyaddr; |
d468d94b | 645 | int max_tdp_level; |
5a4f55cd | 646 | |
34c16eec ZX |
647 | /* emulate context */ |
648 | ||
c9b8b07c | 649 | struct x86_emulate_ctxt *emulate_ctxt; |
7ae441ea GN |
650 | bool emulate_regs_need_sync_to_vcpu; |
651 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 652 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
653 | |
654 | gpa_t time; | |
50d0a0f9 | 655 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 656 | unsigned int hw_tsc_khz; |
0b79459b AH |
657 | struct gfn_to_hva_cache pv_time; |
658 | bool pv_time_enabled; | |
51d59c6b MT |
659 | /* set guest stopped flag in pvclock flags field */ |
660 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
661 | |
662 | struct { | |
a6bd811f | 663 | u8 preempted; |
c9aaa895 GC |
664 | u64 msr_val; |
665 | u64 last_steal; | |
91724814 | 666 | struct gfn_to_pfn_cache cache; |
c9aaa895 GC |
667 | } st; |
668 | ||
56ba77a4 | 669 | u64 l1_tsc_offset; |
a545ab6a | 670 | u64 tsc_offset; |
1d5f066e | 671 | u64 last_guest_tsc; |
6f526ec5 | 672 | u64 last_host_tsc; |
0dd6a6ed | 673 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
674 | u64 this_tsc_nsec; |
675 | u64 this_tsc_write; | |
0d3da0d2 | 676 | u64 this_tsc_generation; |
c285545f | 677 | bool tsc_catchup; |
cc578287 ZA |
678 | bool tsc_always_catchup; |
679 | s8 virtual_tsc_shift; | |
680 | u32 virtual_tsc_mult; | |
681 | u32 virtual_tsc_khz; | |
ba904635 | 682 | s64 ia32_tsc_adjust_msr; |
73f624f4 | 683 | u64 msr_ia32_power_ctl; |
ad721883 | 684 | u64 tsc_scaling_ratio; |
3419ffc8 | 685 | |
7460fb4a AK |
686 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
687 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
688 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 689 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 690 | |
70109e7d | 691 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 692 | u64 pat; |
42dbaa5a | 693 | |
360b948d | 694 | unsigned switch_db_regs; |
42dbaa5a JK |
695 | unsigned long db[KVM_NR_DB_REGS]; |
696 | unsigned long dr6; | |
697 | unsigned long dr7; | |
698 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 699 | unsigned long guest_debug_dr7; |
db2336a8 KH |
700 | u64 msr_platform_info; |
701 | u64 msr_misc_features_enables; | |
890ca9ae HY |
702 | |
703 | u64 mcg_cap; | |
704 | u64 mcg_status; | |
705 | u64 mcg_ctl; | |
c45dcc71 | 706 | u64 mcg_ext_ctl; |
890ca9ae | 707 | u64 *mce_banks; |
94fe45da | 708 | |
bebb106a XG |
709 | /* Cache MMIO info */ |
710 | u64 mmio_gva; | |
871bd034 | 711 | unsigned mmio_access; |
bebb106a | 712 | gfn_t mmio_gfn; |
56f17dd3 | 713 | u64 mmio_gen; |
bebb106a | 714 | |
f5132b01 GN |
715 | struct kvm_pmu pmu; |
716 | ||
94fe45da | 717 | /* used for guest single stepping over the given code position */ |
94fe45da | 718 | unsigned long singlestep_rip; |
f92653ee | 719 | |
e83d5887 | 720 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
721 | |
722 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 723 | |
1cb3f3ae XG |
724 | unsigned long last_retry_eip; |
725 | unsigned long last_retry_addr; | |
726 | ||
af585b92 GN |
727 | struct { |
728 | bool halted; | |
dd03bcaa | 729 | gfn_t gfns[ASYNC_PF_PER_VCPU]; |
344d9588 | 730 | struct gfn_to_hva_cache data; |
2635b5c4 VK |
731 | u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */ |
732 | u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */ | |
733 | u16 vec; | |
7c90705b | 734 | u32 id; |
6adba527 | 735 | bool send_user_only; |
68fd66f1 | 736 | u32 host_apf_flags; |
adfe20fb | 737 | unsigned long nested_apf_token; |
52a5c155 | 738 | bool delivery_as_pf_vmexit; |
557a961a | 739 | bool pageready_pending; |
af585b92 | 740 | } apf; |
2b036c6b BO |
741 | |
742 | /* OSVW MSRs (AMD only) */ | |
743 | struct { | |
744 | u64 length; | |
745 | u64 status; | |
746 | } osvw; | |
ae7a2a3f MT |
747 | |
748 | struct { | |
749 | u64 msr_val; | |
750 | struct gfn_to_hva_cache data; | |
751 | } pv_eoi; | |
93c05d3e | 752 | |
2d5ba19b MT |
753 | u64 msr_kvm_poll_control; |
754 | ||
93c05d3e | 755 | /* |
ffdbd50d ML |
756 | * Indicates the guest is trying to write a gfn that contains one or |
757 | * more of the PTEs used to translate the write itself, i.e. the access | |
758 | * is changing its own translation in the guest page tables. KVM exits | |
759 | * to userspace if emulation of the faulting instruction fails and this | |
760 | * flag is set, as KVM cannot make forward progress. | |
761 | * | |
762 | * If emulation fails for a write to guest page tables, KVM unprotects | |
763 | * (zaps) the shadow page for the target gfn and resumes the guest to | |
764 | * retry the non-emulatable instruction (on hardware). Unprotecting the | |
765 | * gfn doesn't allow forward progress for a self-changing access because | |
766 | * doing so also zaps the translation for the gfn, i.e. retrying the | |
767 | * instruction will hit a !PRESENT fault, which results in a new shadow | |
768 | * page and sends KVM back to square one. | |
93c05d3e XG |
769 | */ |
770 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
771 | |
772 | /* set at EPT violation at this point */ | |
773 | unsigned long exit_qualification; | |
6aef266c SV |
774 | |
775 | /* pv related host specific info */ | |
776 | struct { | |
777 | bool pv_unhalted; | |
778 | } pv; | |
7543a635 SR |
779 | |
780 | int pending_ioapic_eoi; | |
1c1a9ce9 | 781 | int pending_external_vector; |
0f89b207 | 782 | |
de63ad4c LM |
783 | /* be preempted when it's in kernel-mode(cpl=0) */ |
784 | bool preempted_in_kernel; | |
c595ceee PB |
785 | |
786 | /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ | |
787 | bool l1tf_flush_l1d; | |
191c8137 | 788 | |
8a14fe4f JM |
789 | /* Host CPU on which VM-entry was most recently attempted */ |
790 | unsigned int last_vmentry_cpu; | |
791 | ||
191c8137 BP |
792 | /* AMD MSRC001_0015 Hardware Configuration */ |
793 | u64 msr_hwcr; | |
66570e96 OU |
794 | |
795 | /* pv related cpuid info */ | |
796 | struct { | |
797 | /* | |
798 | * value of the eax register in the KVM_CPUID_FEATURES CPUID | |
799 | * leaf. | |
800 | */ | |
801 | u32 features; | |
802 | ||
803 | /* | |
804 | * indicates whether pv emulation should be disabled if features | |
805 | * are not present in the guest's cpuid | |
806 | */ | |
807 | bool enforce; | |
808 | } pv_cpuid; | |
add5e2f0 TL |
809 | |
810 | /* Protected Guests */ | |
811 | bool guest_state_protected; | |
34c16eec ZX |
812 | }; |
813 | ||
db3fe4eb | 814 | struct kvm_lpage_info { |
92f94f1e | 815 | int disallow_lpage; |
db3fe4eb TY |
816 | }; |
817 | ||
818 | struct kvm_arch_memory_slot { | |
018aabb5 | 819 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb | 820 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
21ebbeda | 821 | unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; |
db3fe4eb TY |
822 | }; |
823 | ||
3548a259 RK |
824 | /* |
825 | * We use as the mode the number of bits allocated in the LDR for the | |
826 | * logical processor ID. It happens that these are all powers of two. | |
827 | * This makes it is very easy to detect cases where the APICs are | |
828 | * configured for multiple modes; in that case, we cannot use the map and | |
829 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
830 | */ | |
831 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
832 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
833 | #define KVM_APIC_MODE_X2APIC 16 | |
834 | ||
1e08ec4a GN |
835 | struct kvm_apic_map { |
836 | struct rcu_head rcu; | |
3548a259 | 837 | u8 mode; |
0ca52e7b | 838 | u32 max_apic_id; |
e45115b6 RK |
839 | union { |
840 | struct kvm_lapic *xapic_flat_map[8]; | |
841 | struct kvm_lapic *xapic_cluster_map[16][4]; | |
842 | }; | |
0ca52e7b | 843 | struct kvm_lapic *phys_map[]; |
1e08ec4a GN |
844 | }; |
845 | ||
f97f5a56 JD |
846 | /* Hyper-V synthetic debugger (SynDbg)*/ |
847 | struct kvm_hv_syndbg { | |
848 | struct { | |
849 | u64 control; | |
850 | u64 status; | |
851 | u64 send_page; | |
852 | u64 recv_page; | |
853 | u64 pending_page; | |
854 | } control; | |
855 | u64 options; | |
856 | }; | |
857 | ||
e83d5887 AS |
858 | /* Hyper-V emulation context */ |
859 | struct kvm_hv { | |
3f5ad8be | 860 | struct mutex hv_lock; |
e83d5887 AS |
861 | u64 hv_guest_os_id; |
862 | u64 hv_hypercall; | |
863 | u64 hv_tsc_page; | |
e7d9513b AS |
864 | |
865 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
866 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
867 | u64 hv_crash_ctl; | |
095cf55d | 868 | |
7357b1df | 869 | struct ms_hyperv_tsc_page tsc_ref; |
faeb7833 RK |
870 | |
871 | struct idr conn_to_evt; | |
a2e164e7 VK |
872 | |
873 | u64 hv_reenlightenment_control; | |
874 | u64 hv_tsc_emulation_control; | |
875 | u64 hv_tsc_emulation_status; | |
87ee613d VK |
876 | |
877 | /* How many vCPUs have VP index != vCPU index */ | |
878 | atomic_t num_mismatched_vp_indexes; | |
6f6a657c VK |
879 | |
880 | struct hv_partition_assist_pg *hv_pa_pg; | |
f97f5a56 | 881 | struct kvm_hv_syndbg hv_syndbg; |
e83d5887 AS |
882 | }; |
883 | ||
1a155254 AG |
884 | struct msr_bitmap_range { |
885 | u32 flags; | |
886 | u32 nmsrs; | |
887 | u32 base; | |
888 | unsigned long *bitmap; | |
889 | }; | |
890 | ||
49776faf RK |
891 | enum kvm_irqchip_mode { |
892 | KVM_IRQCHIP_NONE, | |
893 | KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ | |
894 | KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ | |
895 | }; | |
896 | ||
34d38a54 SC |
897 | struct kvm_x86_msr_filter { |
898 | u8 count; | |
899 | bool default_allow:1; | |
900 | struct msr_bitmap_range ranges[16]; | |
901 | }; | |
902 | ||
4e19c36f | 903 | #define APICV_INHIBIT_REASON_DISABLE 0 |
f4fdc0a2 | 904 | #define APICV_INHIBIT_REASON_HYPERV 1 |
9a0bf054 | 905 | #define APICV_INHIBIT_REASON_NESTED 2 |
f3515dc3 | 906 | #define APICV_INHIBIT_REASON_IRQWIN 3 |
e2ed4078 | 907 | #define APICV_INHIBIT_REASON_PIT_REINJ 4 |
cc7f5577 | 908 | #define APICV_INHIBIT_REASON_X2APIC 5 |
4e19c36f | 909 | |
fef9cce0 | 910 | struct kvm_arch { |
bc8a3d89 BG |
911 | unsigned long n_used_mmu_pages; |
912 | unsigned long n_requested_mmu_pages; | |
913 | unsigned long n_max_mmu_pages; | |
332b207d | 914 | unsigned int indirect_shadow_pages; |
ca333add | 915 | u8 mmu_valid_gen; |
f05e70ac ZX |
916 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
917 | /* | |
918 | * Hash table of struct kvm_mmu_page. | |
919 | */ | |
920 | struct list_head active_mmu_pages; | |
31741eb1 | 921 | struct list_head zapped_obsolete_pages; |
1aa9b957 | 922 | struct list_head lpage_disallowed_mmu_pages; |
13d268ca | 923 | struct kvm_page_track_notifier_node mmu_sp_tracker; |
0eb05bf2 | 924 | struct kvm_page_track_notifier_head track_notifier_head; |
365c8868 | 925 | |
4d5c5d0f | 926 | struct list_head assigned_dev_head; |
19de40a8 | 927 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 928 | bool iommu_noncoherent; |
e0f0bbc5 AW |
929 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
930 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
931 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
932 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
933 | struct kvm_pic *vpic; |
934 | struct kvm_ioapic *vioapic; | |
7837699f | 935 | struct kvm_pit *vpit; |
42720138 | 936 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
937 | struct mutex apic_map_lock; |
938 | struct kvm_apic_map *apic_map; | |
44d52717 | 939 | atomic_t apic_map_dirty; |
bfc6d222 | 940 | |
c24ae0dc | 941 | bool apic_access_page_done; |
4e19c36f | 942 | unsigned long apicv_inhibit_reasons; |
18068523 GOC |
943 | |
944 | gpa_t wall_clock; | |
b7ebfb05 | 945 | |
4d5422ce | 946 | bool mwait_in_guest; |
caa057a2 | 947 | bool hlt_in_guest; |
b31c114b | 948 | bool pause_in_guest; |
b5170063 | 949 | bool cstate_in_guest; |
4d5422ce | 950 | |
5550af4d | 951 | unsigned long irq_sources_bitmap; |
afbcf7ab | 952 | s64 kvmclock_offset; |
038f8c11 | 953 | raw_spinlock_t tsc_write_lock; |
f38e098f | 954 | u64 last_tsc_nsec; |
f38e098f | 955 | u64 last_tsc_write; |
5d3cb0f6 | 956 | u32 last_tsc_khz; |
e26101b1 ZA |
957 | u64 cur_tsc_nsec; |
958 | u64 cur_tsc_write; | |
959 | u64 cur_tsc_offset; | |
0d3da0d2 | 960 | u64 cur_tsc_generation; |
b48aa97e | 961 | int nr_vcpus_matched_tsc; |
ffde22ac | 962 | |
d828199e MT |
963 | spinlock_t pvclock_gtod_sync_lock; |
964 | bool use_master_clock; | |
965 | u64 master_kernel_ns; | |
a5a1d1c2 | 966 | u64 master_cycle_now; |
7e44e449 | 967 | struct delayed_work kvmclock_update_work; |
332967a3 | 968 | struct delayed_work kvmclock_sync_work; |
d828199e | 969 | |
ffde22ac | 970 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 971 | |
6ef768fa PB |
972 | /* reads protected by irq_srcu, writes by irq_lock */ |
973 | struct hlist_head mask_notifier_list; | |
974 | ||
e83d5887 | 975 | struct kvm_hv hyperv; |
b034cf01 XG |
976 | |
977 | #ifdef CONFIG_KVM_MMU_AUDIT | |
978 | int audit_point; | |
979 | #endif | |
54750f2c | 980 | |
a826faf1 | 981 | bool backwards_tsc_observed; |
54750f2c | 982 | bool boot_vcpu_runs_old_kvmclock; |
d71ba788 | 983 | u32 bsp_vcpu_id; |
90de4a18 NA |
984 | |
985 | u64 disabled_quirks; | |
49df6397 | 986 | |
49776faf | 987 | enum kvm_irqchip_mode irqchip_mode; |
b053b2ae | 988 | u8 nr_reserved_ioapic_pins; |
52004014 FW |
989 | |
990 | bool disabled_lapic_found; | |
44a95dae | 991 | |
37131313 | 992 | bool x2apic_format; |
c519265f | 993 | bool x2apic_broadcast_quirk_disabled; |
6fbbde9a DS |
994 | |
995 | bool guest_can_read_msr_platform_info; | |
59073aaf | 996 | bool exception_payload_enabled; |
66bb8a06 | 997 | |
34d38a54 SC |
998 | bool bus_lock_detection_enabled; |
999 | ||
1ae09954 AG |
1000 | /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */ |
1001 | u32 user_space_msr_mask; | |
1002 | ||
34d38a54 | 1003 | struct kvm_x86_msr_filter __rcu *msr_filter; |
1a155254 | 1004 | |
66bb8a06 | 1005 | struct kvm_pmu_event_filter *pmu_event_filter; |
1aa9b957 | 1006 | struct task_struct *nx_lpage_recovery_thread; |
fe5db27d BG |
1007 | |
1008 | /* | |
1009 | * Whether the TDP MMU is enabled for this VM. This contains a | |
1010 | * snapshot of the TDP MMU module parameter from when the VM was | |
1011 | * created and remains unchanged for the life of the VM. If this is | |
1012 | * true, TDP MMU handler functions will run for various MMU | |
1013 | * operations. | |
1014 | */ | |
1015 | bool tdp_mmu_enabled; | |
89c0fd49 | 1016 | |
c0dba6e4 BG |
1017 | /* |
1018 | * List of struct kvmp_mmu_pages being used as roots. | |
1019 | * All struct kvm_mmu_pages in the list should have | |
1020 | * tdp_mmu_page set. | |
1021 | * All struct kvm_mmu_pages in the list should have a positive | |
1022 | * root_count except when a thread holds the MMU lock and is removing | |
1023 | * an entry from the list. | |
1024 | */ | |
02c00b3a | 1025 | struct list_head tdp_mmu_roots; |
c0dba6e4 BG |
1026 | |
1027 | /* | |
1028 | * List of struct kvmp_mmu_pages not being used as roots. | |
1029 | * All struct kvm_mmu_pages in the list should have | |
1030 | * tdp_mmu_page set and a root_count of 0. | |
1031 | */ | |
89c0fd49 | 1032 | struct list_head tdp_mmu_pages; |
d69fb81f ZX |
1033 | }; |
1034 | ||
0711456c | 1035 | struct kvm_vm_stat { |
8a7e75d4 SJS |
1036 | ulong mmu_shadow_zapped; |
1037 | ulong mmu_pte_write; | |
1038 | ulong mmu_pte_updated; | |
1039 | ulong mmu_pde_zapped; | |
1040 | ulong mmu_flooded; | |
1041 | ulong mmu_recycled; | |
1042 | ulong mmu_cache_miss; | |
1043 | ulong mmu_unsync; | |
1044 | ulong remote_tlb_flush; | |
1045 | ulong lpages; | |
b8e8c830 | 1046 | ulong nx_lpage_splits; |
f3414bc7 | 1047 | ulong max_mmu_page_hash_collisions; |
0711456c ZX |
1048 | }; |
1049 | ||
77b4c255 | 1050 | struct kvm_vcpu_stat { |
8a7e75d4 SJS |
1051 | u64 pf_fixed; |
1052 | u64 pf_guest; | |
1053 | u64 tlb_flush; | |
1054 | u64 invlpg; | |
1055 | ||
1056 | u64 exits; | |
1057 | u64 io_exits; | |
1058 | u64 mmio_exits; | |
1059 | u64 signal_exits; | |
1060 | u64 irq_window_exits; | |
1061 | u64 nmi_window_exits; | |
c595ceee | 1062 | u64 l1d_flush; |
8a7e75d4 SJS |
1063 | u64 halt_exits; |
1064 | u64 halt_successful_poll; | |
1065 | u64 halt_attempted_poll; | |
1066 | u64 halt_poll_invalid; | |
1067 | u64 halt_wakeup; | |
1068 | u64 request_irq_exits; | |
1069 | u64 irq_exits; | |
1070 | u64 host_state_reload; | |
8a7e75d4 SJS |
1071 | u64 fpu_reload; |
1072 | u64 insn_emulation; | |
1073 | u64 insn_emulation_fail; | |
1074 | u64 hypercalls; | |
1075 | u64 irq_injections; | |
1076 | u64 nmi_injections; | |
0f1e261e | 1077 | u64 req_event; |
cb953129 DM |
1078 | u64 halt_poll_success_ns; |
1079 | u64 halt_poll_fail_ns; | |
77b4c255 | 1080 | }; |
ad312c7c | 1081 | |
8a76d7f2 JR |
1082 | struct x86_instruction_info; |
1083 | ||
8fe8ab46 WA |
1084 | struct msr_data { |
1085 | bool host_initiated; | |
1086 | u32 index; | |
1087 | u64 data; | |
1088 | }; | |
1089 | ||
cb5281a5 PB |
1090 | struct kvm_lapic_irq { |
1091 | u32 vector; | |
b7cb2231 PB |
1092 | u16 delivery_mode; |
1093 | u16 dest_mode; | |
1094 | bool level; | |
1095 | u16 trig_mode; | |
cb5281a5 PB |
1096 | u32 shorthand; |
1097 | u32 dest_id; | |
93bbf0b8 | 1098 | bool msi_redir_hint; |
cb5281a5 PB |
1099 | }; |
1100 | ||
c96001c5 PX |
1101 | static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) |
1102 | { | |
1103 | return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; | |
1104 | } | |
1105 | ||
ea4a5ff8 | 1106 | struct kvm_x86_ops { |
13a34e06 RK |
1107 | int (*hardware_enable)(void); |
1108 | void (*hardware_disable)(void); | |
6e4fd06f | 1109 | void (*hardware_unsetup)(void); |
774ead3a | 1110 | bool (*cpu_has_accelerated_tpr)(void); |
5719455f | 1111 | bool (*has_emulated_msr)(struct kvm *kvm, u32 index); |
7c1b761b | 1112 | void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1113 | |
562b6b08 | 1114 | unsigned int vm_size; |
03543133 SS |
1115 | int (*vm_init)(struct kvm *kvm); |
1116 | void (*vm_destroy)(struct kvm *kvm); | |
1117 | ||
ea4a5ff8 | 1118 | /* Create, but do not attach this VCPU */ |
987b2594 | 1119 | int (*vcpu_create)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1120 | void (*vcpu_free)(struct kvm_vcpu *vcpu); |
d28bc9dd | 1121 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
1122 | |
1123 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
1124 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
1125 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 1126 | |
6986982f | 1127 | void (*update_exception_bitmap)(struct kvm_vcpu *vcpu); |
609e36d3 | 1128 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1129 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
1130 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
1131 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
1132 | struct kvm_segment *var, int seg); | |
2e4d2653 | 1133 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1134 | void (*set_segment)(struct kvm_vcpu *vcpu, |
1135 | struct kvm_segment *var, int seg); | |
1136 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
ea4a5ff8 | 1137 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); |
c2fe3cd4 SC |
1138 | bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0); |
1139 | void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); | |
72f211ec | 1140 | int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
1141 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
1142 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
1143 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
1144 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
c77fb5fe | 1145 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 1146 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 1147 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
1148 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
1149 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
1150 | ||
7780938c | 1151 | void (*tlb_flush_all)(struct kvm_vcpu *vcpu); |
eeeb4f67 | 1152 | void (*tlb_flush_current)(struct kvm_vcpu *vcpu); |
b08660e5 | 1153 | int (*tlb_remote_flush)(struct kvm *kvm); |
a49b9635 LT |
1154 | int (*tlb_remote_flush_with_range)(struct kvm *kvm, |
1155 | struct kvm_tlb_range *range); | |
ea4a5ff8 | 1156 | |
faff8758 JS |
1157 | /* |
1158 | * Flush any TLB entries associated with the given GVA. | |
1159 | * Does not need to flush GPA->HPA mappings. | |
1160 | * Can potentially get non-canonical addresses through INVLPGs, which | |
1161 | * the implementation may choose to ignore if appropriate. | |
1162 | */ | |
1163 | void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); | |
ea4a5ff8 | 1164 | |
e64419d9 SC |
1165 | /* |
1166 | * Flush any TLB entries created by the guest. Like tlb_flush_gva(), | |
1167 | * does not need to flush GPA->HPA mappings. | |
1168 | */ | |
1169 | void (*tlb_flush_guest)(struct kvm_vcpu *vcpu); | |
1170 | ||
a9ab13ff | 1171 | enum exit_fastpath_completion (*run)(struct kvm_vcpu *vcpu); |
1e9e2622 WL |
1172 | int (*handle_exit)(struct kvm_vcpu *vcpu, |
1173 | enum exit_fastpath_completion exit_fastpath); | |
f8ea7c60 | 1174 | int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
5ef8acbd | 1175 | void (*update_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 1176 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 1177 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1178 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
1179 | unsigned char *hypercall_addr); | |
66fd3f7f | 1180 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 1181 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
cfcd20e5 | 1182 | void (*queue_exception)(struct kvm_vcpu *vcpu); |
b463a6f7 | 1183 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
c9d40913 PB |
1184 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection); |
1185 | int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); | |
3cfc3092 JK |
1186 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
1187 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
1188 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
1189 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 1190 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
ef8efd7a | 1191 | bool (*check_apicv_inhibit_reasons)(ulong bit); |
2de9d0cc | 1192 | void (*pre_update_apicv_exec_ctrl)(struct kvm *kvm, bool activate); |
d62caabb | 1193 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); |
c7c9c56c | 1194 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
67c9dddc | 1195 | void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); |
e6c67d8c | 1196 | bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); |
6308630b | 1197 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d860bbe | 1198 | void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); |
a4148b7c | 1199 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu); |
91a5f413 | 1200 | int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
76dfafd5 | 1201 | int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1202 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
2ac52ab8 | 1203 | int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); |
4b12f0de | 1204 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
344f414f | 1205 | |
2a40b900 SC |
1206 | void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, unsigned long pgd, |
1207 | int pgd_level); | |
727a7e27 | 1208 | |
f5f48ee1 SY |
1209 | bool (*has_wbinvd_exit)(void); |
1210 | ||
326e7425 LS |
1211 | /* Returns actual tsc_offset set in active VMCS */ |
1212 | u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); | |
99e3e30a | 1213 | |
235ba74f SC |
1214 | /* |
1215 | * Retrieve somewhat arbitrary exit information. Intended to be used | |
1216 | * only from within tracepoints to avoid VMREADs when tracing is off. | |
1217 | */ | |
1218 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2, | |
1219 | u32 *exit_int_info, u32 *exit_int_info_err_code); | |
8a76d7f2 JR |
1220 | |
1221 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
1222 | struct x86_instruction_info *info, | |
21f1b8f2 SC |
1223 | enum x86_intercept_stage stage, |
1224 | struct x86_exception *exception); | |
a9ab13ff | 1225 | void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); |
7f5581f5 | 1226 | |
d264ee0c | 1227 | void (*request_immediate_exit)(struct kvm_vcpu *vcpu); |
ae97a3b8 RK |
1228 | |
1229 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
1230 | |
1231 | /* | |
1232 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
1233 | * be valid if the specific arch has hardware-accelerated dirty logging | |
1234 | * mechanism. Currently only for PML on VMX. | |
1235 | * | |
1236 | * - slot_enable_log_dirty: | |
1237 | * called when enabling log dirty mode for the slot. | |
1238 | * - slot_disable_log_dirty: | |
1239 | * called when disabling log dirty mode for the slot. | |
1240 | * also called when slot is created with log dirty disabled. | |
1241 | * - flush_log_dirty: | |
1242 | * called before reporting dirty_bitmap to userspace. | |
1243 | * - enable_log_dirty_pt_masked: | |
1244 | * called when reenabling log dirty for the GFNs in the mask after | |
1245 | * corresponding bits are cleared in slot->dirty_bitmap. | |
1246 | */ | |
1247 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
1248 | struct kvm_memory_slot *slot); | |
1249 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
1250 | struct kvm_memory_slot *slot); | |
1251 | void (*flush_log_dirty)(struct kvm *kvm); | |
1252 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
1253 | struct kvm_memory_slot *slot, | |
1254 | gfn_t offset, unsigned long mask); | |
fb04a1ed | 1255 | int (*cpu_dirty_log_size)(void); |
bab4165e | 1256 | |
25462f7f WH |
1257 | /* pmu operations of sub-arch */ |
1258 | const struct kvm_pmu_ops *pmu_ops; | |
33b22172 | 1259 | const struct kvm_x86_nested_ops *nested_ops; |
efc64404 | 1260 | |
bf9f6ac8 FW |
1261 | /* |
1262 | * Architecture specific hooks for vCPU blocking due to | |
1263 | * HLT instruction. | |
1264 | * Returns for .pre_block(): | |
1265 | * - 0 means continue to block the vCPU. | |
1266 | * - 1 means we cannot block the vCPU since some event | |
1267 | * happens during this period, such as, 'ON' bit in | |
1268 | * posted-interrupts descriptor is set. | |
1269 | */ | |
1270 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
1271 | void (*post_block)(struct kvm_vcpu *vcpu); | |
d1ed092f SS |
1272 | |
1273 | void (*vcpu_blocking)(struct kvm_vcpu *vcpu); | |
1274 | void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); | |
1275 | ||
efc64404 FW |
1276 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
1277 | uint32_t guest_irq, bool set); | |
be8ca170 | 1278 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); |
17e433b5 | 1279 | bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); |
ce7a058a | 1280 | |
f9927982 SC |
1281 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, |
1282 | bool *expired); | |
ce7a058a | 1283 | void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); |
c45dcc71 AR |
1284 | |
1285 | void (*setup_mce)(struct kvm_vcpu *vcpu); | |
0234bf88 | 1286 | |
c9d40913 | 1287 | int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); |
0234bf88 | 1288 | int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); |
ed19321f | 1289 | int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); |
c9d40913 | 1290 | void (*enable_smi_window)(struct kvm_vcpu *vcpu); |
5acc5c06 BS |
1291 | |
1292 | int (*mem_enc_op)(struct kvm *kvm, void __user *argp); | |
69eaedee BS |
1293 | int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); |
1294 | int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); | |
801e459a TL |
1295 | |
1296 | int (*get_msr_feature)(struct kvm_msr_entry *entry); | |
57b119da | 1297 | |
09e3e2a1 | 1298 | bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, void *insn, int insn_len); |
4b9852f4 LA |
1299 | |
1300 | bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); | |
344c6c80 | 1301 | int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); |
93dff2fe JM |
1302 | |
1303 | void (*migrate_timers)(struct kvm_vcpu *vcpu); | |
51de8151 | 1304 | void (*msr_filter_changed)(struct kvm_vcpu *vcpu); |
f9a4d621 | 1305 | int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); |
647daca2 TL |
1306 | |
1307 | void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); | |
ea4a5ff8 ZX |
1308 | }; |
1309 | ||
33b22172 PB |
1310 | struct kvm_x86_nested_ops { |
1311 | int (*check_events)(struct kvm_vcpu *vcpu); | |
d2060bd4 | 1312 | bool (*hv_timer_pending)(struct kvm_vcpu *vcpu); |
33b22172 PB |
1313 | int (*get_state)(struct kvm_vcpu *vcpu, |
1314 | struct kvm_nested_state __user *user_kvm_nested_state, | |
1315 | unsigned user_data_size); | |
1316 | int (*set_state)(struct kvm_vcpu *vcpu, | |
1317 | struct kvm_nested_state __user *user_kvm_nested_state, | |
1318 | struct kvm_nested_state *kvm_state); | |
729c15c2 | 1319 | bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu); |
02f5fb2e | 1320 | int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa); |
33b22172 PB |
1321 | |
1322 | int (*enable_evmcs)(struct kvm_vcpu *vcpu, | |
1323 | uint16_t *vmcs_version); | |
1324 | uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 ZX |
1325 | }; |
1326 | ||
d008dfdb SC |
1327 | struct kvm_x86_init_ops { |
1328 | int (*cpu_has_kvm_support)(void); | |
1329 | int (*disabled_by_bios)(void); | |
1330 | int (*check_processor_compatibility)(void); | |
1331 | int (*hardware_setup)(void); | |
1332 | ||
1333 | struct kvm_x86_ops *runtime_ops; | |
1334 | }; | |
1335 | ||
af585b92 | 1336 | struct kvm_arch_async_pf { |
7c90705b | 1337 | u32 token; |
af585b92 | 1338 | gfn_t gfn; |
fb67e14f | 1339 | unsigned long cr3; |
c4806acd | 1340 | bool direct_map; |
af585b92 GN |
1341 | }; |
1342 | ||
91661989 | 1343 | extern u64 __read_mostly host_efer; |
3edd6839 | 1344 | extern bool __read_mostly allow_smaller_maxphyaddr; |
afaf0b2f | 1345 | extern struct kvm_x86_ops kvm_x86_ops; |
97896d04 | 1346 | |
434a1e94 SC |
1347 | #define __KVM_HAVE_ARCH_VM_ALLOC |
1348 | static inline struct kvm *kvm_arch_alloc_vm(void) | |
1349 | { | |
88dca4ca | 1350 | return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
434a1e94 | 1351 | } |
562b6b08 | 1352 | void kvm_arch_free_vm(struct kvm *kvm); |
434a1e94 | 1353 | |
b08660e5 TL |
1354 | #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB |
1355 | static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) | |
1356 | { | |
afaf0b2f SC |
1357 | if (kvm_x86_ops.tlb_remote_flush && |
1358 | !kvm_x86_ops.tlb_remote_flush(kvm)) | |
b08660e5 TL |
1359 | return 0; |
1360 | else | |
1361 | return -ENOTSUPP; | |
1362 | } | |
1363 | ||
54f1585a ZX |
1364 | int kvm_mmu_module_init(void); |
1365 | void kvm_mmu_module_exit(void); | |
1366 | ||
1367 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
1368 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
13d268ca XG |
1369 | void kvm_mmu_init_vm(struct kvm *kvm); |
1370 | void kvm_mmu_uninit_vm(struct kvm *kvm); | |
7b52345e | 1371 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 1372 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 1373 | u64 acc_track_mask, u64 me_mask); |
54f1585a | 1374 | |
8a3c1a33 | 1375 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 | 1376 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
1377 | struct kvm_memory_slot *memslot, |
1378 | int start_level); | |
3ea3b7fa | 1379 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 1380 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
1381 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
1382 | struct kvm_memory_slot *memslot); | |
1383 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
1384 | struct kvm_memory_slot *memslot); | |
1385 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
1386 | struct kvm_memory_slot *memslot); | |
1387 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1388 | struct kvm_memory_slot *slot, | |
1389 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 1390 | void kvm_mmu_zap_all(struct kvm *kvm); |
15248258 | 1391 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); |
bc8a3d89 BG |
1392 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); |
1393 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); | |
54f1585a | 1394 | |
ff03a073 | 1395 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
9ed38ffa | 1396 | bool pdptrs_changed(struct kvm_vcpu *vcpu); |
cc4b6871 | 1397 | |
3200f405 | 1398 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 1399 | const void *val, int bytes); |
2f333bcb | 1400 | |
6ef768fa PB |
1401 | struct kvm_irq_mask_notifier { |
1402 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
1403 | int irq; | |
1404 | struct hlist_node link; | |
1405 | }; | |
1406 | ||
1407 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1408 | struct kvm_irq_mask_notifier *kimn); | |
1409 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1410 | struct kvm_irq_mask_notifier *kimn); | |
1411 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1412 | bool mask); | |
1413 | ||
2f333bcb | 1414 | extern bool tdp_enabled; |
9f811285 | 1415 | |
a3e06bbe LJ |
1416 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
1417 | ||
92a1f12d JR |
1418 | /* control of guest tsc rate supported? */ |
1419 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
1420 | /* maximum supported tsc_khz for guests */ |
1421 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
1422 | /* number of bits of the fractional part of the TSC scaling ratio */ |
1423 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1424 | /* maximum allowed value of TSC scaling ratio */ | |
1425 | extern u64 kvm_max_tsc_scaling_ratio; | |
64672c95 YJ |
1426 | /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ |
1427 | extern u64 kvm_default_tsc_scaling_ratio; | |
92a1f12d | 1428 | |
c45dcc71 | 1429 | extern u64 kvm_mce_cap_supported; |
92a1f12d | 1430 | |
41577ab8 SC |
1431 | /* |
1432 | * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing | |
1433 | * userspace I/O) to indicate that the emulation context | |
1434 | * should be resued as is, i.e. skip initialization of | |
1435 | * emulation context, instruction fetch and decode. | |
1436 | * | |
1437 | * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. | |
1438 | * Indicates that only select instructions (tagged with | |
1439 | * EmulateOnUD) should be emulated (to minimize the emulator | |
1440 | * attack surface). See also EMULTYPE_TRAP_UD_FORCED. | |
1441 | * | |
1442 | * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to | |
1443 | * decode the instruction length. For use *only* by | |
afaf0b2f | 1444 | * kvm_x86_ops.skip_emulated_instruction() implementations. |
41577ab8 | 1445 | * |
92daa48b SC |
1446 | * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to |
1447 | * retry native execution under certain conditions, | |
1448 | * Can only be set in conjunction with EMULTYPE_PF. | |
41577ab8 SC |
1449 | * |
1450 | * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was | |
1451 | * triggered by KVM's magic "force emulation" prefix, | |
1452 | * which is opt in via module param (off by default). | |
1453 | * Bypasses EmulateOnUD restriction despite emulating | |
1454 | * due to an intercepted #UD (see EMULTYPE_TRAP_UD). | |
1455 | * Used to test the full emulator from userspace. | |
1456 | * | |
1457 | * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware | |
1458 | * backdoor emulation, which is opt in via module param. | |
1459 | * VMware backoor emulation handles select instructions | |
1460 | * and reinjects the #GP for all other cases. | |
92daa48b SC |
1461 | * |
1462 | * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which | |
1463 | * case the CR2/GPA value pass on the stack is valid. | |
41577ab8 | 1464 | */ |
571008da SY |
1465 | #define EMULTYPE_NO_DECODE (1 << 0) |
1466 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1467 | #define EMULTYPE_SKIP (1 << 2) |
92daa48b | 1468 | #define EMULTYPE_ALLOW_RETRY_PF (1 << 3) |
b4000606 | 1469 | #define EMULTYPE_TRAP_UD_FORCED (1 << 4) |
42cbf068 | 1470 | #define EMULTYPE_VMWARE_GP (1 << 5) |
92daa48b SC |
1471 | #define EMULTYPE_PF (1 << 6) |
1472 | ||
c60658d1 SC |
1473 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); |
1474 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
1475 | void *insn, int insn_len); | |
35be0ade | 1476 | |
f2b4b7dd | 1477 | void kvm_enable_efer_bits(u64); |
384bb783 | 1478 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
edef5c36 | 1479 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); |
f20935d8 SC |
1480 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); |
1481 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); | |
1edce0a9 SC |
1482 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); |
1483 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); | |
54f1585a | 1484 | |
dca7f128 | 1485 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); |
6a908b62 | 1486 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
54f1585a | 1487 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); |
5cb56059 | 1488 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
647daca2 | 1489 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1490 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1491 | |
3e6e0aab | 1492 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1493 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1494 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1495 | |
7f3d35fd KW |
1496 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1497 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1498 | |
ed02b213 TL |
1499 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu); |
1500 | ||
f27ad38a | 1501 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0); |
5b51cb13 | 1502 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4); |
49a9b07e | 1503 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1504 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1505 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1506 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1507 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1508 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1509 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1510 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1511 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1512 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1513 | |
609e36d3 | 1514 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1515 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1516 | |
91586a3b JK |
1517 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1518 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1519 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1520 | |
298101da AK |
1521 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1522 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
4d5523cf | 1523 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload); |
ce7ddec4 JR |
1524 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1525 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1526 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
53b3d8e9 SC |
1527 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
1528 | struct x86_exception *fault); | |
ec92fe44 JR |
1529 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1530 | gfn_t gfn, void *data, int offset, int len, | |
1531 | u32 access); | |
0a79b009 | 1532 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1533 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1534 | |
1a577b72 MT |
1535 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1536 | int irq_source_id, int level) | |
1537 | { | |
1538 | /* Logical OR for level trig interrupt */ | |
1539 | if (level) | |
1540 | __set_bit(irq_source_id, irq_state); | |
1541 | else | |
1542 | __clear_bit(irq_source_id, irq_state); | |
1543 | ||
1544 | return !!(*irq_state); | |
1545 | } | |
1546 | ||
b94742c9 JS |
1547 | #define KVM_MMU_ROOT_CURRENT BIT(0) |
1548 | #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) | |
1549 | #define KVM_MMU_ROOTS_ALL (~0UL) | |
08fb59d8 | 1550 | |
1a577b72 MT |
1551 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); |
1552 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1553 | |
3419ffc8 SY |
1554 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1555 | ||
7c86663b PB |
1556 | void kvm_update_dr7(struct kvm_vcpu *vcpu); |
1557 | ||
1cb3f3ae | 1558 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1559 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1560 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1561 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1562 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1563 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
6a82cd1c VK |
1564 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1565 | ulong roots_to_free); | |
54987b7a PB |
1566 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1567 | struct x86_exception *exception); | |
ab9ae313 AK |
1568 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1569 | struct x86_exception *exception); | |
1570 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1571 | struct x86_exception *exception); | |
1572 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1573 | struct x86_exception *exception); | |
1574 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1575 | struct x86_exception *exception); | |
54f1585a | 1576 | |
4e19c36f SS |
1577 | bool kvm_apicv_activated(struct kvm *kvm); |
1578 | void kvm_apicv_init(struct kvm *kvm, bool enable); | |
8df14af4 SS |
1579 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu); |
1580 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, | |
1581 | unsigned long bit); | |
d62caabb | 1582 | |
54f1585a ZX |
1583 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1584 | ||
736c291c | 1585 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 1586 | void *insn, int insn_len); |
a7052897 | 1587 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
5efac074 PB |
1588 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1589 | gva_t gva, hpa_t root_hpa); | |
eb4b248e | 1590 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); |
be01e8e2 | 1591 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush, |
4a632ac6 | 1592 | bool skip_mmu_sync); |
34c16eec | 1593 | |
83013059 SC |
1594 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
1595 | int tdp_huge_page_level); | |
18552672 | 1596 | |
d6e88aec | 1597 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1598 | { |
1599 | u16 ldt; | |
1600 | asm("sldt %0" : "=g"(ldt)); | |
1601 | return ldt; | |
1602 | } | |
1603 | ||
d6e88aec | 1604 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1605 | { |
1606 | asm("lldt %0" : : "rm"(sel)); | |
1607 | } | |
ec6d273d | 1608 | |
ec6d273d ZX |
1609 | #ifdef CONFIG_X86_64 |
1610 | static inline unsigned long read_msr(unsigned long msr) | |
1611 | { | |
1612 | u64 value; | |
1613 | ||
1614 | rdmsrl(msr, value); | |
1615 | return value; | |
1616 | } | |
1617 | #endif | |
1618 | ||
ec6d273d ZX |
1619 | static inline u32 get_rdx_init_val(void) |
1620 | { | |
1621 | return 0x600; /* P6 family */ | |
1622 | } | |
1623 | ||
c1a5d4f9 AK |
1624 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1625 | { | |
1626 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1627 | } | |
1628 | ||
ec6d273d ZX |
1629 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1630 | #define TSS_BASE_SIZE 0x68 | |
1631 | #define TSS_IOPB_SIZE (65536 / 8) | |
1632 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1633 | #define RMODE_TSS_SIZE \ |
1634 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1635 | |
37817f29 IE |
1636 | enum { |
1637 | TASK_SWITCH_CALL = 0, | |
1638 | TASK_SWITCH_IRET = 1, | |
1639 | TASK_SWITCH_JMP = 2, | |
1640 | TASK_SWITCH_GATE = 3, | |
1641 | }; | |
1642 | ||
1371d904 | 1643 | #define HF_GIF_MASK (1 << 0) |
95ba8273 | 1644 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1645 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1646 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1647 | #define HF_SMM_MASK (1 << 6) |
1648 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1649 | |
699023e2 PB |
1650 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1651 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1652 | ||
1653 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1654 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1655 | |
4b526de5 | 1656 | asmlinkage void kvm_spurious_fault(void); |
3901336e | 1657 | |
4ecac3fd AK |
1658 | /* |
1659 | * Hardware virtualization extension instructions may fault if a | |
1660 | * reboot turns off virtualization while processes are running. | |
3901336e JP |
1661 | * Usually after catching the fault we just panic; during reboot |
1662 | * instead the instruction is ignored. | |
4ecac3fd | 1663 | */ |
98cd382d | 1664 | #define __kvm_handle_fault_on_reboot(insn) \ |
3901336e JP |
1665 | "666: \n\t" \ |
1666 | insn "\n\t" \ | |
1667 | "jmp 668f \n\t" \ | |
1668 | "667: \n\t" \ | |
3ebccdf3 TG |
1669 | "1: \n\t" \ |
1670 | ".pushsection .discard.instr_begin \n\t" \ | |
1671 | ".long 1b - . \n\t" \ | |
1672 | ".popsection \n\t" \ | |
3901336e | 1673 | "call kvm_spurious_fault \n\t" \ |
3ebccdf3 TG |
1674 | "1: \n\t" \ |
1675 | ".pushsection .discard.instr_end \n\t" \ | |
1676 | ".long 1b - . \n\t" \ | |
1677 | ".popsection \n\t" \ | |
3901336e | 1678 | "668: \n\t" \ |
f209a26d | 1679 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1680 | |
e930bffe | 1681 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
fdfe7cbd WD |
1682 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end, |
1683 | unsigned flags); | |
57128468 | 1684 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1685 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
748c0e31 | 1686 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1687 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 | 1688 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
71cc849b | 1689 | int kvm_cpu_has_extint(struct kvm_vcpu *v); |
a1b37100 | 1690 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); |
0b71785d | 1691 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1692 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1693 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
e930bffe | 1694 | |
4180bf1b | 1695 | int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, |
bdf7ffc8 | 1696 | unsigned long ipi_bitmap_high, u32 min, |
4180bf1b WL |
1697 | unsigned long icr, int op_64_bit); |
1698 | ||
7e34fbd0 SC |
1699 | void kvm_define_user_return_msr(unsigned index, u32 msr); |
1700 | int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask); | |
18863bdd | 1701 | |
35181e86 | 1702 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1703 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1704 | |
82b32774 | 1705 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1706 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1707 | ||
2860c4b1 PB |
1708 | void kvm_make_mclock_inprogress_request(struct kvm *kvm); |
1709 | void kvm_make_scan_ioapic_request(struct kvm *kvm); | |
7ee30bc1 NNL |
1710 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
1711 | unsigned long *vcpu_bitmap); | |
2860c4b1 | 1712 | |
2a18b7e7 | 1713 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
1714 | struct kvm_async_pf *work); |
1715 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1716 | struct kvm_async_pf *work); | |
56028d08 GN |
1717 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1718 | struct kvm_async_pf *work); | |
557a961a | 1719 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu); |
7c0ade6c | 1720 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1721 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1722 | ||
6affcbed KH |
1723 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); |
1724 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); | |
d264ee0c | 1725 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); |
db8fcefa | 1726 | |
f5132b01 GN |
1727 | int kvm_is_in_guest(void); |
1728 | ||
ff5a983c PX |
1729 | void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, |
1730 | u32 size); | |
d71ba788 PB |
1731 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1732 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1733 | |
8feb4a04 FW |
1734 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1735 | struct kvm_vcpu **dest_vcpu); | |
1736 | ||
37131313 | 1737 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 1738 | struct kvm_lapic_irq *irq); |
197a4f4b | 1739 | |
fdcf7562 AG |
1740 | static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) |
1741 | { | |
1742 | /* We can only post Fixed and LowPrio IRQs */ | |
637543a8 SS |
1743 | return (irq->delivery_mode == APIC_DM_FIXED || |
1744 | irq->delivery_mode == APIC_DM_LOWEST); | |
fdcf7562 AG |
1745 | } |
1746 | ||
d1ed092f SS |
1747 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) |
1748 | { | |
afaf0b2f SC |
1749 | if (kvm_x86_ops.vcpu_blocking) |
1750 | kvm_x86_ops.vcpu_blocking(vcpu); | |
d1ed092f SS |
1751 | } |
1752 | ||
1753 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1754 | { | |
afaf0b2f SC |
1755 | if (kvm_x86_ops.vcpu_unblocking) |
1756 | kvm_x86_ops.vcpu_unblocking(vcpu); | |
d1ed092f SS |
1757 | } |
1758 | ||
3491caf2 | 1759 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
3217f7c2 | 1760 | |
7d669f50 SS |
1761 | static inline int kvm_cpu_get_apicid(int mps_cpu) |
1762 | { | |
1763 | #ifdef CONFIG_X86_LOCAL_APIC | |
64063505 | 1764 | return default_cpu_present_to_apicid(mps_cpu); |
7d669f50 SS |
1765 | #else |
1766 | WARN_ON_ONCE(1); | |
1767 | return BAD_APICID; | |
1768 | #endif | |
1769 | } | |
1770 | ||
05cade71 LP |
1771 | #define put_smstate(type, buf, offset, val) \ |
1772 | *(type *)((buf) + (offset) - 0x7e00) = val | |
1773 | ||
ed19321f SC |
1774 | #define GET_SMSTATE(type, buf, offset) \ |
1775 | (*(type *)((buf) + (offset) - 0x7e00)) | |
1776 | ||
fb04a1ed PX |
1777 | int kvm_cpu_dirty_log_size(void); |
1778 | ||
1965aae3 | 1779 | #endif /* _ASM_X86_KVM_HOST_H */ |