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05e4d316 PA |
1 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H |
2 | #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H | |
1da177e4 | 3 | |
dd46e3ca GC |
4 | #ifdef CONFIG_X86_LOCAL_APIC |
5 | ||
1da177e4 LT |
6 | #include <mach_apicdef.h> |
7 | #include <asm/smp.h> | |
8 | ||
9 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
10 | ||
0a9cc20b | 11 | static inline const struct cpumask *default_target_cpus(void) |
1da177e4 LT |
12 | { |
13 | #ifdef CONFIG_SMP | |
bcda016e | 14 | return cpu_online_mask; |
1da177e4 | 15 | #else |
bcda016e | 16 | return cpumask_of(0); |
1da177e4 LT |
17 | #endif |
18 | } | |
1da177e4 | 19 | |
dd46e3ca GC |
20 | #ifdef CONFIG_X86_64 |
21 | #include <asm/genapic.h> | |
c8d46cf0 IM |
22 | #define cpu_mask_to_apicid (apic->cpu_mask_to_apicid) |
23 | #define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and) | |
24 | #define phys_pkg_id (apic->phys_pkg_id) | |
f910a9dc | 25 | #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID))) |
c8d46cf0 IM |
26 | #define send_IPI_self (apic->send_IPI_self) |
27 | #define wakeup_secondary_cpu (apic->wakeup_cpu) | |
72ce0165 | 28 | extern void default_setup_apic_routing(void); |
dd46e3ca | 29 | #else |
54ac14a8 | 30 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init |
1da177e4 LT |
31 | /* |
32 | * Set up the logical destination ID. | |
33 | * | |
34 | * Intel recommends to set DFR, LDR and TPR before enabling | |
35 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
36 | * document number 292116). So here it goes... | |
37 | */ | |
a5c43296 | 38 | static inline void default_init_apic_ldr(void) |
1da177e4 LT |
39 | { |
40 | unsigned long val; | |
41 | ||
593f4a78 | 42 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
1da177e4 LT |
43 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
44 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
593f4a78 | 45 | apic_write(APIC_LDR, val); |
1da177e4 LT |
46 | } |
47 | ||
7ed248da | 48 | static inline int default_apic_id_registered(void) |
1da177e4 | 49 | { |
4c9961d5 | 50 | return physid_isset(read_apic_id(), phys_cpu_present_map); |
dd46e3ca GC |
51 | } |
52 | ||
bcda016e | 53 | static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask) |
dd46e3ca | 54 | { |
bcda016e | 55 | return cpumask_bits(cpumask)[0]; |
dd46e3ca GC |
56 | } |
57 | ||
6eeb7c5a MT |
58 | static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
59 | const struct cpumask *andmask) | |
95d313cf | 60 | { |
6eeb7c5a MT |
61 | unsigned long mask1 = cpumask_bits(cpumask)[0]; |
62 | unsigned long mask2 = cpumask_bits(andmask)[0]; | |
a775a38b | 63 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; |
95d313cf | 64 | |
a775a38b | 65 | return (unsigned int)(mask1 & mask2 & mask3); |
95d313cf MT |
66 | } |
67 | ||
dd46e3ca GC |
68 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) |
69 | { | |
70 | return cpuid_apic >> index_msb; | |
1da177e4 LT |
71 | } |
72 | ||
72ce0165 | 73 | static inline void default_setup_apic_routing(void) |
1da177e4 | 74 | { |
61048c63 | 75 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
76 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
77 | "Flat", nr_ioapics); | |
61048c63 | 78 | #endif |
1da177e4 LT |
79 | } |
80 | ||
3f57a318 | 81 | static inline int default_apicid_to_node(int logical_apicid) |
1da177e4 | 82 | { |
f47f9d53 YL |
83 | #ifdef CONFIG_SMP |
84 | return apicid_2_node[hard_smp_processor_id()]; | |
85 | #else | |
1da177e4 | 86 | return 0; |
f47f9d53 | 87 | #endif |
1da177e4 | 88 | } |
497c9a19 | 89 | |
dd46e3ca | 90 | #endif |
1da177e4 | 91 | |
d1d7cae8 | 92 | static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) |
dd46e3ca GC |
93 | { |
94 | return physid_isset(apicid, bitmap); | |
95 | } | |
96 | ||
d1d7cae8 | 97 | static inline unsigned long default_check_apicid_present(int bit) |
dd46e3ca GC |
98 | { |
99 | return physid_isset(bit, phys_cpu_present_map); | |
100 | } | |
101 | ||
d190cb87 | 102 | static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) |
dd46e3ca GC |
103 | { |
104 | return phys_map; | |
105 | } | |
106 | ||
1da177e4 | 107 | /* Mapping from cpu number to logical apicid */ |
5257c511 | 108 | static inline int default_cpu_to_logical_apicid(int cpu) |
1da177e4 LT |
109 | { |
110 | return 1 << cpu; | |
111 | } | |
112 | ||
a21769a4 | 113 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
1da177e4 | 114 | { |
e7986739 | 115 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) |
f6bc4029 | 116 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); |
1da177e4 LT |
117 | else |
118 | return BAD_APICID; | |
119 | } | |
120 | ||
a21769a4 IM |
121 | #ifdef CONFIG_X86_32 |
122 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
123 | { | |
124 | return __default_cpu_present_to_apicid(mps_cpu); | |
125 | } | |
126 | #else | |
127 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
128 | #endif | |
129 | ||
1da177e4 LT |
130 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) |
131 | { | |
132 | return physid_mask_of_physid(phys_apicid); | |
133 | } | |
134 | ||
1da177e4 LT |
135 | static inline void setup_portio_remap(void) |
136 | { | |
137 | } | |
138 | ||
139 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | |
140 | { | |
141 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | |
142 | } | |
143 | ||
1da177e4 LT |
144 | static inline void enable_apic_mode(void) |
145 | { | |
146 | } | |
dd46e3ca | 147 | #endif /* CONFIG_X86_LOCAL_APIC */ |
05e4d316 | 148 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */ |