[mirror_ubuntu-focal-kernel.git] / arch / x86 / include / asm / mach_timer.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  Machine specific calibrate_tsc() for generic.
 *  Split out from timer_tsc.c by Osamu Tomita <tomita@cinet.co.jp>
 */
/* ------ Calibrate the TSC ------- 
 * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
 * Too much 64-bit arithmetic here to do this cleanly in C, and for
 * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
 * output busy loop as low as possible. We avoid reading the CTC registers
 * directly because of the awkward 8-bit access mechanism of the 82C54
 * device.
 */
#ifndef _ASM_X86_MACH_DEFAULT_MACH_TIMER_H
#define _ASM_X86_MACH_DEFAULT_MACH_TIMER_H

#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
#define CALIBRATE_LATCH	\
	((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)

static inline void mach_prepare_counter(void)
{
       /* Set the Gate high, disable speaker */
	outb((inb(0x61) & ~0x02) | 0x01, 0x61);

	/*
	 * Now let's take care of CTC channel 2
	 *
	 * Set the Gate high, program CTC channel 2 for mode 0,
	 * (interrupt on terminal count mode), binary count,
	 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
	 *
	 * Some devices need a delay here.
	 */
	outb(0xb0, 0x43);			/* binary, mode 0, LSB/MSB, Ch 2 */
	outb_p(CALIBRATE_LATCH & 0xff, 0x42);	/* LSB of count */
	outb_p(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
}

static inline void mach_countup(unsigned long *count_p)
{
	unsigned long count = 0;
	do {
		count++;
	} while ((inb_p(0x61) & 0x20) == 0);
	*count_p = count;
}

#endif /* _ASM_X86_MACH_DEFAULT_MACH_TIMER_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4	2	/*
1da177e4 LT	3	* Machine specific calibrate_tsc() for generic.
	4	* Split out from timer_tsc.c by Osamu Tomita <tomita@cinet.co.jp>
	5	*/
	6	/* ------ Calibrate the TSC -------
	7	* Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
	8	* Too much 64-bit arithmetic here to do this cleanly in C, and for
	9	* accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
	10	* output busy loop as low as possible. We avoid reading the CTC registers
	11	* directly because of the awkward 8-bit access mechanism of the 82C54
	12	* device.
	13	*/
05e4d316 PA	14	#ifndef _ASM_X86_MACH_DEFAULT_MACH_TIMER_H
05e4d316 PA	15	#define _ASM_X86_MACH_DEFAULT_MACH_TIMER_H
1da177e4	16
539eb11e JS	17	#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
539eb11e JS	18	#define CALIBRATE_LATCH \
b0145bf3	19	((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
1da177e4 LT	20
	21	static inline void mach_prepare_counter(void)
	22	{
	23	/* Set the Gate high, disable speaker */
	24	outb((inb(0x61) & ~0x02) \| 0x01, 0x61);
	25
	26	/*
	27	* Now let's take care of CTC channel 2
	28	*
	29	* Set the Gate high, program CTC channel 2 for mode 0,
	30	* (interrupt on terminal count mode), binary count,
	31	* load 5 * LATCH count, (LSB and MSB) to begin countdown.
	32	*
	33	* Some devices need a delay here.
	34	*/
	35	outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
	36	outb_p(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
	37	outb_p(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
	38	}
	39
	40	static inline void mach_countup(unsigned long *count_p)
	41	{
	42	unsigned long count = 0;
	43	do {
	44	count++;
	45	} while ((inb_p(0x61) & 0x20) == 0);
	46	*count_p = count;
	47	}
	48
05e4d316	49	#endif /* _ASM_X86_MACH_DEFAULT_MACH_TIMER_H */