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1965aae3 PA |
1 | #ifndef _ASM_X86_MCE_H |
2 | #define _ASM_X86_MCE_H | |
e2f43029 | 3 | |
af170c50 | 4 | #include <uapi/asm/mce.h> |
e2f43029 | 5 | |
f51bde6f BP |
6 | /* |
7 | * Machine Check support for x86 | |
8 | */ | |
9 | ||
10 | /* MCG_CAP register defines */ | |
11 | #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ | |
12 | #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ | |
13 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ | |
14 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ | |
15 | #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ | |
16 | #define MCG_EXT_CNT_SHIFT 16 | |
17 | #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) | |
18 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
4b3db708 | 19 | #define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */ |
bc12edb8 | 20 | #define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */ |
f51bde6f BP |
21 | |
22 | /* MCG_STATUS register defines */ | |
23 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ | |
24 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
25 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
bc12edb8 AR |
26 | #define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */ |
27 | ||
28 | /* MCG_EXT_CTL register defines */ | |
29 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */ | |
f51bde6f BP |
30 | |
31 | /* MCi_STATUS register defines */ | |
32 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ | |
33 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
34 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
35 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
36 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
37 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
38 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
39 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
40 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
0ca06c08 | 41 | |
e3480271 CY |
42 | /* AMD-specific bits */ |
43 | #define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */ | |
44 | #define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */ | |
45 | ||
0ca06c08 TL |
46 | /* |
47 | * Note that the full MCACOD field of IA32_MCi_STATUS MSR is | |
48 | * bits 15:0. But bit 12 is the 'F' bit, defined for corrected | |
49 | * errors to indicate that errors are being filtered by hardware. | |
50 | * We should mask out bit 12 when looking for specific signatures | |
51 | * of uncorrected errors - so the F bit is deliberately skipped | |
52 | * in this #define. | |
53 | */ | |
54 | #define MCACOD 0xefff /* MCA Error Code */ | |
f51bde6f BP |
55 | |
56 | /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ | |
57 | #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ | |
0ca06c08 | 58 | #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ |
f51bde6f BP |
59 | #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ |
60 | #define MCACOD_DATA 0x0134 /* Data Load */ | |
61 | #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ | |
62 | ||
63 | /* MCi_MISC register defines */ | |
64 | #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) | |
65 | #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) | |
66 | #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ | |
67 | #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ | |
68 | #define MCI_MISC_ADDR_PHYS 2 /* physical address */ | |
69 | #define MCI_MISC_ADDR_MEM 3 /* memory address */ | |
70 | #define MCI_MISC_ADDR_GENERIC 7 /* generic */ | |
71 | ||
72 | /* CTL2 register defines */ | |
73 | #define MCI_CTL2_CMCI_EN (1ULL << 30) | |
74 | #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL | |
75 | ||
76 | #define MCJ_CTX_MASK 3 | |
77 | #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) | |
78 | #define MCJ_CTX_RANDOM 0 /* inject context: random */ | |
79 | #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ | |
80 | #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ | |
81 | #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ | |
82 | #define MCJ_EXCEPTION 0x8 /* raise as exception */ | |
a9093684 | 83 | #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ |
f51bde6f BP |
84 | |
85 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ | |
86 | ||
87 | /* Software defined banks */ | |
88 | #define MCE_EXTENDED_BANK 128 | |
89 | #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) | |
f51bde6f BP |
90 | |
91 | #define MCE_LOG_LEN 32 | |
92 | #define MCE_LOG_SIGNATURE "MACHINECHECK" | |
93 | ||
94 | /* | |
95 | * This structure contains all data related to the MCE log. Also | |
96 | * carries a signature to make it easier to find from external | |
97 | * debugging tools. Each entry is only valid when its finished flag | |
98 | * is set. | |
99 | */ | |
100 | struct mce_log { | |
101 | char signature[12]; /* "MACHINECHECK" */ | |
102 | unsigned len; /* = MCE_LOG_LEN */ | |
103 | unsigned next; | |
104 | unsigned flags; | |
105 | unsigned recordlen; /* length of struct mce */ | |
106 | struct mce entry[MCE_LOG_LEN]; | |
107 | }; | |
d203f0b8 BP |
108 | |
109 | struct mca_config { | |
110 | bool dont_log_ce; | |
7af19e4a BP |
111 | bool cmci_disabled; |
112 | bool ignore_ce; | |
1462594b BP |
113 | bool disabled; |
114 | bool ser; | |
115 | bool bios_cmci_threshold; | |
d203f0b8 | 116 | u8 banks; |
84c2559d | 117 | s8 bootlog; |
d203f0b8 | 118 | int tolerant; |
84c2559d | 119 | int monarch_timeout; |
7af19e4a | 120 | int panic_timeout; |
84c2559d | 121 | u32 rip_msr; |
d203f0b8 BP |
122 | }; |
123 | ||
bf80bbd7 | 124 | struct mce_vendor_flags { |
7559e13f AG |
125 | /* |
126 | * overflow recovery cpuid bit indicates that overflow | |
127 | * conditions are not fatal | |
128 | */ | |
129 | __u64 overflow_recov : 1, | |
130 | ||
131 | /* | |
132 | * SUCCOR stands for S/W UnCorrectable error COntainment | |
133 | * and Recovery. It indicates support for data poisoning | |
134 | * in HW and deferred error interrupts. | |
135 | */ | |
136 | succor : 1, | |
137 | __reserved_0 : 62; | |
bf80bbd7 AG |
138 | }; |
139 | extern struct mce_vendor_flags mce_flags; | |
140 | ||
7af19e4a | 141 | extern struct mca_config mca_cfg; |
3653ada5 BP |
142 | extern void mce_register_decode_chain(struct notifier_block *nb); |
143 | extern void mce_unregister_decode_chain(struct notifier_block *nb); | |
df39a2e4 | 144 | |
9e55e44e | 145 | #include <linux/percpu.h> |
60063497 | 146 | #include <linux/atomic.h> |
9e55e44e | 147 | |
c6978369 | 148 | extern int mce_p5_enabled; |
e2f43029 | 149 | |
58995d2d | 150 | #ifdef CONFIG_X86_MCE |
a2202aa2 | 151 | int mcheck_init(void); |
5e09954a | 152 | void mcheck_cpu_init(struct cpuinfo_x86 *c); |
43eaa2a1 | 153 | void mcheck_vendor_init_severity(void); |
58995d2d | 154 | #else |
a2202aa2 | 155 | static inline int mcheck_init(void) { return 0; } |
5e09954a | 156 | static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} |
43eaa2a1 | 157 | static inline void mcheck_vendor_init_severity(void) {} |
58995d2d HS |
158 | #endif |
159 | ||
9e55e44e HS |
160 | #ifdef CONFIG_X86_ANCIENT_MCE |
161 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c); | |
162 | void winchip_mcheck_init(struct cpuinfo_x86 *c); | |
c6978369 | 163 | static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } |
9e55e44e HS |
164 | #else |
165 | static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} | |
166 | static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} | |
c6978369 | 167 | static inline void enable_p5_mce(void) {} |
9e55e44e HS |
168 | #endif |
169 | ||
b5f2fa4e | 170 | void mce_setup(struct mce *m); |
e2f43029 | 171 | void mce_log(struct mce *m); |
d6126ef5 | 172 | DECLARE_PER_CPU(struct device *, mce_device); |
e2f43029 | 173 | |
41fdff32 | 174 | /* |
3ccdccfa AK |
175 | * Maximum banks number. |
176 | * This is the limit of the current register layout on | |
177 | * Intel CPUs. | |
41fdff32 | 178 | */ |
3ccdccfa | 179 | #define MAX_NR_BANKS 32 |
41fdff32 | 180 | |
e2f43029 TG |
181 | #ifdef CONFIG_X86_MCE_INTEL |
182 | void mce_intel_feature_init(struct cpuinfo_x86 *c); | |
88ccbedd AK |
183 | void cmci_clear(void); |
184 | void cmci_reenable(void); | |
7a0c819d | 185 | void cmci_rediscover(void); |
88ccbedd | 186 | void cmci_recheck(void); |
e2f43029 TG |
187 | #else |
188 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } | |
88ccbedd AK |
189 | static inline void cmci_clear(void) {} |
190 | static inline void cmci_reenable(void) {} | |
7a0c819d | 191 | static inline void cmci_rediscover(void) {} |
88ccbedd | 192 | static inline void cmci_recheck(void) {} |
e2f43029 TG |
193 | #endif |
194 | ||
195 | #ifdef CONFIG_X86_MCE_AMD | |
196 | void mce_amd_feature_init(struct cpuinfo_x86 *c); | |
197 | #else | |
198 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } | |
199 | #endif | |
200 | ||
38736072 | 201 | int mce_available(struct cpuinfo_x86 *c); |
88ccbedd | 202 | |
01ca79f1 | 203 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
ca84f696 | 204 | DECLARE_PER_CPU(unsigned, mce_poll_count); |
01ca79f1 | 205 | |
ee031c31 AK |
206 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
207 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); | |
208 | ||
b79109c3 | 209 | enum mcp_flags { |
3f2f0680 BP |
210 | MCP_TIMESTAMP = BIT(0), /* log time stamp */ |
211 | MCP_UC = BIT(1), /* log uncorrected errors */ | |
212 | MCP_DONTLOG = BIT(2), /* only clear, don't log */ | |
b79109c3 | 213 | }; |
3f2f0680 | 214 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
b79109c3 | 215 | |
9ff36ee9 | 216 | int mce_notify_irq(void); |
e2f43029 | 217 | |
ea149b36 | 218 | DECLARE_PER_CPU(struct mce, injectm); |
66f5ddf3 TL |
219 | |
220 | extern void register_mce_write_callback(ssize_t (*)(struct file *filp, | |
221 | const char __user *ubuf, | |
222 | size_t usize, loff_t *off)); | |
ea149b36 | 223 | |
c3d1fb56 NR |
224 | /* Disable CMCI/polling for MCA bank claimed by firmware */ |
225 | extern void mce_disable_bank(int bank); | |
226 | ||
58995d2d HS |
227 | /* |
228 | * Exception handler | |
229 | */ | |
230 | ||
231 | /* Call the installed machine check handler for this CPU setup. */ | |
232 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); | |
233 | void do_machine_check(struct pt_regs *, long); | |
234 | ||
235 | /* | |
236 | * Threshold handler | |
237 | */ | |
e2f43029 | 238 | |
b2762686 | 239 | extern void (*mce_threshold_vector)(void); |
58995d2d | 240 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
b2762686 | 241 | |
24fd78a8 AG |
242 | /* Deferred error interrupt handler */ |
243 | extern void (*deferred_error_int_vector)(void); | |
244 | ||
e8ce2c5e HS |
245 | /* |
246 | * Thermal handler | |
247 | */ | |
248 | ||
e8ce2c5e HS |
249 | void intel_init_thermal(struct cpuinfo_x86 *c); |
250 | ||
e8ce2c5e | 251 | void mce_log_therm_throt_event(__u64 status); |
a2202aa2 | 252 | |
9e76a97e D |
253 | /* Interrupt Handler for core thermal thresholds */ |
254 | extern int (*platform_thermal_notify)(__u64 msr_val); | |
255 | ||
25cdce17 SP |
256 | /* Interrupt Handler for package thermal thresholds */ |
257 | extern int (*platform_thermal_package_notify)(__u64 msr_val); | |
258 | ||
259 | /* Callback support of rate control, return true, if | |
260 | * callback has rate control */ | |
261 | extern bool (*platform_thermal_package_rate_control)(void); | |
262 | ||
a2202aa2 YW |
263 | #ifdef CONFIG_X86_THERMAL_VECTOR |
264 | extern void mcheck_intel_therm_init(void); | |
265 | #else | |
266 | static inline void mcheck_intel_therm_init(void) { } | |
267 | #endif | |
268 | ||
d334a491 HY |
269 | /* |
270 | * Used by APEI to report memory error via /dev/mcelog | |
271 | */ | |
272 | ||
273 | struct cper_sec_mem_err; | |
274 | extern void apei_mce_report_mem_error(int corrected, | |
275 | struct cper_sec_mem_err *mem_err); | |
276 | ||
1965aae3 | 277 | #endif /* _ASM_X86_MCE_H */ |