[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / microcode.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_MICROCODE_H
#define _ASM_X86_MICROCODE_H

#include <asm/cpu.h>
#include <linux/earlycpio.h>
#include <linux/initrd.h>

#define native_rdmsr(msr, val1, val2)			\
do {							\
	u64 __val = __rdmsr((msr));			\
	(void)((val1) = (u32)__val);			\
	(void)((val2) = (u32)(__val >> 32));		\
} while (0)

#define native_wrmsr(msr, low, high)			\
	__wrmsr(msr, low, high)

#define native_wrmsrl(msr, val)				\
	__wrmsr((msr), (u32)((u64)(val)),		\
		       (u32)((u64)(val) >> 32))

struct ucode_patch {
	struct list_head plist;
	void *data;		/* Intel uses only this one */
	u32 patch_id;
	u16 equiv_cpu;
};

extern struct list_head microcode_cache;

struct cpu_signature {
	unsigned int sig;
	unsigned int pf;
	unsigned int rev;
};

struct device;

enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };

struct microcode_ops {
	enum ucode_state (*request_microcode_user) (int cpu,
				const void __user *buf, size_t size);

	enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
						  bool refresh_fw);

	void (*microcode_fini_cpu) (int cpu);

	/*
	 * The generic 'microcode_core' part guarantees that
	 * the callbacks below run on a target cpu when they
	 * are being called.
	 * See also the "Synchronization" section in microcode_core.c.
	 */
	int (*apply_microcode) (int cpu);
	int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
};

struct ucode_cpu_info {
	struct cpu_signature	cpu_sig;
	int			valid;
	void			*mc;
};
extern struct ucode_cpu_info ucode_cpu_info[];
struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);

#ifdef CONFIG_MICROCODE_INTEL
extern struct microcode_ops * __init init_intel_microcode(void);
#else
static inline struct microcode_ops * __init init_intel_microcode(void)
{
	return NULL;
}
#endif /* CONFIG_MICROCODE_INTEL */

#ifdef CONFIG_MICROCODE_AMD
extern struct microcode_ops * __init init_amd_microcode(void);
extern void __exit exit_amd_microcode(void);
#else
static inline struct microcode_ops * __init init_amd_microcode(void)
{
	return NULL;
}
static inline void __exit exit_amd_microcode(void) {}
#endif

#define MAX_UCODE_COUNT 128

#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')

#define CPUID_IS(a, b, c, ebx, ecx, edx)	\
		(!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))

/*
 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
 * x86_cpuid_vendor() gets vendor id for BSP.
 *
 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
 * coding, we still use x86_cpuid_vendor() to get vendor id for AP.
 *
 * x86_cpuid_vendor() gets vendor information directly from CPUID.
 */
static inline int x86_cpuid_vendor(void)
{
	u32 eax = 0x00000000;
	u32 ebx, ecx = 0, edx;

	native_cpuid(&eax, &ebx, &ecx, &edx);

	if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
		return X86_VENDOR_INTEL;

	if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
		return X86_VENDOR_AMD;

	return X86_VENDOR_UNKNOWN;
}

static inline unsigned int x86_cpuid_family(void)
{
	u32 eax = 0x00000001;
	u32 ebx, ecx = 0, edx;

	native_cpuid(&eax, &ebx, &ecx, &edx);

	return x86_family(eax);
}

#ifdef CONFIG_MICROCODE
int __init microcode_init(void);
extern void __init load_ucode_bsp(void);
extern void load_ucode_ap(void);
void reload_early_microcode(void);
extern bool get_builtin_firmware(struct cpio_data *cd, const char *name);
extern bool initrd_gone;
#else
static inline int __init microcode_init(void)			{ return 0; };
static inline void __init load_ucode_bsp(void)			{ }
static inline void load_ucode_ap(void)				{ }
static inline void reload_early_microcode(void)			{ }
static inline bool
get_builtin_firmware(struct cpio_data *cd, const char *name)	{ return false; }
#endif

#endif /* _ASM_X86_MICROCODE_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_MICROCODE_H
1965aae3 PA	3	#define _ASM_X86_MICROCODE_H
d45de409	4
99f925ce	5	#include <asm/cpu.h>
760d765b	6	#include <linux/earlycpio.h>
5f9c01aa	7	#include <linux/initrd.h>
760d765b	8
e1b43e3f BP	9	#define native_rdmsr(msr, val1, val2) \
e1b43e3f BP	10	do { \
0c12d18a	11	u64 __val = __rdmsr((msr)); \
e1b43e3f BP	12	(void)((val1) = (u32)__val); \
	13	(void)((val2) = (u32)(__val >> 32)); \
	14	} while (0)
	15
	16	#define native_wrmsr(msr, low, high) \
0c12d18a	17	__wrmsr(msr, low, high)
e1b43e3f BP	18
e1b43e3f BP	19	#define native_wrmsrl(msr, val) \
0c12d18a BP	20	__wrmsr((msr), (u32)((u64)(val)), \
0c12d18a BP	21	(u32)((u64)(val) >> 32))
e1b43e3f	22
058dc498 BP	23	struct ucode_patch {
	24	struct list_head plist;
	25	void data; / Intel uses only this one */
	26	u32 patch_id;
	27	u16 equiv_cpu;
	28	};
	29
	30	extern struct list_head microcode_cache;
	31
18dbc916 DA	32	struct cpu_signature {
	33	unsigned int sig;
	34	unsigned int pf;
	35	unsigned int rev;
	36	};
8d86f390	37
a0a29b62	38	struct device;
d45de409	39
871b72dd DA	40	enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };
871b72dd DA	41
26bf7a48	42	struct microcode_ops {
871b72dd DA	43	enum ucode_state (*request_microcode_user) (int cpu,
871b72dd DA	44	const void __user *buf, size_t size);
a0a29b62	45
48e30685 BP	46	enum ucode_state (request_microcode_fw) (int cpu, struct device ,
48e30685 BP	47	bool refresh_fw);
a0a29b62	48
a0a29b62	49	void (*microcode_fini_cpu) (int cpu);
871b72dd DA	50
	51	/*
	52	* The generic 'microcode_core' part guarantees that
	53	* the callbacks below run on a target cpu when they
	54	* are being called.
	55	* See also the "Synchronization" section in microcode_core.c.
	56	*/
	57	int (*apply_microcode) (int cpu);
	58	int (collect_cpu_info) (int cpu, struct cpu_signature csig);
26bf7a48 PO	59	};
26bf7a48 PO	60
d45de409	61	struct ucode_cpu_info {
871b72dd DA	62	struct cpu_signature cpu_sig;
	63	int valid;
	64	void *mc;
c3b71bce	65	};
d45de409	66	extern struct ucode_cpu_info ucode_cpu_info[];
06b8534c	67	struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);
d45de409	68
18dbc916 DA	69	#ifdef CONFIG_MICROCODE_INTEL
	70	extern struct microcode_ops * __init init_intel_microcode(void);
	71	#else
	72	static inline struct microcode_ops * __init init_intel_microcode(void)
	73	{
	74	return NULL;
	75	}
	76	#endif /* CONFIG_MICROCODE_INTEL */
	77
	78	#ifdef CONFIG_MICROCODE_AMD
	79	extern struct microcode_ops * __init init_amd_microcode(void);
f72c1a57	80	extern void __exit exit_amd_microcode(void);
18dbc916 DA	81	#else
	82	static inline struct microcode_ops * __init init_amd_microcode(void)
	83	{
	84	return NULL;
	85	}
f72c1a57	86	static inline void __exit exit_amd_microcode(void) {}
18dbc916 DA	87	#endif
18dbc916 DA	88
a8ebf6d1	89	#define MAX_UCODE_COUNT 128
58ce8d6d BP	90
	91	#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
	92	#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
	93	#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
	94	#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
	95	#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
	96	#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
	97	#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
	98
	99	#define CPUID_IS(a, b, c, ebx, ecx, edx) \
	100	(!((ebx ^ (a))\|(edx ^ (b))\|(ecx ^ (c))))
	101
	102	/*
	103	* In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
99f925ce	104	* x86_cpuid_vendor() gets vendor id for BSP.
58ce8d6d BP	105	*
58ce8d6d BP	106	* In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
99f925ce	107	* coding, we still use x86_cpuid_vendor() to get vendor id for AP.
58ce8d6d	108	*
99f925ce	109	* x86_cpuid_vendor() gets vendor information directly from CPUID.
58ce8d6d	110	*/
99f925ce	111	static inline int x86_cpuid_vendor(void)
58ce8d6d BP	112	{
	113	u32 eax = 0x00000000;
	114	u32 ebx, ecx = 0, edx;
	115
	116	native_cpuid(&eax, &ebx, &ecx, &edx);
	117
	118	if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
	119	return X86_VENDOR_INTEL;
	120
	121	if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
	122	return X86_VENDOR_AMD;
	123
	124	return X86_VENDOR_UNKNOWN;
	125	}
	126
99f925ce	127	static inline unsigned int x86_cpuid_family(void)
58ce8d6d BP	128	{
	129	u32 eax = 0x00000001;
	130	u32 ebx, ecx = 0, edx;
	131
	132	native_cpuid(&eax, &ebx, &ecx, &edx);
	133
99f925ce	134	return x86_family(eax);
58ce8d6d BP	135	}
58ce8d6d BP	136
fe055896	137	#ifdef CONFIG_MICROCODE
f5bdfefb	138	int __init microcode_init(void);
a8ebf6d1	139	extern void __init load_ucode_bsp(void);
148f9bb8	140	extern void load_ucode_ap(void);
fbae4ba8	141	void reload_early_microcode(void);
760d765b	142	extern bool get_builtin_firmware(struct cpio_data cd, const char name);
24c25032	143	extern bool initrd_gone;
a8ebf6d1	144	#else
f5bdfefb	145	static inline int __init microcode_init(void) { return 0; };
fe055896 BP	146	static inline void __init load_ucode_bsp(void) { }
fe055896 BP	147	static inline void load_ucode_ap(void) { }
fe055896 BP	148	static inline void reload_early_microcode(void) { }
	149	static inline bool
	150	get_builtin_firmware(struct cpio_data cd, const char name) { return false; }
a8ebf6d1	151	#endif
5f9c01aa	152
1965aae3	153	#endif /* _ASM_X86_MICROCODE_H */