[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / microcode.h

#ifndef _ASM_X86_MICROCODE_H
#define _ASM_X86_MICROCODE_H

#include <asm/cpu.h>
#include <linux/earlycpio.h>
#include <linux/initrd.h>

#define native_rdmsr(msr, val1, val2)			\
do {							\
	u64 __val = __rdmsr((msr));			\
	(void)((val1) = (u32)__val);			\
	(void)((val2) = (u32)(__val >> 32));		\
} while (0)

#define native_wrmsr(msr, low, high)			\
	__wrmsr(msr, low, high)

#define native_wrmsrl(msr, val)				\
	__wrmsr((msr), (u32)((u64)(val)),		\
		       (u32)((u64)(val) >> 32))

struct ucode_patch {
	struct list_head plist;
	void *data;		/* Intel uses only this one */
	u32 patch_id;
	u16 equiv_cpu;
};

extern struct list_head microcode_cache;

struct cpu_signature {
	unsigned int sig;
	unsigned int pf;
	unsigned int rev;
};

struct device;

enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };

struct microcode_ops {
	enum ucode_state (*request_microcode_user) (int cpu,
				const void __user *buf, size_t size);

	enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
						  bool refresh_fw);

	void (*microcode_fini_cpu) (int cpu);

	/*
	 * The generic 'microcode_core' part guarantees that
	 * the callbacks below run on a target cpu when they
	 * are being called.
	 * See also the "Synchronization" section in microcode_core.c.
	 */
	int (*apply_microcode) (int cpu);
	int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
};

struct ucode_cpu_info {
	struct cpu_signature	cpu_sig;
	int			valid;
	void			*mc;
};
extern struct ucode_cpu_info ucode_cpu_info[];
struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);

#ifdef CONFIG_MICROCODE_INTEL
extern struct microcode_ops * __init init_intel_microcode(void);
#else
static inline struct microcode_ops * __init init_intel_microcode(void)
{
	return NULL;
}
#endif /* CONFIG_MICROCODE_INTEL */

#ifdef CONFIG_MICROCODE_AMD
extern struct microcode_ops * __init init_amd_microcode(void);
extern void __exit exit_amd_microcode(void);
#else
static inline struct microcode_ops * __init init_amd_microcode(void)
{
	return NULL;
}
static inline void __exit exit_amd_microcode(void) {}
#endif

#define MAX_UCODE_COUNT 128

#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')

#define CPUID_IS(a, b, c, ebx, ecx, edx)	\
		(!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))

/*
 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
 * x86_cpuid_vendor() gets vendor id for BSP.
 *
 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
 * coding, we still use x86_cpuid_vendor() to get vendor id for AP.
 *
 * x86_cpuid_vendor() gets vendor information directly from CPUID.
 */
static inline int x86_cpuid_vendor(void)
{
	u32 eax = 0x00000000;
	u32 ebx, ecx = 0, edx;

	native_cpuid(&eax, &ebx, &ecx, &edx);

	if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
		return X86_VENDOR_INTEL;

	if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
		return X86_VENDOR_AMD;

	return X86_VENDOR_UNKNOWN;
}

static inline unsigned int x86_cpuid_family(void)
{
	u32 eax = 0x00000001;
	u32 ebx, ecx = 0, edx;

	native_cpuid(&eax, &ebx, &ecx, &edx);

	return x86_family(eax);
}

#ifdef CONFIG_MICROCODE
int __init microcode_init(void);
extern void __init load_ucode_bsp(void);
extern void load_ucode_ap(void);
void reload_early_microcode(void);
extern bool get_builtin_firmware(struct cpio_data *cd, const char *name);
extern bool initrd_gone;
#else
static inline int __init microcode_init(void)			{ return 0; };
static inline void __init load_ucode_bsp(void)			{ }
static inline void load_ucode_ap(void)				{ }
static inline void reload_early_microcode(void)			{ }
static inline bool
get_builtin_firmware(struct cpio_data *cd, const char *name)	{ return false; }
#endif

#endif /* _ASM_X86_MICROCODE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MICROCODE_H
1965aae3 PA	2	#define _ASM_X86_MICROCODE_H
d45de409	3
99f925ce	4	#include <asm/cpu.h>
760d765b	5	#include <linux/earlycpio.h>
5f9c01aa	6	#include <linux/initrd.h>
760d765b	7
e1b43e3f BP	8	#define native_rdmsr(msr, val1, val2) \
e1b43e3f BP	9	do { \
0c12d18a	10	u64 __val = __rdmsr((msr)); \
e1b43e3f BP	11	(void)((val1) = (u32)__val); \
	12	(void)((val2) = (u32)(__val >> 32)); \
	13	} while (0)
	14
	15	#define native_wrmsr(msr, low, high) \
0c12d18a	16	__wrmsr(msr, low, high)
e1b43e3f BP	17
e1b43e3f BP	18	#define native_wrmsrl(msr, val) \
0c12d18a BP	19	__wrmsr((msr), (u32)((u64)(val)), \
0c12d18a BP	20	(u32)((u64)(val) >> 32))
e1b43e3f	21
058dc498 BP	22	struct ucode_patch {
	23	struct list_head plist;
	24	void data; / Intel uses only this one */
	25	u32 patch_id;
	26	u16 equiv_cpu;
	27	};
	28
	29	extern struct list_head microcode_cache;
	30
18dbc916 DA	31	struct cpu_signature {
	32	unsigned int sig;
	33	unsigned int pf;
	34	unsigned int rev;
	35	};
8d86f390	36
a0a29b62	37	struct device;
d45de409	38
871b72dd DA	39	enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };
871b72dd DA	40
26bf7a48	41	struct microcode_ops {
871b72dd DA	42	enum ucode_state (*request_microcode_user) (int cpu,
871b72dd DA	43	const void __user *buf, size_t size);
a0a29b62	44
48e30685 BP	45	enum ucode_state (request_microcode_fw) (int cpu, struct device ,
48e30685 BP	46	bool refresh_fw);
a0a29b62	47
a0a29b62	48	void (*microcode_fini_cpu) (int cpu);
871b72dd DA	49
	50	/*
	51	* The generic 'microcode_core' part guarantees that
	52	* the callbacks below run on a target cpu when they
	53	* are being called.
	54	* See also the "Synchronization" section in microcode_core.c.
	55	*/
	56	int (*apply_microcode) (int cpu);
	57	int (collect_cpu_info) (int cpu, struct cpu_signature csig);
26bf7a48 PO	58	};
26bf7a48 PO	59
d45de409	60	struct ucode_cpu_info {
871b72dd DA	61	struct cpu_signature cpu_sig;
	62	int valid;
	63	void *mc;
c3b71bce	64	};
d45de409	65	extern struct ucode_cpu_info ucode_cpu_info[];
06b8534c	66	struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);
d45de409	67
18dbc916 DA	68	#ifdef CONFIG_MICROCODE_INTEL
	69	extern struct microcode_ops * __init init_intel_microcode(void);
	70	#else
	71	static inline struct microcode_ops * __init init_intel_microcode(void)
	72	{
	73	return NULL;
	74	}
	75	#endif /* CONFIG_MICROCODE_INTEL */
	76
	77	#ifdef CONFIG_MICROCODE_AMD
	78	extern struct microcode_ops * __init init_amd_microcode(void);
f72c1a57	79	extern void __exit exit_amd_microcode(void);
18dbc916 DA	80	#else
	81	static inline struct microcode_ops * __init init_amd_microcode(void)
	82	{
	83	return NULL;
	84	}
f72c1a57	85	static inline void __exit exit_amd_microcode(void) {}
18dbc916 DA	86	#endif
18dbc916 DA	87
a8ebf6d1	88	#define MAX_UCODE_COUNT 128
58ce8d6d BP	89
	90	#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
	91	#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
	92	#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
	93	#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
	94	#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
	95	#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
	96	#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
	97
	98	#define CPUID_IS(a, b, c, ebx, ecx, edx) \
	99	(!((ebx ^ (a))\|(edx ^ (b))\|(ecx ^ (c))))
	100
	101	/*
	102	* In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
99f925ce	103	* x86_cpuid_vendor() gets vendor id for BSP.
58ce8d6d BP	104	*
58ce8d6d BP	105	* In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
99f925ce	106	* coding, we still use x86_cpuid_vendor() to get vendor id for AP.
58ce8d6d	107	*
99f925ce	108	* x86_cpuid_vendor() gets vendor information directly from CPUID.
58ce8d6d	109	*/
99f925ce	110	static inline int x86_cpuid_vendor(void)
58ce8d6d BP	111	{
	112	u32 eax = 0x00000000;
	113	u32 ebx, ecx = 0, edx;
	114
	115	native_cpuid(&eax, &ebx, &ecx, &edx);
	116
	117	if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
	118	return X86_VENDOR_INTEL;
	119
	120	if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
	121	return X86_VENDOR_AMD;
	122
	123	return X86_VENDOR_UNKNOWN;
	124	}
	125
99f925ce	126	static inline unsigned int x86_cpuid_family(void)
58ce8d6d BP	127	{
	128	u32 eax = 0x00000001;
	129	u32 ebx, ecx = 0, edx;
	130
	131	native_cpuid(&eax, &ebx, &ecx, &edx);
	132
99f925ce	133	return x86_family(eax);
58ce8d6d BP	134	}
58ce8d6d BP	135
fe055896	136	#ifdef CONFIG_MICROCODE
f5bdfefb	137	int __init microcode_init(void);
a8ebf6d1	138	extern void __init load_ucode_bsp(void);
148f9bb8	139	extern void load_ucode_ap(void);
fbae4ba8	140	void reload_early_microcode(void);
760d765b	141	extern bool get_builtin_firmware(struct cpio_data cd, const char name);
24c25032	142	extern bool initrd_gone;
a8ebf6d1	143	#else
f5bdfefb	144	static inline int __init microcode_init(void) { return 0; };
fe055896 BP	145	static inline void __init load_ucode_bsp(void) { }
fe055896 BP	146	static inline void load_ucode_ap(void) { }
fe055896 BP	147	static inline void reload_early_microcode(void) { }
	148	static inline bool
	149	get_builtin_firmware(struct cpio_data cd, const char name) { return false; }
a8ebf6d1	150	#endif
5f9c01aa	151
1965aae3	152	#endif /* _ASM_X86_MICROCODE_H */