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1965aae3 PA |
1 | #ifndef _ASM_X86_MICROCODE_H |
2 | #define _ASM_X86_MICROCODE_H | |
d45de409 | 3 | |
99f925ce | 4 | #include <asm/cpu.h> |
760d765b BP |
5 | #include <linux/earlycpio.h> |
6 | ||
e1b43e3f BP |
7 | #define native_rdmsr(msr, val1, val2) \ |
8 | do { \ | |
9 | u64 __val = native_read_msr((msr)); \ | |
10 | (void)((val1) = (u32)__val); \ | |
11 | (void)((val2) = (u32)(__val >> 32)); \ | |
12 | } while (0) | |
13 | ||
14 | #define native_wrmsr(msr, low, high) \ | |
15 | native_write_msr(msr, low, high) | |
16 | ||
17 | #define native_wrmsrl(msr, val) \ | |
18 | native_write_msr((msr), \ | |
19 | (u32)((u64)(val)), \ | |
20 | (u32)((u64)(val) >> 32)) | |
21 | ||
18dbc916 DA |
22 | struct cpu_signature { |
23 | unsigned int sig; | |
24 | unsigned int pf; | |
25 | unsigned int rev; | |
26 | }; | |
8d86f390 | 27 | |
a0a29b62 | 28 | struct device; |
d45de409 | 29 | |
871b72dd DA |
30 | enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND }; |
31 | ||
26bf7a48 | 32 | struct microcode_ops { |
871b72dd DA |
33 | enum ucode_state (*request_microcode_user) (int cpu, |
34 | const void __user *buf, size_t size); | |
a0a29b62 | 35 | |
48e30685 BP |
36 | enum ucode_state (*request_microcode_fw) (int cpu, struct device *, |
37 | bool refresh_fw); | |
a0a29b62 | 38 | |
a0a29b62 | 39 | void (*microcode_fini_cpu) (int cpu); |
871b72dd DA |
40 | |
41 | /* | |
42 | * The generic 'microcode_core' part guarantees that | |
43 | * the callbacks below run on a target cpu when they | |
44 | * are being called. | |
45 | * See also the "Synchronization" section in microcode_core.c. | |
46 | */ | |
47 | int (*apply_microcode) (int cpu); | |
48 | int (*collect_cpu_info) (int cpu, struct cpu_signature *csig); | |
26bf7a48 PO |
49 | }; |
50 | ||
d45de409 | 51 | struct ucode_cpu_info { |
871b72dd DA |
52 | struct cpu_signature cpu_sig; |
53 | int valid; | |
54 | void *mc; | |
c3b71bce | 55 | }; |
d45de409 DA |
56 | extern struct ucode_cpu_info ucode_cpu_info[]; |
57 | ||
9a2bc335 BP |
58 | #ifdef CONFIG_MICROCODE |
59 | int __init microcode_init(void); | |
60 | #else | |
61 | static inline int __init microcode_init(void) { return 0; }; | |
62 | #endif | |
63 | ||
18dbc916 DA |
64 | #ifdef CONFIG_MICROCODE_INTEL |
65 | extern struct microcode_ops * __init init_intel_microcode(void); | |
66 | #else | |
67 | static inline struct microcode_ops * __init init_intel_microcode(void) | |
68 | { | |
69 | return NULL; | |
70 | } | |
71 | #endif /* CONFIG_MICROCODE_INTEL */ | |
72 | ||
73 | #ifdef CONFIG_MICROCODE_AMD | |
74 | extern struct microcode_ops * __init init_amd_microcode(void); | |
f72c1a57 | 75 | extern void __exit exit_amd_microcode(void); |
18dbc916 DA |
76 | #else |
77 | static inline struct microcode_ops * __init init_amd_microcode(void) | |
78 | { | |
79 | return NULL; | |
80 | } | |
f72c1a57 | 81 | static inline void __exit exit_amd_microcode(void) {} |
18dbc916 DA |
82 | #endif |
83 | ||
a8ebf6d1 | 84 | #define MAX_UCODE_COUNT 128 |
58ce8d6d BP |
85 | |
86 | #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) | |
87 | #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') | |
88 | #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') | |
89 | #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') | |
90 | #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') | |
91 | #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') | |
92 | #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') | |
93 | ||
94 | #define CPUID_IS(a, b, c, ebx, ecx, edx) \ | |
95 | (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c)))) | |
96 | ||
97 | /* | |
98 | * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. | |
99f925ce | 99 | * x86_cpuid_vendor() gets vendor id for BSP. |
58ce8d6d BP |
100 | * |
101 | * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify | |
99f925ce | 102 | * coding, we still use x86_cpuid_vendor() to get vendor id for AP. |
58ce8d6d | 103 | * |
99f925ce | 104 | * x86_cpuid_vendor() gets vendor information directly from CPUID. |
58ce8d6d | 105 | */ |
99f925ce | 106 | static inline int x86_cpuid_vendor(void) |
58ce8d6d BP |
107 | { |
108 | u32 eax = 0x00000000; | |
109 | u32 ebx, ecx = 0, edx; | |
110 | ||
111 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
112 | ||
113 | if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) | |
114 | return X86_VENDOR_INTEL; | |
115 | ||
116 | if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) | |
117 | return X86_VENDOR_AMD; | |
118 | ||
119 | return X86_VENDOR_UNKNOWN; | |
120 | } | |
121 | ||
99f925ce | 122 | static inline unsigned int x86_cpuid_family(void) |
58ce8d6d BP |
123 | { |
124 | u32 eax = 0x00000001; | |
125 | u32 ebx, ecx = 0, edx; | |
126 | ||
127 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
128 | ||
99f925ce | 129 | return x86_family(eax); |
58ce8d6d BP |
130 | } |
131 | ||
fe055896 | 132 | #ifdef CONFIG_MICROCODE |
a8ebf6d1 | 133 | extern void __init load_ucode_bsp(void); |
148f9bb8 | 134 | extern void load_ucode_ap(void); |
a8ebf6d1 | 135 | extern int __init save_microcode_in_initrd(void); |
fbae4ba8 | 136 | void reload_early_microcode(void); |
760d765b | 137 | extern bool get_builtin_firmware(struct cpio_data *cd, const char *name); |
a8ebf6d1 | 138 | #else |
fe055896 BP |
139 | static inline void __init load_ucode_bsp(void) { } |
140 | static inline void load_ucode_ap(void) { } | |
141 | static inline int __init save_microcode_in_initrd(void) { return 0; } | |
142 | static inline void reload_early_microcode(void) { } | |
143 | static inline bool | |
144 | get_builtin_firmware(struct cpio_data *cd, const char *name) { return false; } | |
a8ebf6d1 | 145 | #endif |
1965aae3 | 146 | #endif /* _ASM_X86_MICROCODE_H */ |