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1965aae3 PA |
1 | #ifndef _ASM_X86_MICROCODE_H |
2 | #define _ASM_X86_MICROCODE_H | |
d45de409 | 3 | |
99f925ce | 4 | #include <asm/cpu.h> |
760d765b | 5 | #include <linux/earlycpio.h> |
5f9c01aa | 6 | #include <linux/initrd.h> |
760d765b | 7 | |
e1b43e3f BP |
8 | #define native_rdmsr(msr, val1, val2) \ |
9 | do { \ | |
10 | u64 __val = native_read_msr((msr)); \ | |
11 | (void)((val1) = (u32)__val); \ | |
12 | (void)((val2) = (u32)(__val >> 32)); \ | |
13 | } while (0) | |
14 | ||
15 | #define native_wrmsr(msr, low, high) \ | |
16 | native_write_msr(msr, low, high) | |
17 | ||
18 | #define native_wrmsrl(msr, val) \ | |
19 | native_write_msr((msr), \ | |
20 | (u32)((u64)(val)), \ | |
21 | (u32)((u64)(val) >> 32)) | |
22 | ||
058dc498 BP |
23 | struct ucode_patch { |
24 | struct list_head plist; | |
25 | void *data; /* Intel uses only this one */ | |
26 | u32 patch_id; | |
27 | u16 equiv_cpu; | |
28 | }; | |
29 | ||
30 | extern struct list_head microcode_cache; | |
31 | ||
18dbc916 DA |
32 | struct cpu_signature { |
33 | unsigned int sig; | |
34 | unsigned int pf; | |
35 | unsigned int rev; | |
36 | }; | |
8d86f390 | 37 | |
a0a29b62 | 38 | struct device; |
d45de409 | 39 | |
871b72dd DA |
40 | enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND }; |
41 | ||
26bf7a48 | 42 | struct microcode_ops { |
871b72dd DA |
43 | enum ucode_state (*request_microcode_user) (int cpu, |
44 | const void __user *buf, size_t size); | |
a0a29b62 | 45 | |
48e30685 BP |
46 | enum ucode_state (*request_microcode_fw) (int cpu, struct device *, |
47 | bool refresh_fw); | |
a0a29b62 | 48 | |
a0a29b62 | 49 | void (*microcode_fini_cpu) (int cpu); |
871b72dd DA |
50 | |
51 | /* | |
52 | * The generic 'microcode_core' part guarantees that | |
53 | * the callbacks below run on a target cpu when they | |
54 | * are being called. | |
55 | * See also the "Synchronization" section in microcode_core.c. | |
56 | */ | |
57 | int (*apply_microcode) (int cpu); | |
58 | int (*collect_cpu_info) (int cpu, struct cpu_signature *csig); | |
26bf7a48 PO |
59 | }; |
60 | ||
d45de409 | 61 | struct ucode_cpu_info { |
871b72dd DA |
62 | struct cpu_signature cpu_sig; |
63 | int valid; | |
64 | void *mc; | |
c3b71bce | 65 | }; |
d45de409 DA |
66 | extern struct ucode_cpu_info ucode_cpu_info[]; |
67 | ||
18dbc916 DA |
68 | #ifdef CONFIG_MICROCODE_INTEL |
69 | extern struct microcode_ops * __init init_intel_microcode(void); | |
70 | #else | |
71 | static inline struct microcode_ops * __init init_intel_microcode(void) | |
72 | { | |
73 | return NULL; | |
74 | } | |
75 | #endif /* CONFIG_MICROCODE_INTEL */ | |
76 | ||
77 | #ifdef CONFIG_MICROCODE_AMD | |
78 | extern struct microcode_ops * __init init_amd_microcode(void); | |
f72c1a57 | 79 | extern void __exit exit_amd_microcode(void); |
18dbc916 DA |
80 | #else |
81 | static inline struct microcode_ops * __init init_amd_microcode(void) | |
82 | { | |
83 | return NULL; | |
84 | } | |
f72c1a57 | 85 | static inline void __exit exit_amd_microcode(void) {} |
18dbc916 DA |
86 | #endif |
87 | ||
a8ebf6d1 | 88 | #define MAX_UCODE_COUNT 128 |
58ce8d6d BP |
89 | |
90 | #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) | |
91 | #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') | |
92 | #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') | |
93 | #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') | |
94 | #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') | |
95 | #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') | |
96 | #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') | |
97 | ||
98 | #define CPUID_IS(a, b, c, ebx, ecx, edx) \ | |
99 | (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c)))) | |
100 | ||
101 | /* | |
102 | * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. | |
99f925ce | 103 | * x86_cpuid_vendor() gets vendor id for BSP. |
58ce8d6d BP |
104 | * |
105 | * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify | |
99f925ce | 106 | * coding, we still use x86_cpuid_vendor() to get vendor id for AP. |
58ce8d6d | 107 | * |
99f925ce | 108 | * x86_cpuid_vendor() gets vendor information directly from CPUID. |
58ce8d6d | 109 | */ |
99f925ce | 110 | static inline int x86_cpuid_vendor(void) |
58ce8d6d BP |
111 | { |
112 | u32 eax = 0x00000000; | |
113 | u32 ebx, ecx = 0, edx; | |
114 | ||
115 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
116 | ||
117 | if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) | |
118 | return X86_VENDOR_INTEL; | |
119 | ||
120 | if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) | |
121 | return X86_VENDOR_AMD; | |
122 | ||
123 | return X86_VENDOR_UNKNOWN; | |
124 | } | |
125 | ||
99f925ce | 126 | static inline unsigned int x86_cpuid_family(void) |
58ce8d6d BP |
127 | { |
128 | u32 eax = 0x00000001; | |
129 | u32 ebx, ecx = 0, edx; | |
130 | ||
131 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
132 | ||
99f925ce | 133 | return x86_family(eax); |
58ce8d6d BP |
134 | } |
135 | ||
fe055896 | 136 | #ifdef CONFIG_MICROCODE |
f5bdfefb | 137 | int __init microcode_init(void); |
a8ebf6d1 | 138 | extern void __init load_ucode_bsp(void); |
148f9bb8 | 139 | extern void load_ucode_ap(void); |
fbae4ba8 | 140 | void reload_early_microcode(void); |
760d765b | 141 | extern bool get_builtin_firmware(struct cpio_data *cd, const char *name); |
a8ebf6d1 | 142 | #else |
f5bdfefb | 143 | static inline int __init microcode_init(void) { return 0; }; |
fe055896 BP |
144 | static inline void __init load_ucode_bsp(void) { } |
145 | static inline void load_ucode_ap(void) { } | |
fe055896 BP |
146 | static inline void reload_early_microcode(void) { } |
147 | static inline bool | |
148 | get_builtin_firmware(struct cpio_data *cd, const char *name) { return false; } | |
a8ebf6d1 | 149 | #endif |
5f9c01aa | 150 | |
1965aae3 | 151 | #endif /* _ASM_X86_MICROCODE_H */ |