[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / msr-index.h

#ifndef _ASM_X86_MSR_INDEX_H
#define _ASM_X86_MSR_INDEX_H

/* CPU model specific register (MSR) numbers */

/* x86-64 specific MSRs */
#define MSR_EFER		0xc0000080 /* extended feature register */
#define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
#define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
#define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
#define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
#define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
#define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
#define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
#define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */

/* EFER bits: */
#define _EFER_SCE		0  /* SYSCALL/SYSRET */
#define _EFER_LME		8  /* Long mode enable */
#define _EFER_LMA		10 /* Long mode active (read-only) */
#define _EFER_NX		11 /* No execute enable */
#define _EFER_SVME		12 /* Enable virtualization */
#define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */
#define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */

#define EFER_SCE		(1<<_EFER_SCE)
#define EFER_LME		(1<<_EFER_LME)
#define EFER_LMA		(1<<_EFER_LMA)
#define EFER_NX			(1<<_EFER_NX)
#define EFER_SVME		(1<<_EFER_SVME)
#define EFER_LMSLE		(1<<_EFER_LMSLE)
#define EFER_FFXSR		(1<<_EFER_FFXSR)

/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_PERFCTR0		0x000000c1
#define MSR_IA32_PERFCTR1		0x000000c2
#define MSR_FSB_FREQ			0x000000cd

#define MSR_NHM_SNB_PKG_CST_CFG_CTL	0x000000e2
#define NHM_C3_AUTO_DEMOTE		(1UL << 25)
#define NHM_C1_AUTO_DEMOTE		(1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE		(1UL << 25)

#define MSR_MTRRcap			0x000000fe
#define MSR_IA32_BBL_CR_CTL		0x00000119
#define MSR_IA32_BBL_CR_CTL3		0x0000011e

#define MSR_IA32_SYSENTER_CS		0x00000174
#define MSR_IA32_SYSENTER_ESP		0x00000175
#define MSR_IA32_SYSENTER_EIP		0x00000176

#define MSR_IA32_MCG_CAP		0x00000179
#define MSR_IA32_MCG_STATUS		0x0000017a
#define MSR_IA32_MCG_CTL		0x0000017b

#define MSR_OFFCORE_RSP_0		0x000001a6
#define MSR_OFFCORE_RSP_1		0x000001a7

#define MSR_LBR_SELECT			0x000001c8
#define MSR_LBR_TOS			0x000001c9
#define MSR_LBR_NHM_FROM		0x00000680
#define MSR_LBR_NHM_TO			0x000006c0
#define MSR_LBR_CORE_FROM		0x00000040
#define MSR_LBR_CORE_TO			0x00000060

#define MSR_IA32_PEBS_ENABLE		0x000003f1
#define MSR_IA32_DS_AREA		0x00000600
#define MSR_IA32_PERF_CAPABILITIES	0x00000345

#define MSR_MTRRfix64K_00000		0x00000250
#define MSR_MTRRfix16K_80000		0x00000258
#define MSR_MTRRfix16K_A0000		0x00000259
#define MSR_MTRRfix4K_C0000		0x00000268
#define MSR_MTRRfix4K_C8000		0x00000269
#define MSR_MTRRfix4K_D0000		0x0000026a
#define MSR_MTRRfix4K_D8000		0x0000026b
#define MSR_MTRRfix4K_E0000		0x0000026c
#define MSR_MTRRfix4K_E8000		0x0000026d
#define MSR_MTRRfix4K_F0000		0x0000026e
#define MSR_MTRRfix4K_F8000		0x0000026f
#define MSR_MTRRdefType			0x000002ff

#define MSR_IA32_CR_PAT			0x00000277

#define MSR_IA32_DEBUGCTLMSR		0x000001d9
#define MSR_IA32_LASTBRANCHFROMIP	0x000001db
#define MSR_IA32_LASTBRANCHTOIP		0x000001dc
#define MSR_IA32_LASTINTFROMIP		0x000001dd
#define MSR_IA32_LASTINTTOIP		0x000001de

/* DEBUGCTLMSR bits (others vary by model): */
#define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
#define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */
#define DEBUGCTLMSR_TR			(1UL <<  6)
#define DEBUGCTLMSR_BTS			(1UL <<  7)
#define DEBUGCTLMSR_BTINT		(1UL <<  8)
#define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
#define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)

#define MSR_IA32_MC0_CTL		0x00000400
#define MSR_IA32_MC0_STATUS		0x00000401
#define MSR_IA32_MC0_ADDR		0x00000402
#define MSR_IA32_MC0_MISC		0x00000403

#define MSR_AMD64_MC0_MASK		0xc0010044

#define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))
#define MSR_IA32_MCx_STATUS(x)		(MSR_IA32_MC0_STATUS + 4*(x))
#define MSR_IA32_MCx_ADDR(x)		(MSR_IA32_MC0_ADDR + 4*(x))
#define MSR_IA32_MCx_MISC(x)		(MSR_IA32_MC0_MISC + 4*(x))

#define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))

/* These are consecutive and not in the normal 4er MCE bank block */
#define MSR_IA32_MC0_CTL2		0x00000280
#define MSR_IA32_MCx_CTL2(x)		(MSR_IA32_MC0_CTL2 + (x))

#define MSR_P6_PERFCTR0			0x000000c1
#define MSR_P6_PERFCTR1			0x000000c2
#define MSR_P6_EVNTSEL0			0x00000186
#define MSR_P6_EVNTSEL1			0x00000187

/* AMD64 MSRs. Not complete. See the architecture manual for a more
   complete list. */

#define MSR_AMD64_PATCH_LEVEL		0x0000008b
#define MSR_AMD64_TSC_RATIO		0xc0000104
#define MSR_AMD64_NB_CFG		0xc001001f
#define MSR_AMD64_PATCH_LOADER		0xc0010020
#define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
#define MSR_AMD64_OSVW_STATUS		0xc0010141
#define MSR_AMD64_DC_CFG		0xc0011022
#define MSR_AMD64_IBSFETCHCTL		0xc0011030
#define MSR_AMD64_IBSFETCHLINAD		0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032
#define MSR_AMD64_IBSFETCH_REG_COUNT	3
#define MSR_AMD64_IBSFETCH_REG_MASK	((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
#define MSR_AMD64_IBSOPCTL		0xc0011033
#define MSR_AMD64_IBSOPRIP		0xc0011034
#define MSR_AMD64_IBSOPDATA		0xc0011035
#define MSR_AMD64_IBSOPDATA2		0xc0011036
#define MSR_AMD64_IBSOPDATA3		0xc0011037
#define MSR_AMD64_IBSDCLINAD		0xc0011038
#define MSR_AMD64_IBSDCPHYSAD		0xc0011039
#define MSR_AMD64_IBSOP_REG_COUNT	7
#define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
#define MSR_AMD64_IBSCTL		0xc001103a
#define MSR_AMD64_IBSBRTARGET		0xc001103b
#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */

/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL		0xc0010200
#define MSR_F15H_PERF_CTR		0xc0010201

/* Fam 10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
#define FAM10H_MMIO_CONF_ENABLE		(1<<0)
#define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf
#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
#define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
#define FAM10H_MMIO_CONF_BASE_SHIFT	20
#define MSR_FAM10H_NODE_ID		0xc001100c

/* K8 MSRs */
#define MSR_K8_TOP_MEM1			0xc001001a
#define MSR_K8_TOP_MEM2			0xc001001d
#define MSR_K8_SYSCFG			0xc0010010
#define MSR_K8_INT_PENDING_MSG		0xc0010055
/* C1E active bits in int pending message */
#define K8_INTP_C1E_ACTIVE_MASK		0x18000000
#define MSR_K8_TSEG_ADDR		0xc0010112
#define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */
#define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */
#define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */

/* K7 MSRs */
#define MSR_K7_EVNTSEL0			0xc0010000
#define MSR_K7_PERFCTR0			0xc0010004
#define MSR_K7_EVNTSEL1			0xc0010001
#define MSR_K7_PERFCTR1			0xc0010005
#define MSR_K7_EVNTSEL2			0xc0010002
#define MSR_K7_PERFCTR2			0xc0010006
#define MSR_K7_EVNTSEL3			0xc0010003
#define MSR_K7_PERFCTR3			0xc0010007
#define MSR_K7_CLK_CTL			0xc001001b
#define MSR_K7_HWCR			0xc0010015
#define MSR_K7_FID_VID_CTL		0xc0010041
#define MSR_K7_FID_VID_STATUS		0xc0010042

/* K6 MSRs */
#define MSR_K6_WHCR			0xc0000082
#define MSR_K6_UWCCR			0xc0000085
#define MSR_K6_EPMR			0xc0000086
#define MSR_K6_PSOR			0xc0000087
#define MSR_K6_PFIR			0xc0000088

/* Centaur-Hauls/IDT defined MSRs. */
#define MSR_IDT_FCR1			0x00000107
#define MSR_IDT_FCR2			0x00000108
#define MSR_IDT_FCR3			0x00000109
#define MSR_IDT_FCR4			0x0000010a

#define MSR_IDT_MCR0			0x00000110
#define MSR_IDT_MCR1			0x00000111
#define MSR_IDT_MCR2			0x00000112
#define MSR_IDT_MCR3			0x00000113
#define MSR_IDT_MCR4			0x00000114
#define MSR_IDT_MCR5			0x00000115
#define MSR_IDT_MCR6			0x00000116
#define MSR_IDT_MCR7			0x00000117
#define MSR_IDT_MCR_CTRL		0x00000120

/* VIA Cyrix defined MSRs*/
#define MSR_VIA_FCR			0x00001107
#define MSR_VIA_LONGHAUL		0x0000110a
#define MSR_VIA_RNG			0x0000110b
#define MSR_VIA_BCR2			0x00001147

/* Transmeta defined MSRs */
#define MSR_TMTA_LONGRUN_CTRL		0x80868010
#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
#define MSR_TMTA_LRTI_READOUT		0x80868018
#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a

/* Intel defined MSRs. */
#define MSR_IA32_P5_MC_ADDR		0x00000000
#define MSR_IA32_P5_MC_TYPE		0x00000001
#define MSR_IA32_TSC			0x00000010
#define MSR_IA32_PLATFORM_ID		0x00000017
#define MSR_IA32_EBL_CR_POWERON		0x0000002a
#define MSR_EBC_FREQUENCY_ID		0x0000002c
#define MSR_IA32_FEATURE_CONTROL        0x0000003a

#define FEATURE_CONTROL_LOCKED				(1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)

#define MSR_IA32_APICBASE		0x0000001b
#define MSR_IA32_APICBASE_BSP		(1<<8)
#define MSR_IA32_APICBASE_ENABLE	(1<<11)
#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)

#define MSR_IA32_TSCDEADLINE		0x000006e0

#define MSR_IA32_UCODE_WRITE		0x00000079
#define MSR_IA32_UCODE_REV		0x0000008b

#define MSR_IA32_PERF_STATUS		0x00000198
#define MSR_IA32_PERF_CTL		0x00000199
#define MSR_AMD_PERF_STATUS		0xc0010063
#define MSR_AMD_PERF_CTL		0xc0010062

#define MSR_IA32_MPERF			0x000000e7
#define MSR_IA32_APERF			0x000000e8

#define MSR_IA32_THERM_CONTROL		0x0000019a
#define MSR_IA32_THERM_INTERRUPT	0x0000019b

#define THERM_INT_HIGH_ENABLE		(1 << 0)
#define THERM_INT_LOW_ENABLE		(1 << 1)
#define THERM_INT_PLN_ENABLE		(1 << 24)

#define MSR_IA32_THERM_STATUS		0x0000019c

#define THERM_STATUS_PROCHOT		(1 << 0)
#define THERM_STATUS_POWER_LIMIT	(1 << 10)

#define MSR_THERM2_CTL			0x0000019d

#define MSR_THERM2_CTL_TM_SELECT	(1ULL << 16)

#define MSR_IA32_MISC_ENABLE		0x000001a0

#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2

#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
#define ENERGY_PERF_BIAS_PERFORMANCE	0
#define ENERGY_PERF_BIAS_NORMAL		6
#define ENERGY_PERF_BIAS_POWERSAVE	15

#define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1

#define PACKAGE_THERM_STATUS_PROCHOT		(1 << 0)
#define PACKAGE_THERM_STATUS_POWER_LIMIT	(1 << 10)

#define MSR_IA32_PACKAGE_THERM_INTERRUPT	0x000001b2

#define PACKAGE_THERM_INT_HIGH_ENABLE		(1 << 0)
#define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)
#define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)

/* Thermal Thresholds Support */
#define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
#define THERM_SHIFT_THRESHOLD0        8
#define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
#define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
#define THERM_SHIFT_THRESHOLD1        16
#define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
#define THERM_STATUS_THRESHOLD0        (1 << 6)
#define THERM_LOG_THRESHOLD0           (1 << 7)
#define THERM_STATUS_THRESHOLD1        (1 << 8)
#define THERM_LOG_THRESHOLD1           (1 << 9)

/* MISC_ENABLE bits: architectural */
#define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
#define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
#define MSR_IA32_MISC_ENABLE_EMON		(1ULL << 7)
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL	(1ULL << 11)
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL	(1ULL << 12)
#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP	(1ULL << 16)
#define MSR_IA32_MISC_ENABLE_MWAIT		(1ULL << 18)
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID	(1ULL << 22)
#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE	(1ULL << 23)
#define MSR_IA32_MISC_ENABLE_XD_DISABLE		(1ULL << 34)

/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
#define MSR_IA32_MISC_ENABLE_X87_COMPAT		(1ULL << 2)
#define MSR_IA32_MISC_ENABLE_TM1		(1ULL << 3)
#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE	(1ULL << 4)
#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE	(1ULL << 6)
#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK	(1ULL << 8)
#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE	(1ULL << 9)
#define MSR_IA32_MISC_ENABLE_FERR		(1ULL << 10)
#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX	(1ULL << 10)
#define MSR_IA32_MISC_ENABLE_TM2		(1ULL << 13)
#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE	(1ULL << 19)
#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK	(1ULL << 20)
#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT	(1ULL << 24)
#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE	(1ULL << 37)
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE	(1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE	(1ULL << 39)

/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX		0x00000180
#define MSR_IA32_MCG_EBX		0x00000181
#define MSR_IA32_MCG_ECX		0x00000182
#define MSR_IA32_MCG_EDX		0x00000183
#define MSR_IA32_MCG_ESI		0x00000184
#define MSR_IA32_MCG_EDI		0x00000185
#define MSR_IA32_MCG_EBP		0x00000186
#define MSR_IA32_MCG_ESP		0x00000187
#define MSR_IA32_MCG_EFLAGS		0x00000188
#define MSR_IA32_MCG_EIP		0x00000189
#define MSR_IA32_MCG_RESERVED		0x0000018a

/* Pentium IV performance counter MSRs */
#define MSR_P4_BPU_PERFCTR0		0x00000300
#define MSR_P4_BPU_PERFCTR1		0x00000301
#define MSR_P4_BPU_PERFCTR2		0x00000302
#define MSR_P4_BPU_PERFCTR3		0x00000303
#define MSR_P4_MS_PERFCTR0		0x00000304
#define MSR_P4_MS_PERFCTR1		0x00000305
#define MSR_P4_MS_PERFCTR2		0x00000306
#define MSR_P4_MS_PERFCTR3		0x00000307
#define MSR_P4_FLAME_PERFCTR0		0x00000308
#define MSR_P4_FLAME_PERFCTR1		0x00000309
#define MSR_P4_FLAME_PERFCTR2		0x0000030a
#define MSR_P4_FLAME_PERFCTR3		0x0000030b
#define MSR_P4_IQ_PERFCTR0		0x0000030c
#define MSR_P4_IQ_PERFCTR1		0x0000030d
#define MSR_P4_IQ_PERFCTR2		0x0000030e
#define MSR_P4_IQ_PERFCTR3		0x0000030f
#define MSR_P4_IQ_PERFCTR4		0x00000310
#define MSR_P4_IQ_PERFCTR5		0x00000311
#define MSR_P4_BPU_CCCR0		0x00000360
#define MSR_P4_BPU_CCCR1		0x00000361
#define MSR_P4_BPU_CCCR2		0x00000362
#define MSR_P4_BPU_CCCR3		0x00000363
#define MSR_P4_MS_CCCR0			0x00000364
#define MSR_P4_MS_CCCR1			0x00000365
#define MSR_P4_MS_CCCR2			0x00000366
#define MSR_P4_MS_CCCR3			0x00000367
#define MSR_P4_FLAME_CCCR0		0x00000368
#define MSR_P4_FLAME_CCCR1		0x00000369
#define MSR_P4_FLAME_CCCR2		0x0000036a
#define MSR_P4_FLAME_CCCR3		0x0000036b
#define MSR_P4_IQ_CCCR0			0x0000036c
#define MSR_P4_IQ_CCCR1			0x0000036d
#define MSR_P4_IQ_CCCR2			0x0000036e
#define MSR_P4_IQ_CCCR3			0x0000036f
#define MSR_P4_IQ_CCCR4			0x00000370
#define MSR_P4_IQ_CCCR5			0x00000371
#define MSR_P4_ALF_ESCR0		0x000003ca
#define MSR_P4_ALF_ESCR1		0x000003cb
#define MSR_P4_BPU_ESCR0		0x000003b2
#define MSR_P4_BPU_ESCR1		0x000003b3
#define MSR_P4_BSU_ESCR0		0x000003a0
#define MSR_P4_BSU_ESCR1		0x000003a1
#define MSR_P4_CRU_ESCR0		0x000003b8
#define MSR_P4_CRU_ESCR1		0x000003b9
#define MSR_P4_CRU_ESCR2		0x000003cc
#define MSR_P4_CRU_ESCR3		0x000003cd
#define MSR_P4_CRU_ESCR4		0x000003e0
#define MSR_P4_CRU_ESCR5		0x000003e1
#define MSR_P4_DAC_ESCR0		0x000003a8
#define MSR_P4_DAC_ESCR1		0x000003a9
#define MSR_P4_FIRM_ESCR0		0x000003a4
#define MSR_P4_FIRM_ESCR1		0x000003a5
#define MSR_P4_FLAME_ESCR0		0x000003a6
#define MSR_P4_FLAME_ESCR1		0x000003a7
#define MSR_P4_FSB_ESCR0		0x000003a2
#define MSR_P4_FSB_ESCR1		0x000003a3
#define MSR_P4_IQ_ESCR0			0x000003ba
#define MSR_P4_IQ_ESCR1			0x000003bb
#define MSR_P4_IS_ESCR0			0x000003b4
#define MSR_P4_IS_ESCR1			0x000003b5
#define MSR_P4_ITLB_ESCR0		0x000003b6
#define MSR_P4_ITLB_ESCR1		0x000003b7
#define MSR_P4_IX_ESCR0			0x000003c8
#define MSR_P4_IX_ESCR1			0x000003c9
#define MSR_P4_MOB_ESCR0		0x000003aa
#define MSR_P4_MOB_ESCR1		0x000003ab
#define MSR_P4_MS_ESCR0			0x000003c0
#define MSR_P4_MS_ESCR1			0x000003c1
#define MSR_P4_PMH_ESCR0		0x000003ac
#define MSR_P4_PMH_ESCR1		0x000003ad
#define MSR_P4_RAT_ESCR0		0x000003bc
#define MSR_P4_RAT_ESCR1		0x000003bd
#define MSR_P4_SAAT_ESCR0		0x000003ae
#define MSR_P4_SAAT_ESCR1		0x000003af
#define MSR_P4_SSU_ESCR0		0x000003be
#define MSR_P4_SSU_ESCR1		0x000003bf /* guess: not in manual */

#define MSR_P4_TBPU_ESCR0		0x000003c2
#define MSR_P4_TBPU_ESCR1		0x000003c3
#define MSR_P4_TC_ESCR0			0x000003c4
#define MSR_P4_TC_ESCR1			0x000003c5
#define MSR_P4_U2L_ESCR0		0x000003b0
#define MSR_P4_U2L_ESCR1		0x000003b1

#define MSR_P4_PEBS_MATRIX_VERT		0x000003f2

/* Intel Core-based CPU performance counters */
#define MSR_CORE_PERF_FIXED_CTR0	0x00000309
#define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
#define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
#define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
#define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390

/* Geode defined MSRs */
#define MSR_GEODE_BUSCONT_CONF0		0x00001900

/* Intel VT MSRs */
#define MSR_IA32_VMX_BASIC              0x00000480
#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
#define MSR_IA32_VMX_MISC               0x00000485
#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
#define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490

/* VMX_BASIC bits and bitmasks */
#define VMX_BASIC_VMCS_SIZE_SHIFT	32
#define VMX_BASIC_64		0x0001000000000000LLU
#define VMX_BASIC_MEM_TYPE_SHIFT	50
#define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU
#define VMX_BASIC_MEM_TYPE_WB	6LLU
#define VMX_BASIC_INOUT		0x0040000000000000LLU

/* AMD-V MSRs */

#define MSR_VM_CR                       0xc0010114
#define MSR_VM_IGNNE                    0xc0010115
#define MSR_VM_HSAVE_PA                 0xc0010117

#endif /* _ASM_X86_MSR_INDEX_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MSR_INDEX_H
1965aae3 PA	2	#define _ASM_X86_MSR_INDEX_H
4bc5aa91 PA	3
	4	/* CPU model specific register (MSR) numbers */
	5
	6	/* x86-64 specific MSRs */
	7	#define MSR_EFER 0xc0000080 /* extended feature register */
	8	#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
	9	#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
	10	#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
	11	#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
	12	#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
	13	#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
	14	#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
5df97400	15	#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
4bc5aa91 PA	16
	17	/* EFER bits: */
	18	#define _EFER_SCE 0 /* SYSCALL/SYSRET */
	19	#define _EFER_LME 8 /* Long mode enable */
	20	#define _EFER_LMA 10 /* Long mode active (read-only) */
	21	#define _EFER_NX 11 /* No execute enable */
9962d032	22	#define _EFER_SVME 12 /* Enable virtualization */
eec4b140	23	#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
d2062693	24	#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
4bc5aa91 PA	25
	26	#define EFER_SCE (1<<_EFER_SCE)
	27	#define EFER_LME (1<<_EFER_LME)
	28	#define EFER_LMA (1<<_EFER_LMA)
	29	#define EFER_NX (1<<_EFER_NX)
9962d032	30	#define EFER_SVME (1<<_EFER_SVME)
eec4b140	31	#define EFER_LMSLE (1<<_EFER_LMSLE)
d2062693	32	#define EFER_FFXSR (1<<_EFER_FFXSR)
4bc5aa91 PA	33
	34	/* Intel MSRs. Some also available on other CPUs */
	35	#define MSR_IA32_PERFCTR0 0x000000c1
	36	#define MSR_IA32_PERFCTR1 0x000000c2
	37	#define MSR_FSB_FREQ 0x000000cd
	38
14796fca LB	39	#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
	40	#define NHM_C3_AUTO_DEMOTE (1UL << 25)
	41	#define NHM_C1_AUTO_DEMOTE (1UL << 26)
bfb53ccf	42	#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
14796fca	43
4bc5aa91 PA	44	#define MSR_MTRRcap 0x000000fe
4bc5aa91 PA	45	#define MSR_IA32_BBL_CR_CTL 0x00000119
91c9c3ed	46	#define MSR_IA32_BBL_CR_CTL3 0x0000011e
4bc5aa91 PA	47
	48	#define MSR_IA32_SYSENTER_CS 0x00000174
	49	#define MSR_IA32_SYSENTER_ESP 0x00000175
	50	#define MSR_IA32_SYSENTER_EIP 0x00000176
	51
	52	#define MSR_IA32_MCG_CAP 0x00000179
	53	#define MSR_IA32_MCG_STATUS 0x0000017a
	54	#define MSR_IA32_MCG_CTL 0x0000017b
	55
a7e3ed1e AK	56	#define MSR_OFFCORE_RSP_0 0x000001a6
	57	#define MSR_OFFCORE_RSP_1 0x000001a7
	58
225ce539 SE	59	#define MSR_LBR_SELECT 0x000001c8
	60	#define MSR_LBR_TOS 0x000001c9
	61	#define MSR_LBR_NHM_FROM 0x00000680
	62	#define MSR_LBR_NHM_TO 0x000006c0
	63	#define MSR_LBR_CORE_FROM 0x00000040
	64	#define MSR_LBR_CORE_TO 0x00000060
	65
4bc5aa91 PA	66	#define MSR_IA32_PEBS_ENABLE 0x000003f1
	67	#define MSR_IA32_DS_AREA 0x00000600
	68	#define MSR_IA32_PERF_CAPABILITIES 0x00000345
	69
	70	#define MSR_MTRRfix64K_00000 0x00000250
	71	#define MSR_MTRRfix16K_80000 0x00000258
	72	#define MSR_MTRRfix16K_A0000 0x00000259
	73	#define MSR_MTRRfix4K_C0000 0x00000268
	74	#define MSR_MTRRfix4K_C8000 0x00000269
	75	#define MSR_MTRRfix4K_D0000 0x0000026a
	76	#define MSR_MTRRfix4K_D8000 0x0000026b
	77	#define MSR_MTRRfix4K_E0000 0x0000026c
	78	#define MSR_MTRRfix4K_E8000 0x0000026d
	79	#define MSR_MTRRfix4K_F0000 0x0000026e
	80	#define MSR_MTRRfix4K_F8000 0x0000026f
	81	#define MSR_MTRRdefType 0x000002ff
	82
2e5d9c85	83	#define MSR_IA32_CR_PAT 0x00000277
2e5d9c85	84
4bc5aa91 PA	85	#define MSR_IA32_DEBUGCTLMSR 0x000001d9
	86	#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
	87	#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
	88	#define MSR_IA32_LASTINTFROMIP 0x000001dd
	89	#define MSR_IA32_LASTINTTOIP 0x000001de
	90
d2499d8b	91	/* DEBUGCTLMSR bits (others vary by model): */
7c5ecaf7 PZ	92	#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
	93	#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
	94	#define DEBUGCTLMSR_TR (1UL << 6)
	95	#define DEBUGCTLMSR_BTS (1UL << 7)
	96	#define DEBUGCTLMSR_BTINT (1UL << 8)
	97	#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
	98	#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
	99	#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
d2499d8b	100
4bc5aa91 PA	101	#define MSR_IA32_MC0_CTL 0x00000400
	102	#define MSR_IA32_MC0_STATUS 0x00000401
	103	#define MSR_IA32_MC0_ADDR 0x00000402
	104	#define MSR_IA32_MC0_MISC 0x00000403
	105
5bbc097d JR	106	#define MSR_AMD64_MC0_MASK 0xc0010044
5bbc097d JR	107
a2d32bcb AK	108	#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
	109	#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
	110	#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
	111	#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
	112
5bbc097d JR	113	#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
5bbc097d JR	114
03195c6b AK	115	/* These are consecutive and not in the normal 4er MCE bank block */
03195c6b AK	116	#define MSR_IA32_MC0_CTL2 0x00000280
a2d32bcb AK	117	#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
a2d32bcb AK	118
4bc5aa91 PA	119	#define MSR_P6_PERFCTR0 0x000000c1
	120	#define MSR_P6_PERFCTR1 0x000000c2
	121	#define MSR_P6_EVNTSEL0 0x00000186
	122	#define MSR_P6_EVNTSEL1 0x00000187
	123
4f8a6b1a	124	/* AMD64 MSRs. Not complete. See the architecture manual for a more
4bc5aa91	125	complete list. */
4f8a6b1a	126
29d0887f	127	#define MSR_AMD64_PATCH_LEVEL 0x0000008b
fbc0db76	128	#define MSR_AMD64_TSC_RATIO 0xc0000104
12db648c	129	#define MSR_AMD64_NB_CFG 0xc001001f
29d0887f	130	#define MSR_AMD64_PATCH_LOADER 0xc0010020
035a02c1 AH	131	#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
035a02c1 AH	132	#define MSR_AMD64_OSVW_STATUS 0xc0010141
67ec6607	133	#define MSR_AMD64_DC_CFG 0xc0011022
4f8a6b1a SE	134	#define MSR_AMD64_IBSFETCHCTL 0xc0011030
	135	#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
	136	#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
b7074f1f RR	137	#define MSR_AMD64_IBSFETCH_REG_COUNT 3
b7074f1f RR	138	#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
4f8a6b1a SE	139	#define MSR_AMD64_IBSOPCTL 0xc0011033
	140	#define MSR_AMD64_IBSOPRIP 0xc0011034
	141	#define MSR_AMD64_IBSOPDATA 0xc0011035
	142	#define MSR_AMD64_IBSOPDATA2 0xc0011036
	143	#define MSR_AMD64_IBSOPDATA3 0xc0011037
	144	#define MSR_AMD64_IBSDCLINAD 0xc0011038
	145	#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
b7074f1f RR	146	#define MSR_AMD64_IBSOP_REG_COUNT 7
b7074f1f RR	147	#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
4f8a6b1a	148	#define MSR_AMD64_IBSCTL 0xc001103a
25da6950	149	#define MSR_AMD64_IBSBRTARGET 0xc001103b
b7074f1f	150	#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
4f8a6b1a	151
da169f5d RR	152	/* Fam 15h MSRs */
	153	#define MSR_F15H_PERF_CTL 0xc0010200
	154	#define MSR_F15H_PERF_CTR 0xc0010201
	155
2274c33e YL	156	/* Fam 10h MSRs */
	157	#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
	158	#define FAM10H_MMIO_CONF_ENABLE (1<<0)
	159	#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
	160	#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
37db6c8f	161	#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
2274c33e	162	#define FAM10H_MMIO_CONF_BASE_SHIFT 20
9d260ebc	163	#define MSR_FAM10H_NODE_ID 0xc001100c
2274c33e	164
4f8a6b1a SE	165	/* K8 MSRs */
	166	#define MSR_K8_TOP_MEM1 0xc001001a
	167	#define MSR_K8_TOP_MEM2 0xc001001d
	168	#define MSR_K8_SYSCFG 0xc0010010
aa83f3f2 TG	169	#define MSR_K8_INT_PENDING_MSG 0xc0010055
	170	/* C1E active bits in int pending message */
	171	#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
8346ea17	172	#define MSR_K8_TSEG_ADDR 0xc0010112
4f8a6b1a SE	173	#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
	174	#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
	175	#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem\|WrMem */
	176
	177	/* K7 MSRs */
4bc5aa91 PA	178	#define MSR_K7_EVNTSEL0 0xc0010000
	179	#define MSR_K7_PERFCTR0 0xc0010004
	180	#define MSR_K7_EVNTSEL1 0xc0010001
	181	#define MSR_K7_PERFCTR1 0xc0010005
	182	#define MSR_K7_EVNTSEL2 0xc0010002
	183	#define MSR_K7_PERFCTR2 0xc0010006
	184	#define MSR_K7_EVNTSEL3 0xc0010003
	185	#define MSR_K7_PERFCTR3 0xc0010007
4bc5aa91	186	#define MSR_K7_CLK_CTL 0xc001001b
4bc5aa91	187	#define MSR_K7_HWCR 0xc0010015
4bc5aa91 PA	188	#define MSR_K7_FID_VID_CTL 0xc0010041
4bc5aa91 PA	189	#define MSR_K7_FID_VID_STATUS 0xc0010042
4bc5aa91 PA	190
4bc5aa91 PA	191	/* K6 MSRs */
4bc5aa91 PA	192	#define MSR_K6_WHCR 0xc0000082
	193	#define MSR_K6_UWCCR 0xc0000085
	194	#define MSR_K6_EPMR 0xc0000086
	195	#define MSR_K6_PSOR 0xc0000087
	196	#define MSR_K6_PFIR 0xc0000088
	197
	198	/* Centaur-Hauls/IDT defined MSRs. */
	199	#define MSR_IDT_FCR1 0x00000107
	200	#define MSR_IDT_FCR2 0x00000108
	201	#define MSR_IDT_FCR3 0x00000109
	202	#define MSR_IDT_FCR4 0x0000010a
	203
	204	#define MSR_IDT_MCR0 0x00000110
	205	#define MSR_IDT_MCR1 0x00000111
	206	#define MSR_IDT_MCR2 0x00000112
	207	#define MSR_IDT_MCR3 0x00000113
	208	#define MSR_IDT_MCR4 0x00000114
	209	#define MSR_IDT_MCR5 0x00000115
	210	#define MSR_IDT_MCR6 0x00000116
	211	#define MSR_IDT_MCR7 0x00000117
	212	#define MSR_IDT_MCR_CTRL 0x00000120
	213
	214	/* VIA Cyrix defined MSRs*/
	215	#define MSR_VIA_FCR 0x00001107
	216	#define MSR_VIA_LONGHAUL 0x0000110a
	217	#define MSR_VIA_RNG 0x0000110b
	218	#define MSR_VIA_BCR2 0x00001147
	219
	220	/* Transmeta defined MSRs */
	221	#define MSR_TMTA_LONGRUN_CTRL 0x80868010
	222	#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
	223	#define MSR_TMTA_LRTI_READOUT 0x80868018
	224	#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
	225
	226	/* Intel defined MSRs. */
	227	#define MSR_IA32_P5_MC_ADDR 0x00000000
	228	#define MSR_IA32_P5_MC_TYPE 0x00000001
	229	#define MSR_IA32_TSC 0x00000010
	230	#define MSR_IA32_PLATFORM_ID 0x00000017
	231	#define MSR_IA32_EBL_CR_POWERON 0x0000002a
b9a52c4b	232	#define MSR_EBC_FREQUENCY_ID 0x0000002c
315a6558	233	#define MSR_IA32_FEATURE_CONTROL 0x0000003a
4bc5aa91	234
cafd6659 SW	235	#define FEATURE_CONTROL_LOCKED (1<<0)
	236	#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
	237	#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
defed7ed	238
4bc5aa91 PA	239	#define MSR_IA32_APICBASE 0x0000001b
	240	#define MSR_IA32_APICBASE_BSP (1<<8)
	241	#define MSR_IA32_APICBASE_ENABLE (1<<11)
	242	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
	243
b90dfb04 LJ	244	#define MSR_IA32_TSCDEADLINE 0x000006e0
b90dfb04 LJ	245
4bc5aa91 PA	246	#define MSR_IA32_UCODE_WRITE 0x00000079
	247	#define MSR_IA32_UCODE_REV 0x0000008b
	248
	249	#define MSR_IA32_PERF_STATUS 0x00000198
	250	#define MSR_IA32_PERF_CTL 0x00000199
3dc9a633 MG	251	#define MSR_AMD_PERF_STATUS 0xc0010063
3dc9a633 MG	252	#define MSR_AMD_PERF_CTL 0xc0010062
4bc5aa91 PA	253
	254	#define MSR_IA32_MPERF 0x000000e7
	255	#define MSR_IA32_APERF 0x000000e8
	256
	257	#define MSR_IA32_THERM_CONTROL 0x0000019a
	258	#define MSR_IA32_THERM_INTERRUPT 0x0000019b
ba2d0f2b	259
9792db61 FY	260	#define THERM_INT_HIGH_ENABLE (1 << 0)
	261	#define THERM_INT_LOW_ENABLE (1 << 1)
	262	#define THERM_INT_PLN_ENABLE (1 << 24)
ba2d0f2b	263
4bc5aa91	264	#define MSR_IA32_THERM_STATUS 0x0000019c
ba2d0f2b TG	265
ba2d0f2b TG	266	#define THERM_STATUS_PROCHOT (1 << 0)
9792db61	267	#define THERM_STATUS_POWER_LIMIT (1 << 10)
ba2d0f2b	268
f3a0867b BZ	269	#define MSR_THERM2_CTL 0x0000019d
	270
	271	#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
	272
4bc5aa91 PA	273	#define MSR_IA32_MISC_ENABLE 0x000001a0
4bc5aa91 PA	274
a321cedb CE	275	#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
a321cedb CE	276
23016bf0	277	#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
abe48b10 LB	278	#define ENERGY_PERF_BIAS_PERFORMANCE 0
abe48b10 LB	279	#define ENERGY_PERF_BIAS_NORMAL 6
4bb82178	280	#define ENERGY_PERF_BIAS_POWERSAVE 15
23016bf0	281
9792db61 FY	282	#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
	283
	284	#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
	285	#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
	286
	287	#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
	288
	289	#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
	290	#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
	291	#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
	292
9e76a97e D	293	/* Thermal Thresholds Support */
	294	#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
	295	#define THERM_SHIFT_THRESHOLD0 8
	296	#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
	297	#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
	298	#define THERM_SHIFT_THRESHOLD1 16
	299	#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
	300	#define THERM_STATUS_THRESHOLD0 (1 << 6)
	301	#define THERM_LOG_THRESHOLD0 (1 << 7)
	302	#define THERM_STATUS_THRESHOLD1 (1 << 8)
	303	#define THERM_LOG_THRESHOLD1 (1 << 9)
	304
bdf21a49 PA	305	/* MISC_ENABLE bits: architectural */
	306	#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
	307	#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
	308	#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
	309	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
	310	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
	311	#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
	312	#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
	313	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
	314	#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
	315	#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
	316
	317	/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
	318	#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
	319	#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
	320	#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
	321	#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
	322	#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
	323	#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
	324	#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
	325	#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
	326	#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
	327	#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
	328	#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
	329	#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
	330	#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
	331	#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
	332	#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
	333
4bc5aa91 PA	334	/* P4/Xeon+ specific */
	335	#define MSR_IA32_MCG_EAX 0x00000180
	336	#define MSR_IA32_MCG_EBX 0x00000181
	337	#define MSR_IA32_MCG_ECX 0x00000182
	338	#define MSR_IA32_MCG_EDX 0x00000183
	339	#define MSR_IA32_MCG_ESI 0x00000184
	340	#define MSR_IA32_MCG_EDI 0x00000185
	341	#define MSR_IA32_MCG_EBP 0x00000186
	342	#define MSR_IA32_MCG_ESP 0x00000187
	343	#define MSR_IA32_MCG_EFLAGS 0x00000188
	344	#define MSR_IA32_MCG_EIP 0x00000189
	345	#define MSR_IA32_MCG_RESERVED 0x0000018a
	346
	347	/* Pentium IV performance counter MSRs */
	348	#define MSR_P4_BPU_PERFCTR0 0x00000300
	349	#define MSR_P4_BPU_PERFCTR1 0x00000301
	350	#define MSR_P4_BPU_PERFCTR2 0x00000302
	351	#define MSR_P4_BPU_PERFCTR3 0x00000303
	352	#define MSR_P4_MS_PERFCTR0 0x00000304
	353	#define MSR_P4_MS_PERFCTR1 0x00000305
	354	#define MSR_P4_MS_PERFCTR2 0x00000306
	355	#define MSR_P4_MS_PERFCTR3 0x00000307
	356	#define MSR_P4_FLAME_PERFCTR0 0x00000308
	357	#define MSR_P4_FLAME_PERFCTR1 0x00000309
	358	#define MSR_P4_FLAME_PERFCTR2 0x0000030a
	359	#define MSR_P4_FLAME_PERFCTR3 0x0000030b
	360	#define MSR_P4_IQ_PERFCTR0 0x0000030c
	361	#define MSR_P4_IQ_PERFCTR1 0x0000030d
	362	#define MSR_P4_IQ_PERFCTR2 0x0000030e
	363	#define MSR_P4_IQ_PERFCTR3 0x0000030f
	364	#define MSR_P4_IQ_PERFCTR4 0x00000310
	365	#define MSR_P4_IQ_PERFCTR5 0x00000311
	366	#define MSR_P4_BPU_CCCR0 0x00000360
	367	#define MSR_P4_BPU_CCCR1 0x00000361
	368	#define MSR_P4_BPU_CCCR2 0x00000362
	369	#define MSR_P4_BPU_CCCR3 0x00000363
	370	#define MSR_P4_MS_CCCR0 0x00000364
	371	#define MSR_P4_MS_CCCR1 0x00000365
	372	#define MSR_P4_MS_CCCR2 0x00000366
	373	#define MSR_P4_MS_CCCR3 0x00000367
	374	#define MSR_P4_FLAME_CCCR0 0x00000368
	375	#define MSR_P4_FLAME_CCCR1 0x00000369
	376	#define MSR_P4_FLAME_CCCR2 0x0000036a
	377	#define MSR_P4_FLAME_CCCR3 0x0000036b
	378	#define MSR_P4_IQ_CCCR0 0x0000036c
	379	#define MSR_P4_IQ_CCCR1 0x0000036d
	380	#define MSR_P4_IQ_CCCR2 0x0000036e
	381	#define MSR_P4_IQ_CCCR3 0x0000036f
	382	#define MSR_P4_IQ_CCCR4 0x00000370
	383	#define MSR_P4_IQ_CCCR5 0x00000371
	384	#define MSR_P4_ALF_ESCR0 0x000003ca
	385	#define MSR_P4_ALF_ESCR1 0x000003cb
	386	#define MSR_P4_BPU_ESCR0 0x000003b2
	387	#define MSR_P4_BPU_ESCR1 0x000003b3
	388	#define MSR_P4_BSU_ESCR0 0x000003a0
	389	#define MSR_P4_BSU_ESCR1 0x000003a1
	390	#define MSR_P4_CRU_ESCR0 0x000003b8
	391	#define MSR_P4_CRU_ESCR1 0x000003b9
	392	#define MSR_P4_CRU_ESCR2 0x000003cc
	393	#define MSR_P4_CRU_ESCR3 0x000003cd
	394	#define MSR_P4_CRU_ESCR4 0x000003e0
	395	#define MSR_P4_CRU_ESCR5 0x000003e1
	396	#define MSR_P4_DAC_ESCR0 0x000003a8
	397	#define MSR_P4_DAC_ESCR1 0x000003a9
398	#define MSR_P4_FIRM_ESCR0 0x000003a4
399	#define MSR_P4_FIRM_ESCR1 0x000003a5
400	#define MSR_P4_FLAME_ESCR0 0x000003a6
401	#define MSR_P4_FLAME_ESCR1 0x000003a7
402	#define MSR_P4_FSB_ESCR0 0x000003a2
403	#define MSR_P4_FSB_ESCR1 0x000003a3
404	#define MSR_P4_IQ_ESCR0 0x000003ba
405	#define MSR_P4_IQ_ESCR1 0x000003bb
406	#define MSR_P4_IS_ESCR0 0x000003b4
407	#define MSR_P4_IS_ESCR1 0x000003b5
408	#define MSR_P4_ITLB_ESCR0 0x000003b6
409	#define MSR_P4_ITLB_ESCR1 0x000003b7
410	#define MSR_P4_IX_ESCR0 0x000003c8
411	#define MSR_P4_IX_ESCR1 0x000003c9
412	#define MSR_P4_MOB_ESCR0 0x000003aa
413	#define MSR_P4_MOB_ESCR1 0x000003ab
414	#define MSR_P4_MS_ESCR0 0x000003c0
415	#define MSR_P4_MS_ESCR1 0x000003c1
416	#define MSR_P4_PMH_ESCR0 0x000003ac
417	#define MSR_P4_PMH_ESCR1 0x000003ad
418	#define MSR_P4_RAT_ESCR0 0x000003bc
419	#define MSR_P4_RAT_ESCR1 0x000003bd
420	#define MSR_P4_SAAT_ESCR0 0x000003ae
421	#define MSR_P4_SAAT_ESCR1 0x000003af
422	#define MSR_P4_SSU_ESCR0 0x000003be
423	#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
424
425	#define MSR_P4_TBPU_ESCR0 0x000003c2
426	#define MSR_P4_TBPU_ESCR1 0x000003c3
427	#define MSR_P4_TC_ESCR0 0x000003c4
428	#define MSR_P4_TC_ESCR1 0x000003c5
429	#define MSR_P4_U2L_ESCR0 0x000003b0
430	#define MSR_P4_U2L_ESCR1 0x000003b1
431
cb7d6b50 LM	432	#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
cb7d6b50 LM	433
4bc5aa91 PA	434	/* Intel Core-based CPU performance counters */
	435	#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
	436	#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
	437	#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
	438	#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
	439	#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
	440	#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
	441	#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
	442
	443	/* Geode defined MSRs */
	444	#define MSR_GEODE_BUSCONT_CONF0 0x00001900
	445
315a6558 SY	446	/* Intel VT MSRs */
	447	#define MSR_IA32_VMX_BASIC 0x00000480
	448	#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
	449	#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
	450	#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
	451	#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
	452	#define MSR_IA32_VMX_MISC 0x00000485
	453	#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
	454	#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
	455	#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
	456	#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
	457	#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
	458	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
	459	#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
b87a51ae NHE	460	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
	461	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
	462	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
	463	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
	464
	465	/* VMX_BASIC bits and bitmasks */
	466	#define VMX_BASIC_VMCS_SIZE_SHIFT 32
	467	#define VMX_BASIC_64 0x0001000000000000LLU
	468	#define VMX_BASIC_MEM_TYPE_SHIFT 50
	469	#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
	470	#define VMX_BASIC_MEM_TYPE_WB 6LLU
	471	#define VMX_BASIC_INOUT 0x0040000000000000LLU
315a6558	472
9962d032 AG	473	/* AMD-V MSRs */
	474
	475	#define MSR_VM_CR 0xc0010114
0367b433	476	#define MSR_VM_IGNNE 0xc0010115
9962d032 AG	477	#define MSR_VM_HSAVE_PA 0xc0010117
9962d032 AG	478
1965aae3	479	#endif /* _ASM_X86_MSR_INDEX_H */