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bc83cccc PA |
1 | #ifndef _ASM_X86_MWAIT_H |
2 | #define _ASM_X86_MWAIT_H | |
3 | ||
16824255 | 4 | #include <linux/sched.h> |
4c822698 | 5 | #include <linux/sched/idle.h> |
16824255 | 6 | |
cd4d09ec | 7 | #include <asm/cpufeature.h> |
9aff3d50 TC |
8 | #include <asm/spec_ctrl.h> |
9 | #include <asm/microcode.h> | |
cd4d09ec | 10 | |
bc83cccc PA |
11 | #define MWAIT_SUBSTATE_MASK 0xf |
12 | #define MWAIT_CSTATE_MASK 0xf | |
13 | #define MWAIT_SUBSTATE_SIZE 4 | |
e022e7eb LB |
14 | #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) |
15 | #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) | |
bc83cccc PA |
16 | |
17 | #define CPUID_MWAIT_LEAF 5 | |
18 | #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 | |
19 | #define CPUID5_ECX_INTERRUPT_BREAK 0x2 | |
20 | ||
21 | #define MWAIT_ECX_INTERRUPT_BREAK 0x1 | |
f9675674 HR |
22 | #define MWAITX_ECX_TIMER_ENABLE BIT(1) |
23 | #define MWAITX_MAX_LOOPS ((u32)-1) | |
24 | #define MWAITX_DISABLE_CSTATES 0xf | |
bc83cccc | 25 | |
16824255 PZ |
26 | static inline void __monitor(const void *eax, unsigned long ecx, |
27 | unsigned long edx) | |
28 | { | |
29 | /* "monitor %eax, %ecx, %edx;" */ | |
30 | asm volatile(".byte 0x0f, 0x01, 0xc8;" | |
31 | :: "a" (eax), "c" (ecx), "d"(edx)); | |
32 | } | |
33 | ||
f9675674 HR |
34 | static inline void __monitorx(const void *eax, unsigned long ecx, |
35 | unsigned long edx) | |
36 | { | |
37 | /* "monitorx %eax, %ecx, %edx;" */ | |
38 | asm volatile(".byte 0x0f, 0x01, 0xfa;" | |
39 | :: "a" (eax), "c" (ecx), "d"(edx)); | |
40 | } | |
41 | ||
16824255 PZ |
42 | static inline void __mwait(unsigned long eax, unsigned long ecx) |
43 | { | |
44 | /* "mwait %eax, %ecx;" */ | |
45 | asm volatile(".byte 0x0f, 0x01, 0xc9;" | |
46 | :: "a" (eax), "c" (ecx)); | |
47 | } | |
48 | ||
f9675674 HR |
49 | /* |
50 | * MWAITX allows for a timer expiration to get the core out a wait state in | |
51 | * addition to the default MWAIT exit condition of a store appearing at a | |
52 | * monitored virtual address. | |
53 | * | |
54 | * Registers: | |
55 | * | |
56 | * MWAITX ECX[1]: enable timer if set | |
57 | * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 | |
58 | * frequency is the same as the TSC frequency. | |
59 | * | |
60 | * Below is a comparison between MWAIT and MWAITX on AMD processors: | |
61 | * | |
62 | * MWAIT MWAITX | |
63 | * opcode 0f 01 c9 | 0f 01 fb | |
64 | * ECX[0] value of RFLAGS.IF seen by instruction | |
65 | * ECX[1] unused/#GP if set | enable timer if set | |
66 | * ECX[31:2] unused/#GP if set | |
67 | * EAX unused (reserve for hint) | |
68 | * EBX[31:0] unused | max wait time (P0 clocks) | |
69 | * | |
70 | * MONITOR MONITORX | |
71 | * opcode 0f 01 c8 | 0f 01 fa | |
72 | * EAX (logical) address to monitor | |
73 | * ECX #GP if not zero | |
74 | */ | |
75 | static inline void __mwaitx(unsigned long eax, unsigned long ebx, | |
76 | unsigned long ecx) | |
77 | { | |
78 | /* "mwaitx %eax, %ebx, %ecx;" */ | |
79 | asm volatile(".byte 0x0f, 0x01, 0xfb;" | |
80 | :: "a" (eax), "b" (ebx), "c" (ecx)); | |
81 | } | |
82 | ||
b253149b LB |
83 | static inline void __sti_mwait(unsigned long eax, unsigned long ecx) |
84 | { | |
85 | trace_hardirqs_on(); | |
86 | /* "mwait %eax, %ecx;" */ | |
87 | asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" | |
88 | :: "a" (eax), "c" (ecx)); | |
89 | } | |
90 | ||
16824255 PZ |
91 | /* |
92 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
93 | * which can obviate IPI to trigger checking of need_resched. | |
94 | * We execute MONITOR against need_resched and enter optimized wait state | |
95 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
96 | * up from MWAIT (without an IPI). | |
97 | * | |
98 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
99 | * capability. | |
100 | */ | |
101 | static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) | |
102 | { | |
08e237fa | 103 | if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) { |
9b13a93d | 104 | if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { |
7e98b719 | 105 | mb(); |
16824255 | 106 | clflush((void *)¤t_thread_info()->flags); |
7e98b719 PA |
107 | mb(); |
108 | } | |
16824255 | 109 | |
357b57d7 | 110 | if (ibrs_inuse) |
9aff3d50 TC |
111 | native_wrmsrl(MSR_IA32_SPEC_CTRL, 0); |
112 | ||
16824255 PZ |
113 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
114 | if (!need_resched()) | |
115 | __mwait(eax, ecx); | |
9aff3d50 | 116 | |
357b57d7 | 117 | if (ibrs_inuse) |
9aff3d50 | 118 | native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS); |
16824255 | 119 | } |
8cb75e0c | 120 | current_clr_polling(); |
16824255 PZ |
121 | } |
122 | ||
bc83cccc | 123 | #endif /* _ASM_X86_MWAIT_H */ |