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Commit | Line | Data |
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1965aae3 PA |
1 | #ifndef _ASM_X86_PARAVIRT_H |
2 | #define _ASM_X86_PARAVIRT_H | |
d3561b7f RR |
3 | /* Various instructions on x86 need to be replaced for |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
54321d94 | 7 | #include <asm/pgtable_types.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
ac5672f8 | 10 | #include <asm/paravirt_types.h> |
ecb93d1c | 11 | |
d3561b7f | 12 | #ifndef __ASSEMBLY__ |
187f1882 | 13 | #include <linux/bug.h> |
3dc494e8 | 14 | #include <linux/types.h> |
d4c10477 | 15 | #include <linux/cpumask.h> |
1a45b7aa | 16 | |
f8822f42 JF |
17 | static inline int paravirt_enabled(void) |
18 | { | |
93b1eab3 | 19 | return pv_info.paravirt_enabled; |
f8822f42 | 20 | } |
d3561b7f | 21 | |
faca6227 | 22 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
23 | struct thread_struct *thread) |
24 | { | |
faca6227 | 25 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
26 | } |
27 | ||
d3561b7f RR |
28 | /* The paravirtualized CPUID instruction. */ |
29 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
30 | unsigned int *ecx, unsigned int *edx) | |
31 | { | |
93b1eab3 | 32 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
33 | } |
34 | ||
35 | /* | |
36 | * These special macros can be used to get or set a debugging register | |
37 | */ | |
f8822f42 JF |
38 | static inline unsigned long paravirt_get_debugreg(int reg) |
39 | { | |
93b1eab3 | 40 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
41 | } |
42 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
43 | static inline void set_debugreg(unsigned long val, int reg) | |
44 | { | |
93b1eab3 | 45 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 46 | } |
d3561b7f | 47 | |
f8822f42 JF |
48 | static inline void clts(void) |
49 | { | |
93b1eab3 | 50 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 51 | } |
d3561b7f | 52 | |
f8822f42 JF |
53 | static inline unsigned long read_cr0(void) |
54 | { | |
93b1eab3 | 55 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 56 | } |
d3561b7f | 57 | |
f8822f42 JF |
58 | static inline void write_cr0(unsigned long x) |
59 | { | |
93b1eab3 | 60 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
61 | } |
62 | ||
63 | static inline unsigned long read_cr2(void) | |
64 | { | |
93b1eab3 | 65 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
66 | } |
67 | ||
68 | static inline void write_cr2(unsigned long x) | |
69 | { | |
93b1eab3 | 70 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
71 | } |
72 | ||
73 | static inline unsigned long read_cr3(void) | |
74 | { | |
93b1eab3 | 75 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 76 | } |
d3561b7f | 77 | |
f8822f42 JF |
78 | static inline void write_cr3(unsigned long x) |
79 | { | |
93b1eab3 | 80 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 81 | } |
d3561b7f | 82 | |
f8822f42 JF |
83 | static inline unsigned long read_cr4(void) |
84 | { | |
93b1eab3 | 85 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 JF |
86 | } |
87 | static inline unsigned long read_cr4_safe(void) | |
88 | { | |
93b1eab3 | 89 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 90 | } |
d3561b7f | 91 | |
f8822f42 JF |
92 | static inline void write_cr4(unsigned long x) |
93 | { | |
93b1eab3 | 94 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 95 | } |
3dc494e8 | 96 | |
94ea03cd | 97 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
98 | static inline unsigned long read_cr8(void) |
99 | { | |
100 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
101 | } | |
102 | ||
103 | static inline void write_cr8(unsigned long x) | |
104 | { | |
105 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
106 | } | |
94ea03cd | 107 | #endif |
4c9890c2 | 108 | |
df9ee292 | 109 | static inline void arch_safe_halt(void) |
d3561b7f | 110 | { |
93b1eab3 | 111 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
112 | } |
113 | ||
114 | static inline void halt(void) | |
115 | { | |
c8217b83 | 116 | PVOP_VCALL0(pv_irq_ops.halt); |
f8822f42 JF |
117 | } |
118 | ||
119 | static inline void wbinvd(void) | |
120 | { | |
93b1eab3 | 121 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 122 | } |
d3561b7f | 123 | |
93b1eab3 | 124 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 125 | |
f8822f42 JF |
126 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
127 | { | |
93b1eab3 | 128 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 | 129 | } |
132ec92f | 130 | |
f8822f42 JF |
131 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) |
132 | { | |
93b1eab3 | 133 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
134 | } |
135 | ||
90a0a06a | 136 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
49cd740b JP |
137 | #define rdmsr(msr, val1, val2) \ |
138 | do { \ | |
f8822f42 JF |
139 | int _err; \ |
140 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
141 | val1 = (u32)_l; \ | |
142 | val2 = _l >> 32; \ | |
49cd740b | 143 | } while (0) |
d3561b7f | 144 | |
49cd740b JP |
145 | #define wrmsr(msr, val1, val2) \ |
146 | do { \ | |
f8822f42 | 147 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 148 | } while (0) |
d3561b7f | 149 | |
49cd740b JP |
150 | #define rdmsrl(msr, val) \ |
151 | do { \ | |
f8822f42 JF |
152 | int _err; \ |
153 | val = paravirt_read_msr(msr, &_err); \ | |
49cd740b | 154 | } while (0) |
d3561b7f | 155 | |
49cd740b JP |
156 | #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) |
157 | #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b) | |
d3561b7f RR |
158 | |
159 | /* rdmsr with exception handling */ | |
49cd740b JP |
160 | #define rdmsr_safe(msr, a, b) \ |
161 | ({ \ | |
f8822f42 JF |
162 | int _err; \ |
163 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
164 | (*a) = (u32)_l; \ | |
165 | (*b) = _l >> 32; \ | |
49cd740b JP |
166 | _err; \ |
167 | }) | |
d3561b7f | 168 | |
1de87bd4 AK |
169 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
170 | { | |
171 | int err; | |
172 | ||
173 | *p = paravirt_read_msr(msr, &err); | |
174 | return err; | |
175 | } | |
177fed1e | 176 | |
f8822f42 JF |
177 | static inline u64 paravirt_read_tsc(void) |
178 | { | |
93b1eab3 | 179 | return PVOP_CALL0(u64, pv_cpu_ops.read_tsc); |
f8822f42 | 180 | } |
d3561b7f | 181 | |
49cd740b JP |
182 | #define rdtscl(low) \ |
183 | do { \ | |
f8822f42 JF |
184 | u64 _l = paravirt_read_tsc(); \ |
185 | low = (int)_l; \ | |
49cd740b | 186 | } while (0) |
d3561b7f | 187 | |
f8822f42 | 188 | #define rdtscll(val) (val = paravirt_read_tsc()) |
d3561b7f | 189 | |
688340ea JF |
190 | static inline unsigned long long paravirt_sched_clock(void) |
191 | { | |
93b1eab3 | 192 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 193 | } |
6cb9a835 | 194 | |
c5905afb IM |
195 | struct static_key; |
196 | extern struct static_key paravirt_steal_enabled; | |
197 | extern struct static_key paravirt_steal_rq_enabled; | |
3c404b57 GC |
198 | |
199 | static inline u64 paravirt_steal_clock(int cpu) | |
200 | { | |
201 | return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu); | |
202 | } | |
203 | ||
f8822f42 JF |
204 | static inline unsigned long long paravirt_read_pmc(int counter) |
205 | { | |
93b1eab3 | 206 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 207 | } |
d3561b7f | 208 | |
49cd740b JP |
209 | #define rdpmc(counter, low, high) \ |
210 | do { \ | |
f8822f42 JF |
211 | u64 _l = paravirt_read_pmc(counter); \ |
212 | low = (u32)_l; \ | |
213 | high = _l >> 32; \ | |
49cd740b | 214 | } while (0) |
3dc494e8 | 215 | |
1ff4d58a AK |
216 | #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) |
217 | ||
e5aaac44 GOC |
218 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) |
219 | { | |
220 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); | |
221 | } | |
222 | ||
223 | #define rdtscp(low, high, aux) \ | |
224 | do { \ | |
225 | int __aux; \ | |
226 | unsigned long __val = paravirt_rdtscp(&__aux); \ | |
227 | (low) = (u32)__val; \ | |
228 | (high) = (u32)(__val >> 32); \ | |
229 | (aux) = __aux; \ | |
230 | } while (0) | |
231 | ||
232 | #define rdtscpll(val, aux) \ | |
233 | do { \ | |
234 | unsigned long __aux; \ | |
235 | val = paravirt_rdtscp(&__aux); \ | |
236 | (aux) = __aux; \ | |
237 | } while (0) | |
238 | ||
38ffbe66 JF |
239 | static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
240 | { | |
241 | PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries); | |
242 | } | |
243 | ||
244 | static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) | |
245 | { | |
246 | PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries); | |
247 | } | |
248 | ||
f8822f42 JF |
249 | static inline void load_TR_desc(void) |
250 | { | |
93b1eab3 | 251 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 252 | } |
6b68f01b | 253 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 254 | { |
93b1eab3 | 255 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 256 | } |
6b68f01b | 257 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 258 | { |
93b1eab3 | 259 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
260 | } |
261 | static inline void set_ldt(const void *addr, unsigned entries) | |
262 | { | |
93b1eab3 | 263 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 264 | } |
6b68f01b | 265 | static inline void store_gdt(struct desc_ptr *dtr) |
f8822f42 | 266 | { |
93b1eab3 | 267 | PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr); |
f8822f42 | 268 | } |
6b68f01b | 269 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 270 | { |
93b1eab3 | 271 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
272 | } |
273 | static inline unsigned long paravirt_store_tr(void) | |
274 | { | |
93b1eab3 | 275 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
276 | } |
277 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
278 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
279 | { | |
93b1eab3 | 280 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 281 | } |
75b8bb3e | 282 | |
9f9d489a JF |
283 | #ifdef CONFIG_X86_64 |
284 | static inline void load_gs_index(unsigned int gs) | |
285 | { | |
286 | PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs); | |
287 | } | |
288 | #endif | |
289 | ||
75b8bb3e GOC |
290 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, |
291 | const void *desc) | |
f8822f42 | 292 | { |
75b8bb3e | 293 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 294 | } |
014b15be GOC |
295 | |
296 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
297 | void *desc, int type) | |
f8822f42 | 298 | { |
014b15be | 299 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 300 | } |
014b15be | 301 | |
8d947344 | 302 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 303 | { |
8d947344 | 304 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
305 | } |
306 | static inline void set_iopl_mask(unsigned mask) | |
307 | { | |
93b1eab3 | 308 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 309 | } |
3dc494e8 | 310 | |
d3561b7f | 311 | /* The paravirtualized I/O functions */ |
49cd740b JP |
312 | static inline void slow_down_io(void) |
313 | { | |
93b1eab3 | 314 | pv_cpu_ops.io_delay(); |
d3561b7f | 315 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
316 | pv_cpu_ops.io_delay(); |
317 | pv_cpu_ops.io_delay(); | |
318 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
319 | #endif |
320 | } | |
321 | ||
ae5da273 ZA |
322 | #ifdef CONFIG_SMP |
323 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
324 | unsigned long start_esp) | |
325 | { | |
93b1eab3 JF |
326 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
327 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
328 | } |
329 | #endif | |
13623d79 | 330 | |
d6dd61c8 JF |
331 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
332 | struct mm_struct *next) | |
333 | { | |
93b1eab3 | 334 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
335 | } |
336 | ||
337 | static inline void arch_dup_mmap(struct mm_struct *oldmm, | |
338 | struct mm_struct *mm) | |
339 | { | |
93b1eab3 | 340 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
341 | } |
342 | ||
343 | static inline void arch_exit_mmap(struct mm_struct *mm) | |
344 | { | |
93b1eab3 | 345 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
346 | } |
347 | ||
f8822f42 JF |
348 | static inline void __flush_tlb(void) |
349 | { | |
93b1eab3 | 350 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
351 | } |
352 | static inline void __flush_tlb_global(void) | |
353 | { | |
93b1eab3 | 354 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
355 | } |
356 | static inline void __flush_tlb_single(unsigned long addr) | |
357 | { | |
93b1eab3 | 358 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 359 | } |
da181a8b | 360 | |
4595f962 RR |
361 | static inline void flush_tlb_others(const struct cpumask *cpumask, |
362 | struct mm_struct *mm, | |
e7b52ffd AS |
363 | unsigned long start, |
364 | unsigned long end) | |
d4c10477 | 365 | { |
e7b52ffd | 366 | PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end); |
d4c10477 JF |
367 | } |
368 | ||
eba0045f JF |
369 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
370 | { | |
371 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
372 | } | |
373 | ||
374 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
375 | { | |
376 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
377 | } | |
378 | ||
f8639939 | 379 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 380 | { |
6944a9c8 | 381 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 382 | } |
f8639939 | 383 | static inline void paravirt_release_pte(unsigned long pfn) |
f8822f42 | 384 | { |
6944a9c8 | 385 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 386 | } |
c119ecce | 387 | |
f8639939 | 388 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 389 | { |
6944a9c8 | 390 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 391 | } |
c119ecce | 392 | |
f8639939 | 393 | static inline void paravirt_release_pmd(unsigned long pfn) |
da181a8b | 394 | { |
6944a9c8 | 395 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
396 | } |
397 | ||
f8639939 | 398 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn) |
2761fa09 JF |
399 | { |
400 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
401 | } | |
f8639939 | 402 | static inline void paravirt_release_pud(unsigned long pfn) |
2761fa09 JF |
403 | { |
404 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
405 | } | |
406 | ||
f8822f42 JF |
407 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
408 | pte_t *ptep) | |
da181a8b | 409 | { |
93b1eab3 | 410 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b | 411 | } |
331127f7 AA |
412 | static inline void pmd_update(struct mm_struct *mm, unsigned long addr, |
413 | pmd_t *pmdp) | |
414 | { | |
415 | PVOP_VCALL3(pv_mmu_ops.pmd_update, mm, addr, pmdp); | |
416 | } | |
da181a8b | 417 | |
f8822f42 JF |
418 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
419 | pte_t *ptep) | |
da181a8b | 420 | { |
93b1eab3 | 421 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
422 | } |
423 | ||
331127f7 AA |
424 | static inline void pmd_update_defer(struct mm_struct *mm, unsigned long addr, |
425 | pmd_t *pmdp) | |
426 | { | |
427 | PVOP_VCALL3(pv_mmu_ops.pmd_update_defer, mm, addr, pmdp); | |
428 | } | |
429 | ||
773221f4 | 430 | static inline pte_t __pte(pteval_t val) |
da181a8b | 431 | { |
773221f4 JF |
432 | pteval_t ret; |
433 | ||
434 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
435 | ret = PVOP_CALLEE2(pteval_t, |
436 | pv_mmu_ops.make_pte, | |
437 | val, (u64)val >> 32); | |
773221f4 | 438 | else |
da5de7c2 JF |
439 | ret = PVOP_CALLEE1(pteval_t, |
440 | pv_mmu_ops.make_pte, | |
441 | val); | |
773221f4 | 442 | |
c8e5393a | 443 | return (pte_t) { .pte = ret }; |
da181a8b RR |
444 | } |
445 | ||
773221f4 JF |
446 | static inline pteval_t pte_val(pte_t pte) |
447 | { | |
448 | pteval_t ret; | |
449 | ||
450 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
451 | ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val, |
452 | pte.pte, (u64)pte.pte >> 32); | |
773221f4 | 453 | else |
da5de7c2 JF |
454 | ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val, |
455 | pte.pte); | |
773221f4 JF |
456 | |
457 | return ret; | |
458 | } | |
459 | ||
ef38503e | 460 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 461 | { |
ef38503e JF |
462 | pgdval_t ret; |
463 | ||
464 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
465 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd, |
466 | val, (u64)val >> 32); | |
ef38503e | 467 | else |
da5de7c2 JF |
468 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd, |
469 | val); | |
ef38503e JF |
470 | |
471 | return (pgd_t) { ret }; | |
472 | } | |
473 | ||
474 | static inline pgdval_t pgd_val(pgd_t pgd) | |
475 | { | |
476 | pgdval_t ret; | |
477 | ||
478 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
479 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val, |
480 | pgd.pgd, (u64)pgd.pgd >> 32); | |
ef38503e | 481 | else |
da5de7c2 JF |
482 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val, |
483 | pgd.pgd); | |
ef38503e JF |
484 | |
485 | return ret; | |
f8822f42 JF |
486 | } |
487 | ||
08b882c6 JF |
488 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
489 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
490 | pte_t *ptep) | |
491 | { | |
492 | pteval_t ret; | |
493 | ||
494 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
495 | mm, addr, ptep); | |
496 | ||
497 | return (pte_t) { .pte = ret }; | |
498 | } | |
499 | ||
500 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
501 | pte_t *ptep, pte_t pte) | |
502 | { | |
503 | if (sizeof(pteval_t) > sizeof(long)) | |
504 | /* 5 arg words */ | |
505 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
506 | else | |
507 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
508 | mm, addr, ptep, pte.pte); | |
509 | } | |
510 | ||
4eed80cd JF |
511 | static inline void set_pte(pte_t *ptep, pte_t pte) |
512 | { | |
513 | if (sizeof(pteval_t) > sizeof(long)) | |
514 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
515 | pte.pte, (u64)pte.pte >> 32); | |
516 | else | |
517 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
518 | pte.pte); | |
519 | } | |
520 | ||
521 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
522 | pte_t *ptep, pte_t pte) | |
523 | { | |
524 | if (sizeof(pteval_t) > sizeof(long)) | |
525 | /* 5 arg words */ | |
526 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
527 | else | |
528 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
529 | } | |
530 | ||
331127f7 AA |
531 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
532 | pmd_t *pmdp, pmd_t pmd) | |
533 | { | |
331127f7 AA |
534 | if (sizeof(pmdval_t) > sizeof(long)) |
535 | /* 5 arg words */ | |
536 | pv_mmu_ops.set_pmd_at(mm, addr, pmdp, pmd); | |
537 | else | |
cacf061c AA |
538 | PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp, |
539 | native_pmd_val(pmd)); | |
331127f7 | 540 | } |
331127f7 | 541 | |
60b3f626 JF |
542 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
543 | { | |
544 | pmdval_t val = native_pmd_val(pmd); | |
545 | ||
546 | if (sizeof(pmdval_t) > sizeof(long)) | |
547 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
548 | else | |
549 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
550 | } | |
551 | ||
1fe91514 GOC |
552 | #if PAGETABLE_LEVELS >= 3 |
553 | static inline pmd_t __pmd(pmdval_t val) | |
554 | { | |
555 | pmdval_t ret; | |
556 | ||
557 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
558 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd, |
559 | val, (u64)val >> 32); | |
1fe91514 | 560 | else |
da5de7c2 JF |
561 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd, |
562 | val); | |
1fe91514 GOC |
563 | |
564 | return (pmd_t) { ret }; | |
565 | } | |
566 | ||
567 | static inline pmdval_t pmd_val(pmd_t pmd) | |
568 | { | |
569 | pmdval_t ret; | |
570 | ||
571 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
572 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val, |
573 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1fe91514 | 574 | else |
da5de7c2 JF |
575 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val, |
576 | pmd.pmd); | |
1fe91514 GOC |
577 | |
578 | return ret; | |
579 | } | |
580 | ||
581 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
582 | { | |
583 | pudval_t val = native_pud_val(pud); | |
584 | ||
585 | if (sizeof(pudval_t) > sizeof(long)) | |
586 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
587 | val, (u64)val >> 32); | |
588 | else | |
589 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
590 | val); | |
591 | } | |
9042219c EH |
592 | #if PAGETABLE_LEVELS == 4 |
593 | static inline pud_t __pud(pudval_t val) | |
594 | { | |
595 | pudval_t ret; | |
596 | ||
597 | if (sizeof(pudval_t) > sizeof(long)) | |
da5de7c2 JF |
598 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud, |
599 | val, (u64)val >> 32); | |
9042219c | 600 | else |
da5de7c2 JF |
601 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud, |
602 | val); | |
9042219c EH |
603 | |
604 | return (pud_t) { ret }; | |
605 | } | |
606 | ||
607 | static inline pudval_t pud_val(pud_t pud) | |
608 | { | |
609 | pudval_t ret; | |
610 | ||
611 | if (sizeof(pudval_t) > sizeof(long)) | |
4767afbf JF |
612 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val, |
613 | pud.pud, (u64)pud.pud >> 32); | |
9042219c | 614 | else |
4767afbf JF |
615 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val, |
616 | pud.pud); | |
9042219c EH |
617 | |
618 | return ret; | |
619 | } | |
620 | ||
621 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
622 | { | |
623 | pgdval_t val = native_pgd_val(pgd); | |
624 | ||
625 | if (sizeof(pgdval_t) > sizeof(long)) | |
626 | PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp, | |
627 | val, (u64)val >> 32); | |
628 | else | |
629 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, | |
630 | val); | |
631 | } | |
632 | ||
633 | static inline void pgd_clear(pgd_t *pgdp) | |
634 | { | |
635 | set_pgd(pgdp, __pgd(0)); | |
636 | } | |
637 | ||
638 | static inline void pud_clear(pud_t *pudp) | |
639 | { | |
640 | set_pud(pudp, __pud(0)); | |
641 | } | |
642 | ||
643 | #endif /* PAGETABLE_LEVELS == 4 */ | |
644 | ||
1fe91514 GOC |
645 | #endif /* PAGETABLE_LEVELS >= 3 */ |
646 | ||
4eed80cd JF |
647 | #ifdef CONFIG_X86_PAE |
648 | /* Special-case pte-setting operations for PAE, which can't update a | |
649 | 64-bit pte atomically */ | |
650 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
651 | { | |
652 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
653 | pte.pte, pte.pte >> 32); | |
654 | } | |
655 | ||
4eed80cd JF |
656 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
657 | pte_t *ptep) | |
658 | { | |
659 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
660 | } | |
60b3f626 JF |
661 | |
662 | static inline void pmd_clear(pmd_t *pmdp) | |
663 | { | |
664 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
665 | } | |
4eed80cd JF |
666 | #else /* !CONFIG_X86_PAE */ |
667 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
668 | { | |
669 | set_pte(ptep, pte); | |
670 | } | |
671 | ||
4eed80cd JF |
672 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
673 | pte_t *ptep) | |
674 | { | |
675 | set_pte_at(mm, addr, ptep, __pte(0)); | |
676 | } | |
60b3f626 JF |
677 | |
678 | static inline void pmd_clear(pmd_t *pmdp) | |
679 | { | |
680 | set_pmd(pmdp, __pmd(0)); | |
681 | } | |
4eed80cd JF |
682 | #endif /* CONFIG_X86_PAE */ |
683 | ||
7fd7d83d | 684 | #define __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 685 | static inline void arch_start_context_switch(struct task_struct *prev) |
f8822f42 | 686 | { |
224101ed | 687 | PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev); |
f8822f42 JF |
688 | } |
689 | ||
224101ed | 690 | static inline void arch_end_context_switch(struct task_struct *next) |
f8822f42 | 691 | { |
224101ed | 692 | PVOP_VCALL1(pv_cpu_ops.end_context_switch, next); |
f8822f42 JF |
693 | } |
694 | ||
9226d125 | 695 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
f8822f42 JF |
696 | static inline void arch_enter_lazy_mmu_mode(void) |
697 | { | |
8965c1c0 | 698 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
699 | } |
700 | ||
701 | static inline void arch_leave_lazy_mmu_mode(void) | |
702 | { | |
8965c1c0 | 703 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
704 | } |
705 | ||
d85cf93d | 706 | void arch_flush_lazy_mmu_mode(void); |
9226d125 | 707 | |
aeaaa59c | 708 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
3b3809ac | 709 | phys_addr_t phys, pgprot_t flags) |
aeaaa59c JF |
710 | { |
711 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
712 | } | |
713 | ||
b4ecc126 | 714 | #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS) |
4bb689ee | 715 | |
0199c4e6 | 716 | static inline int arch_spin_is_locked(struct arch_spinlock *lock) |
74d4affd JF |
717 | { |
718 | return PVOP_CALL1(int, pv_lock_ops.spin_is_locked, lock); | |
719 | } | |
720 | ||
0199c4e6 | 721 | static inline int arch_spin_is_contended(struct arch_spinlock *lock) |
74d4affd JF |
722 | { |
723 | return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock); | |
724 | } | |
0199c4e6 | 725 | #define arch_spin_is_contended arch_spin_is_contended |
74d4affd | 726 | |
0199c4e6 | 727 | static __always_inline void arch_spin_lock(struct arch_spinlock *lock) |
74d4affd | 728 | { |
32172561 | 729 | PVOP_VCALL1(pv_lock_ops.spin_lock, lock); |
74d4affd JF |
730 | } |
731 | ||
0199c4e6 | 732 | static __always_inline void arch_spin_lock_flags(struct arch_spinlock *lock, |
63d3a75d JF |
733 | unsigned long flags) |
734 | { | |
735 | PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags); | |
736 | } | |
737 | ||
0199c4e6 | 738 | static __always_inline int arch_spin_trylock(struct arch_spinlock *lock) |
74d4affd JF |
739 | { |
740 | return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock); | |
741 | } | |
742 | ||
0199c4e6 | 743 | static __always_inline void arch_spin_unlock(struct arch_spinlock *lock) |
74d4affd | 744 | { |
32172561 | 745 | PVOP_VCALL1(pv_lock_ops.spin_unlock, lock); |
74d4affd JF |
746 | } |
747 | ||
4bb689ee IM |
748 | #endif |
749 | ||
2e47d3e6 | 750 | #ifdef CONFIG_X86_32 |
ecb93d1c JF |
751 | #define PV_SAVE_REGS "pushl %ecx; pushl %edx;" |
752 | #define PV_RESTORE_REGS "popl %edx; popl %ecx;" | |
753 | ||
754 | /* save and restore all caller-save registers, except return value */ | |
e584f559 JF |
755 | #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" |
756 | #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" | |
ecb93d1c | 757 | |
2e47d3e6 GOC |
758 | #define PV_FLAGS_ARG "0" |
759 | #define PV_EXTRA_CLOBBERS | |
760 | #define PV_VEXTRA_CLOBBERS | |
761 | #else | |
ecb93d1c JF |
762 | /* save and restore all caller-save registers, except return value */ |
763 | #define PV_SAVE_ALL_CALLER_REGS \ | |
764 | "push %rcx;" \ | |
765 | "push %rdx;" \ | |
766 | "push %rsi;" \ | |
767 | "push %rdi;" \ | |
768 | "push %r8;" \ | |
769 | "push %r9;" \ | |
770 | "push %r10;" \ | |
771 | "push %r11;" | |
772 | #define PV_RESTORE_ALL_CALLER_REGS \ | |
773 | "pop %r11;" \ | |
774 | "pop %r10;" \ | |
775 | "pop %r9;" \ | |
776 | "pop %r8;" \ | |
777 | "pop %rdi;" \ | |
778 | "pop %rsi;" \ | |
779 | "pop %rdx;" \ | |
780 | "pop %rcx;" | |
781 | ||
2e47d3e6 GOC |
782 | /* We save some registers, but all of them, that's too much. We clobber all |
783 | * caller saved registers but the argument parameter */ | |
784 | #define PV_SAVE_REGS "pushq %%rdi;" | |
785 | #define PV_RESTORE_REGS "popq %%rdi;" | |
c24481e9 JF |
786 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi" |
787 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi" | |
2e47d3e6 GOC |
788 | #define PV_FLAGS_ARG "D" |
789 | #endif | |
790 | ||
ecb93d1c JF |
791 | /* |
792 | * Generate a thunk around a function which saves all caller-save | |
793 | * registers except for the return value. This allows C functions to | |
794 | * be called from assembler code where fewer than normal registers are | |
795 | * available. It may also help code generation around calls from C | |
796 | * code if the common case doesn't use many registers. | |
797 | * | |
798 | * When a callee is wrapped in a thunk, the caller can assume that all | |
799 | * arg regs and all scratch registers are preserved across the | |
800 | * call. The return value in rax/eax will not be saved, even for void | |
801 | * functions. | |
802 | */ | |
803 | #define PV_CALLEE_SAVE_REGS_THUNK(func) \ | |
804 | extern typeof(func) __raw_callee_save_##func; \ | |
805 | static void *__##func##__ __used = func; \ | |
806 | \ | |
807 | asm(".pushsection .text;" \ | |
808 | "__raw_callee_save_" #func ": " \ | |
809 | PV_SAVE_ALL_CALLER_REGS \ | |
810 | "call " #func ";" \ | |
811 | PV_RESTORE_ALL_CALLER_REGS \ | |
812 | "ret;" \ | |
813 | ".popsection") | |
814 | ||
815 | /* Get a reference to a callee-save function */ | |
816 | #define PV_CALLEE_SAVE(func) \ | |
817 | ((struct paravirt_callee_save) { __raw_callee_save_##func }) | |
818 | ||
819 | /* Promise that "func" already uses the right calling convention */ | |
820 | #define __PV_IS_CALLEE_SAVE(func) \ | |
821 | ((struct paravirt_callee_save) { func }) | |
822 | ||
b5908548 | 823 | static inline notrace unsigned long arch_local_save_flags(void) |
139ec7c4 | 824 | { |
71999d98 | 825 | return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl); |
139ec7c4 RR |
826 | } |
827 | ||
b5908548 | 828 | static inline notrace void arch_local_irq_restore(unsigned long f) |
139ec7c4 | 829 | { |
71999d98 | 830 | PVOP_VCALLEE1(pv_irq_ops.restore_fl, f); |
139ec7c4 RR |
831 | } |
832 | ||
b5908548 | 833 | static inline notrace void arch_local_irq_disable(void) |
139ec7c4 | 834 | { |
71999d98 | 835 | PVOP_VCALLEE0(pv_irq_ops.irq_disable); |
139ec7c4 RR |
836 | } |
837 | ||
b5908548 | 838 | static inline notrace void arch_local_irq_enable(void) |
139ec7c4 | 839 | { |
71999d98 | 840 | PVOP_VCALLEE0(pv_irq_ops.irq_enable); |
139ec7c4 RR |
841 | } |
842 | ||
b5908548 | 843 | static inline notrace unsigned long arch_local_irq_save(void) |
139ec7c4 RR |
844 | { |
845 | unsigned long f; | |
846 | ||
df9ee292 DH |
847 | f = arch_local_save_flags(); |
848 | arch_local_irq_disable(); | |
139ec7c4 RR |
849 | return f; |
850 | } | |
851 | ||
74d4affd | 852 | |
294688c0 | 853 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 854 | #undef PARAVIRT_CALL |
1a45b7aa JF |
855 | #undef __PVOP_CALL |
856 | #undef __PVOP_VCALL | |
f8822f42 JF |
857 | #undef PVOP_VCALL0 |
858 | #undef PVOP_CALL0 | |
859 | #undef PVOP_VCALL1 | |
860 | #undef PVOP_CALL1 | |
861 | #undef PVOP_VCALL2 | |
862 | #undef PVOP_CALL2 | |
863 | #undef PVOP_VCALL3 | |
864 | #undef PVOP_CALL3 | |
865 | #undef PVOP_VCALL4 | |
866 | #undef PVOP_CALL4 | |
139ec7c4 | 867 | |
6f30c1ac TG |
868 | extern void default_banner(void); |
869 | ||
d3561b7f RR |
870 | #else /* __ASSEMBLY__ */ |
871 | ||
658be9d3 | 872 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
873 | 771:; \ |
874 | ops; \ | |
875 | 772:; \ | |
876 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
877 | .align algn; \ |
878 | word 771b; \ | |
139ec7c4 RR |
879 | .byte ptype; \ |
880 | .byte 772b-771b; \ | |
881 | .short clobbers; \ | |
882 | .popsection | |
883 | ||
658be9d3 | 884 | |
9104a18d | 885 | #define COND_PUSH(set, mask, reg) \ |
ecb93d1c | 886 | .if ((~(set)) & mask); push %reg; .endif |
9104a18d | 887 | #define COND_POP(set, mask, reg) \ |
ecb93d1c | 888 | .if ((~(set)) & mask); pop %reg; .endif |
9104a18d | 889 | |
658be9d3 | 890 | #ifdef CONFIG_X86_64 |
9104a18d JF |
891 | |
892 | #define PV_SAVE_REGS(set) \ | |
893 | COND_PUSH(set, CLBR_RAX, rax); \ | |
894 | COND_PUSH(set, CLBR_RCX, rcx); \ | |
895 | COND_PUSH(set, CLBR_RDX, rdx); \ | |
896 | COND_PUSH(set, CLBR_RSI, rsi); \ | |
897 | COND_PUSH(set, CLBR_RDI, rdi); \ | |
898 | COND_PUSH(set, CLBR_R8, r8); \ | |
899 | COND_PUSH(set, CLBR_R9, r9); \ | |
900 | COND_PUSH(set, CLBR_R10, r10); \ | |
901 | COND_PUSH(set, CLBR_R11, r11) | |
902 | #define PV_RESTORE_REGS(set) \ | |
903 | COND_POP(set, CLBR_R11, r11); \ | |
904 | COND_POP(set, CLBR_R10, r10); \ | |
905 | COND_POP(set, CLBR_R9, r9); \ | |
906 | COND_POP(set, CLBR_R8, r8); \ | |
907 | COND_POP(set, CLBR_RDI, rdi); \ | |
908 | COND_POP(set, CLBR_RSI, rsi); \ | |
909 | COND_POP(set, CLBR_RDX, rdx); \ | |
910 | COND_POP(set, CLBR_RCX, rcx); \ | |
911 | COND_POP(set, CLBR_RAX, rax) | |
912 | ||
6057fc82 | 913 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) |
658be9d3 | 914 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 915 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 916 | #else |
9104a18d JF |
917 | #define PV_SAVE_REGS(set) \ |
918 | COND_PUSH(set, CLBR_EAX, eax); \ | |
919 | COND_PUSH(set, CLBR_EDI, edi); \ | |
920 | COND_PUSH(set, CLBR_ECX, ecx); \ | |
921 | COND_PUSH(set, CLBR_EDX, edx) | |
922 | #define PV_RESTORE_REGS(set) \ | |
923 | COND_POP(set, CLBR_EDX, edx); \ | |
924 | COND_POP(set, CLBR_ECX, ecx); \ | |
925 | COND_POP(set, CLBR_EDI, edi); \ | |
926 | COND_POP(set, CLBR_EAX, eax) | |
927 | ||
6057fc82 | 928 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) |
658be9d3 | 929 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 930 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
931 | #endif |
932 | ||
93b1eab3 JF |
933 | #define INTERRUPT_RETURN \ |
934 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 935 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
936 | |
937 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 938 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
ecb93d1c | 939 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 940 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ |
ecb93d1c | 941 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 JF |
942 | |
943 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 944 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
ecb93d1c | 945 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 946 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ |
ecb93d1c | 947 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 | 948 | |
2be29982 JF |
949 | #define USERGS_SYSRET32 \ |
950 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \ | |
6abcd98f | 951 | CLBR_NONE, \ |
2be29982 | 952 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32)) |
2e47d3e6 | 953 | |
6057fc82 | 954 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
955 | #define GET_CR0_INTO_EAX \ |
956 | push %ecx; push %edx; \ | |
957 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 958 | pop %edx; pop %ecx |
2be29982 JF |
959 | |
960 | #define ENABLE_INTERRUPTS_SYSEXIT \ | |
961 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \ | |
962 | CLBR_NONE, \ | |
963 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit)) | |
964 | ||
965 | ||
966 | #else /* !CONFIG_X86_32 */ | |
a00394f8 JF |
967 | |
968 | /* | |
969 | * If swapgs is used while the userspace stack is still current, | |
970 | * there's no way to call a pvop. The PV replacement *must* be | |
971 | * inlined, or the swapgs instruction must be trapped and emulated. | |
972 | */ | |
973 | #define SWAPGS_UNSAFE_STACK \ | |
974 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
975 | swapgs) | |
976 | ||
9104a18d JF |
977 | /* |
978 | * Note: swapgs is very special, and in practise is either going to be | |
979 | * implemented with a single "swapgs" instruction or something very | |
980 | * special. Either way, we don't need to save any registers for | |
981 | * it. | |
982 | */ | |
e801f864 GOC |
983 | #define SWAPGS \ |
984 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
9104a18d | 985 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \ |
e801f864 GOC |
986 | ) |
987 | ||
ffc4bc9c PA |
988 | #define GET_CR2_INTO_RAX \ |
989 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2) | |
4a8c4c4e | 990 | |
fab58420 JF |
991 | #define PARAVIRT_ADJUST_EXCEPTION_FRAME \ |
992 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \ | |
993 | CLBR_NONE, \ | |
994 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame)) | |
995 | ||
2be29982 JF |
996 | #define USERGS_SYSRET64 \ |
997 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ | |
d75cd22f | 998 | CLBR_NONE, \ |
2be29982 JF |
999 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) |
1000 | ||
1001 | #define ENABLE_INTERRUPTS_SYSEXIT32 \ | |
1002 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \ | |
1003 | CLBR_NONE, \ | |
1004 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit)) | |
1005 | #endif /* CONFIG_X86_32 */ | |
139ec7c4 | 1006 | |
d3561b7f | 1007 | #endif /* __ASSEMBLY__ */ |
6f30c1ac TG |
1008 | #else /* CONFIG_PARAVIRT */ |
1009 | # define default_banner x86_init_noop | |
1010 | #endif /* !CONFIG_PARAVIRT */ | |
1965aae3 | 1011 | #endif /* _ASM_X86_PARAVIRT_H */ |