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1965aae3 PA |
1 | #ifndef _ASM_X86_PARAVIRT_H |
2 | #define _ASM_X86_PARAVIRT_H | |
d3561b7f RR |
3 | /* Various instructions on x86 need to be replaced for |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
54321d94 | 7 | #include <asm/pgtable_types.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
ac5672f8 | 10 | #include <asm/paravirt_types.h> |
ecb93d1c | 11 | |
d3561b7f | 12 | #ifndef __ASSEMBLY__ |
187f1882 | 13 | #include <linux/bug.h> |
3dc494e8 | 14 | #include <linux/types.h> |
d4c10477 | 15 | #include <linux/cpumask.h> |
87b240cb | 16 | #include <asm/frame.h> |
1a45b7aa | 17 | |
faca6227 | 18 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
19 | struct thread_struct *thread) |
20 | { | |
faca6227 | 21 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
22 | } |
23 | ||
d3561b7f RR |
24 | /* The paravirtualized CPUID instruction. */ |
25 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
26 | unsigned int *ecx, unsigned int *edx) | |
27 | { | |
93b1eab3 | 28 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
29 | } |
30 | ||
31 | /* | |
32 | * These special macros can be used to get or set a debugging register | |
33 | */ | |
f8822f42 JF |
34 | static inline unsigned long paravirt_get_debugreg(int reg) |
35 | { | |
93b1eab3 | 36 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
37 | } |
38 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
39 | static inline void set_debugreg(unsigned long val, int reg) | |
40 | { | |
93b1eab3 | 41 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 42 | } |
d3561b7f | 43 | |
f8822f42 JF |
44 | static inline unsigned long read_cr0(void) |
45 | { | |
93b1eab3 | 46 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 47 | } |
d3561b7f | 48 | |
f8822f42 JF |
49 | static inline void write_cr0(unsigned long x) |
50 | { | |
93b1eab3 | 51 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
52 | } |
53 | ||
54 | static inline unsigned long read_cr2(void) | |
55 | { | |
93b1eab3 | 56 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
57 | } |
58 | ||
59 | static inline void write_cr2(unsigned long x) | |
60 | { | |
93b1eab3 | 61 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
62 | } |
63 | ||
64 | static inline unsigned long read_cr3(void) | |
65 | { | |
93b1eab3 | 66 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 67 | } |
d3561b7f | 68 | |
f8822f42 JF |
69 | static inline void write_cr3(unsigned long x) |
70 | { | |
93b1eab3 | 71 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 72 | } |
d3561b7f | 73 | |
1e02ce4c | 74 | static inline unsigned long __read_cr4(void) |
f8822f42 | 75 | { |
93b1eab3 | 76 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 | 77 | } |
d3561b7f | 78 | |
1e02ce4c | 79 | static inline void __write_cr4(unsigned long x) |
f8822f42 | 80 | { |
93b1eab3 | 81 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 82 | } |
3dc494e8 | 83 | |
94ea03cd | 84 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
85 | static inline unsigned long read_cr8(void) |
86 | { | |
87 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
88 | } | |
89 | ||
90 | static inline void write_cr8(unsigned long x) | |
91 | { | |
92 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
93 | } | |
94ea03cd | 94 | #endif |
4c9890c2 | 95 | |
df9ee292 | 96 | static inline void arch_safe_halt(void) |
d3561b7f | 97 | { |
93b1eab3 | 98 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
99 | } |
100 | ||
101 | static inline void halt(void) | |
102 | { | |
c8217b83 | 103 | PVOP_VCALL0(pv_irq_ops.halt); |
f8822f42 JF |
104 | } |
105 | ||
106 | static inline void wbinvd(void) | |
107 | { | |
93b1eab3 | 108 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 109 | } |
d3561b7f | 110 | |
93b1eab3 | 111 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 112 | |
dd2f4a00 AL |
113 | static inline u64 paravirt_read_msr(unsigned msr) |
114 | { | |
115 | return PVOP_CALL1(u64, pv_cpu_ops.read_msr, msr); | |
116 | } | |
117 | ||
118 | static inline void paravirt_write_msr(unsigned msr, | |
119 | unsigned low, unsigned high) | |
120 | { | |
121 | return PVOP_VCALL3(pv_cpu_ops.write_msr, msr, low, high); | |
122 | } | |
123 | ||
c2ee03b2 | 124 | static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) |
f8822f42 | 125 | { |
c2ee03b2 | 126 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr_safe, msr, err); |
f8822f42 | 127 | } |
132ec92f | 128 | |
c2ee03b2 AL |
129 | static inline int paravirt_write_msr_safe(unsigned msr, |
130 | unsigned low, unsigned high) | |
f8822f42 | 131 | { |
c2ee03b2 | 132 | return PVOP_CALL3(int, pv_cpu_ops.write_msr_safe, msr, low, high); |
f8822f42 JF |
133 | } |
134 | ||
49cd740b JP |
135 | #define rdmsr(msr, val1, val2) \ |
136 | do { \ | |
4985ce15 | 137 | u64 _l = paravirt_read_msr(msr); \ |
f8822f42 JF |
138 | val1 = (u32)_l; \ |
139 | val2 = _l >> 32; \ | |
49cd740b | 140 | } while (0) |
d3561b7f | 141 | |
49cd740b JP |
142 | #define wrmsr(msr, val1, val2) \ |
143 | do { \ | |
4985ce15 | 144 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 145 | } while (0) |
d3561b7f | 146 | |
49cd740b JP |
147 | #define rdmsrl(msr, val) \ |
148 | do { \ | |
4985ce15 | 149 | val = paravirt_read_msr(msr); \ |
49cd740b | 150 | } while (0) |
d3561b7f | 151 | |
47edb651 AL |
152 | static inline void wrmsrl(unsigned msr, u64 val) |
153 | { | |
154 | wrmsr(msr, (u32)val, (u32)(val>>32)); | |
155 | } | |
156 | ||
c2ee03b2 | 157 | #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b) |
d3561b7f RR |
158 | |
159 | /* rdmsr with exception handling */ | |
c2ee03b2 AL |
160 | #define rdmsr_safe(msr, a, b) \ |
161 | ({ \ | |
162 | int _err; \ | |
163 | u64 _l = paravirt_read_msr_safe(msr, &_err); \ | |
164 | (*a) = (u32)_l; \ | |
165 | (*b) = _l >> 32; \ | |
166 | _err; \ | |
49cd740b | 167 | }) |
d3561b7f | 168 | |
1de87bd4 AK |
169 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
170 | { | |
171 | int err; | |
172 | ||
c2ee03b2 | 173 | *p = paravirt_read_msr_safe(msr, &err); |
1de87bd4 AK |
174 | return err; |
175 | } | |
177fed1e | 176 | |
688340ea JF |
177 | static inline unsigned long long paravirt_sched_clock(void) |
178 | { | |
93b1eab3 | 179 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 180 | } |
6cb9a835 | 181 | |
c5905afb IM |
182 | struct static_key; |
183 | extern struct static_key paravirt_steal_enabled; | |
184 | extern struct static_key paravirt_steal_rq_enabled; | |
3c404b57 GC |
185 | |
186 | static inline u64 paravirt_steal_clock(int cpu) | |
187 | { | |
188 | return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu); | |
189 | } | |
190 | ||
f8822f42 JF |
191 | static inline unsigned long long paravirt_read_pmc(int counter) |
192 | { | |
93b1eab3 | 193 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 194 | } |
d3561b7f | 195 | |
49cd740b JP |
196 | #define rdpmc(counter, low, high) \ |
197 | do { \ | |
f8822f42 JF |
198 | u64 _l = paravirt_read_pmc(counter); \ |
199 | low = (u32)_l; \ | |
200 | high = _l >> 32; \ | |
49cd740b | 201 | } while (0) |
3dc494e8 | 202 | |
1ff4d58a AK |
203 | #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) |
204 | ||
38ffbe66 JF |
205 | static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
206 | { | |
207 | PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries); | |
208 | } | |
209 | ||
210 | static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) | |
211 | { | |
212 | PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries); | |
213 | } | |
214 | ||
f8822f42 JF |
215 | static inline void load_TR_desc(void) |
216 | { | |
93b1eab3 | 217 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 218 | } |
6b68f01b | 219 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 220 | { |
93b1eab3 | 221 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 222 | } |
6b68f01b | 223 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 224 | { |
93b1eab3 | 225 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
226 | } |
227 | static inline void set_ldt(const void *addr, unsigned entries) | |
228 | { | |
93b1eab3 | 229 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 230 | } |
6b68f01b | 231 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 232 | { |
93b1eab3 | 233 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
234 | } |
235 | static inline unsigned long paravirt_store_tr(void) | |
236 | { | |
93b1eab3 | 237 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
238 | } |
239 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
240 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
241 | { | |
93b1eab3 | 242 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 243 | } |
75b8bb3e | 244 | |
9f9d489a JF |
245 | #ifdef CONFIG_X86_64 |
246 | static inline void load_gs_index(unsigned int gs) | |
247 | { | |
248 | PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs); | |
249 | } | |
250 | #endif | |
251 | ||
75b8bb3e GOC |
252 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, |
253 | const void *desc) | |
f8822f42 | 254 | { |
75b8bb3e | 255 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 256 | } |
014b15be GOC |
257 | |
258 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
259 | void *desc, int type) | |
f8822f42 | 260 | { |
014b15be | 261 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 262 | } |
014b15be | 263 | |
8d947344 | 264 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 265 | { |
8d947344 | 266 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
267 | } |
268 | static inline void set_iopl_mask(unsigned mask) | |
269 | { | |
93b1eab3 | 270 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 271 | } |
3dc494e8 | 272 | |
d3561b7f | 273 | /* The paravirtualized I/O functions */ |
49cd740b JP |
274 | static inline void slow_down_io(void) |
275 | { | |
93b1eab3 | 276 | pv_cpu_ops.io_delay(); |
d3561b7f | 277 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
278 | pv_cpu_ops.io_delay(); |
279 | pv_cpu_ops.io_delay(); | |
280 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
281 | #endif |
282 | } | |
283 | ||
d6dd61c8 JF |
284 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
285 | struct mm_struct *next) | |
286 | { | |
93b1eab3 | 287 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
288 | } |
289 | ||
a1ea1c03 DH |
290 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, |
291 | struct mm_struct *mm) | |
d6dd61c8 | 292 | { |
93b1eab3 | 293 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
294 | } |
295 | ||
a1ea1c03 | 296 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) |
d6dd61c8 | 297 | { |
93b1eab3 | 298 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
299 | } |
300 | ||
f8822f42 JF |
301 | static inline void __flush_tlb(void) |
302 | { | |
93b1eab3 | 303 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
304 | } |
305 | static inline void __flush_tlb_global(void) | |
306 | { | |
93b1eab3 | 307 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
308 | } |
309 | static inline void __flush_tlb_single(unsigned long addr) | |
310 | { | |
93b1eab3 | 311 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 312 | } |
da181a8b | 313 | |
4595f962 RR |
314 | static inline void flush_tlb_others(const struct cpumask *cpumask, |
315 | struct mm_struct *mm, | |
e7b52ffd AS |
316 | unsigned long start, |
317 | unsigned long end) | |
d4c10477 | 318 | { |
e7b52ffd | 319 | PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end); |
d4c10477 JF |
320 | } |
321 | ||
eba0045f JF |
322 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
323 | { | |
324 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
325 | } | |
326 | ||
327 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
328 | { | |
329 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
330 | } | |
331 | ||
f8639939 | 332 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 333 | { |
6944a9c8 | 334 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 335 | } |
f8639939 | 336 | static inline void paravirt_release_pte(unsigned long pfn) |
f8822f42 | 337 | { |
6944a9c8 | 338 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 339 | } |
c119ecce | 340 | |
f8639939 | 341 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 342 | { |
6944a9c8 | 343 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 344 | } |
c119ecce | 345 | |
f8639939 | 346 | static inline void paravirt_release_pmd(unsigned long pfn) |
da181a8b | 347 | { |
6944a9c8 | 348 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
349 | } |
350 | ||
f8639939 | 351 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn) |
2761fa09 JF |
352 | { |
353 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
354 | } | |
f8639939 | 355 | static inline void paravirt_release_pud(unsigned long pfn) |
2761fa09 JF |
356 | { |
357 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
358 | } | |
359 | ||
335437fb KS |
360 | static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn) |
361 | { | |
362 | PVOP_VCALL2(pv_mmu_ops.alloc_p4d, mm, pfn); | |
363 | } | |
364 | ||
365 | static inline void paravirt_release_p4d(unsigned long pfn) | |
366 | { | |
367 | PVOP_VCALL1(pv_mmu_ops.release_p4d, pfn); | |
368 | } | |
369 | ||
f8822f42 JF |
370 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
371 | pte_t *ptep) | |
da181a8b | 372 | { |
93b1eab3 | 373 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b | 374 | } |
331127f7 | 375 | |
773221f4 | 376 | static inline pte_t __pte(pteval_t val) |
da181a8b | 377 | { |
773221f4 JF |
378 | pteval_t ret; |
379 | ||
380 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
381 | ret = PVOP_CALLEE2(pteval_t, |
382 | pv_mmu_ops.make_pte, | |
383 | val, (u64)val >> 32); | |
773221f4 | 384 | else |
da5de7c2 JF |
385 | ret = PVOP_CALLEE1(pteval_t, |
386 | pv_mmu_ops.make_pte, | |
387 | val); | |
773221f4 | 388 | |
c8e5393a | 389 | return (pte_t) { .pte = ret }; |
da181a8b RR |
390 | } |
391 | ||
773221f4 JF |
392 | static inline pteval_t pte_val(pte_t pte) |
393 | { | |
394 | pteval_t ret; | |
395 | ||
396 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
397 | ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val, |
398 | pte.pte, (u64)pte.pte >> 32); | |
773221f4 | 399 | else |
da5de7c2 JF |
400 | ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val, |
401 | pte.pte); | |
773221f4 JF |
402 | |
403 | return ret; | |
404 | } | |
405 | ||
ef38503e | 406 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 407 | { |
ef38503e JF |
408 | pgdval_t ret; |
409 | ||
410 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
411 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd, |
412 | val, (u64)val >> 32); | |
ef38503e | 413 | else |
da5de7c2 JF |
414 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd, |
415 | val); | |
ef38503e JF |
416 | |
417 | return (pgd_t) { ret }; | |
418 | } | |
419 | ||
420 | static inline pgdval_t pgd_val(pgd_t pgd) | |
421 | { | |
422 | pgdval_t ret; | |
423 | ||
424 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
425 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val, |
426 | pgd.pgd, (u64)pgd.pgd >> 32); | |
ef38503e | 427 | else |
da5de7c2 JF |
428 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val, |
429 | pgd.pgd); | |
ef38503e JF |
430 | |
431 | return ret; | |
f8822f42 JF |
432 | } |
433 | ||
08b882c6 JF |
434 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
435 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
436 | pte_t *ptep) | |
437 | { | |
438 | pteval_t ret; | |
439 | ||
440 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
441 | mm, addr, ptep); | |
442 | ||
443 | return (pte_t) { .pte = ret }; | |
444 | } | |
445 | ||
446 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
447 | pte_t *ptep, pte_t pte) | |
448 | { | |
449 | if (sizeof(pteval_t) > sizeof(long)) | |
450 | /* 5 arg words */ | |
451 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
452 | else | |
453 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
454 | mm, addr, ptep, pte.pte); | |
455 | } | |
456 | ||
4eed80cd JF |
457 | static inline void set_pte(pte_t *ptep, pte_t pte) |
458 | { | |
459 | if (sizeof(pteval_t) > sizeof(long)) | |
460 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
461 | pte.pte, (u64)pte.pte >> 32); | |
462 | else | |
463 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
464 | pte.pte); | |
465 | } | |
466 | ||
467 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
468 | pte_t *ptep, pte_t pte) | |
469 | { | |
470 | if (sizeof(pteval_t) > sizeof(long)) | |
471 | /* 5 arg words */ | |
472 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
473 | else | |
474 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
475 | } | |
476 | ||
331127f7 AA |
477 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
478 | pmd_t *pmdp, pmd_t pmd) | |
479 | { | |
331127f7 AA |
480 | if (sizeof(pmdval_t) > sizeof(long)) |
481 | /* 5 arg words */ | |
482 | pv_mmu_ops.set_pmd_at(mm, addr, pmdp, pmd); | |
483 | else | |
cacf061c AA |
484 | PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp, |
485 | native_pmd_val(pmd)); | |
331127f7 | 486 | } |
331127f7 | 487 | |
a00cc7d9 MW |
488 | static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, |
489 | pud_t *pudp, pud_t pud) | |
490 | { | |
491 | if (sizeof(pudval_t) > sizeof(long)) | |
492 | /* 5 arg words */ | |
493 | pv_mmu_ops.set_pud_at(mm, addr, pudp, pud); | |
494 | else | |
495 | PVOP_VCALL4(pv_mmu_ops.set_pud_at, mm, addr, pudp, | |
496 | native_pud_val(pud)); | |
497 | } | |
498 | ||
60b3f626 JF |
499 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
500 | { | |
501 | pmdval_t val = native_pmd_val(pmd); | |
502 | ||
503 | if (sizeof(pmdval_t) > sizeof(long)) | |
504 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
505 | else | |
506 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
507 | } | |
508 | ||
98233368 | 509 | #if CONFIG_PGTABLE_LEVELS >= 3 |
1fe91514 GOC |
510 | static inline pmd_t __pmd(pmdval_t val) |
511 | { | |
512 | pmdval_t ret; | |
513 | ||
514 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
515 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd, |
516 | val, (u64)val >> 32); | |
1fe91514 | 517 | else |
da5de7c2 JF |
518 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd, |
519 | val); | |
1fe91514 GOC |
520 | |
521 | return (pmd_t) { ret }; | |
522 | } | |
523 | ||
524 | static inline pmdval_t pmd_val(pmd_t pmd) | |
525 | { | |
526 | pmdval_t ret; | |
527 | ||
528 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
529 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val, |
530 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1fe91514 | 531 | else |
da5de7c2 JF |
532 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val, |
533 | pmd.pmd); | |
1fe91514 GOC |
534 | |
535 | return ret; | |
536 | } | |
537 | ||
538 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
539 | { | |
540 | pudval_t val = native_pud_val(pud); | |
541 | ||
542 | if (sizeof(pudval_t) > sizeof(long)) | |
543 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
544 | val, (u64)val >> 32); | |
545 | else | |
546 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
547 | val); | |
548 | } | |
f2a6a705 | 549 | #if CONFIG_PGTABLE_LEVELS >= 4 |
9042219c EH |
550 | static inline pud_t __pud(pudval_t val) |
551 | { | |
552 | pudval_t ret; | |
553 | ||
554 | if (sizeof(pudval_t) > sizeof(long)) | |
da5de7c2 JF |
555 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud, |
556 | val, (u64)val >> 32); | |
9042219c | 557 | else |
da5de7c2 JF |
558 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud, |
559 | val); | |
9042219c EH |
560 | |
561 | return (pud_t) { ret }; | |
562 | } | |
563 | ||
564 | static inline pudval_t pud_val(pud_t pud) | |
565 | { | |
566 | pudval_t ret; | |
567 | ||
568 | if (sizeof(pudval_t) > sizeof(long)) | |
4767afbf JF |
569 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val, |
570 | pud.pud, (u64)pud.pud >> 32); | |
9042219c | 571 | else |
4767afbf JF |
572 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val, |
573 | pud.pud); | |
9042219c EH |
574 | |
575 | return ret; | |
576 | } | |
577 | ||
f2a6a705 KS |
578 | static inline void pud_clear(pud_t *pudp) |
579 | { | |
580 | set_pud(pudp, __pud(0)); | |
581 | } | |
582 | ||
583 | static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) | |
584 | { | |
585 | p4dval_t val = native_p4d_val(p4d); | |
586 | ||
587 | if (sizeof(p4dval_t) > sizeof(long)) | |
588 | PVOP_VCALL3(pv_mmu_ops.set_p4d, p4dp, | |
589 | val, (u64)val >> 32); | |
590 | else | |
591 | PVOP_VCALL2(pv_mmu_ops.set_p4d, p4dp, | |
592 | val); | |
593 | } | |
594 | ||
335437fb KS |
595 | #if CONFIG_PGTABLE_LEVELS >= 5 |
596 | ||
597 | static inline p4d_t __p4d(p4dval_t val) | |
f2a6a705 | 598 | { |
335437fb | 599 | p4dval_t ret = PVOP_CALLEE1(p4dval_t, pv_mmu_ops.make_p4d, val); |
f2a6a705 | 600 | |
335437fb KS |
601 | return (p4d_t) { ret }; |
602 | } | |
f2a6a705 | 603 | |
335437fb KS |
604 | static inline p4dval_t p4d_val(p4d_t p4d) |
605 | { | |
606 | return PVOP_CALLEE1(p4dval_t, pv_mmu_ops.p4d_val, p4d.p4d); | |
607 | } | |
f2a6a705 | 608 | |
9042219c EH |
609 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) |
610 | { | |
611 | pgdval_t val = native_pgd_val(pgd); | |
612 | ||
335437fb | 613 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, val); |
9042219c EH |
614 | } |
615 | ||
616 | static inline void pgd_clear(pgd_t *pgdp) | |
617 | { | |
618 | set_pgd(pgdp, __pgd(0)); | |
619 | } | |
620 | ||
f2a6a705 | 621 | #endif /* CONFIG_PGTABLE_LEVELS == 5 */ |
9042219c | 622 | |
335437fb KS |
623 | static inline void p4d_clear(p4d_t *p4dp) |
624 | { | |
625 | set_p4d(p4dp, __p4d(0)); | |
626 | } | |
627 | ||
98233368 | 628 | #endif /* CONFIG_PGTABLE_LEVELS == 4 */ |
9042219c | 629 | |
98233368 | 630 | #endif /* CONFIG_PGTABLE_LEVELS >= 3 */ |
1fe91514 | 631 | |
4eed80cd JF |
632 | #ifdef CONFIG_X86_PAE |
633 | /* Special-case pte-setting operations for PAE, which can't update a | |
634 | 64-bit pte atomically */ | |
635 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
636 | { | |
637 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
638 | pte.pte, pte.pte >> 32); | |
639 | } | |
640 | ||
4eed80cd JF |
641 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
642 | pte_t *ptep) | |
643 | { | |
644 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
645 | } | |
60b3f626 JF |
646 | |
647 | static inline void pmd_clear(pmd_t *pmdp) | |
648 | { | |
649 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
650 | } | |
4eed80cd JF |
651 | #else /* !CONFIG_X86_PAE */ |
652 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
653 | { | |
654 | set_pte(ptep, pte); | |
655 | } | |
656 | ||
4eed80cd JF |
657 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
658 | pte_t *ptep) | |
659 | { | |
660 | set_pte_at(mm, addr, ptep, __pte(0)); | |
661 | } | |
60b3f626 JF |
662 | |
663 | static inline void pmd_clear(pmd_t *pmdp) | |
664 | { | |
665 | set_pmd(pmdp, __pmd(0)); | |
666 | } | |
4eed80cd JF |
667 | #endif /* CONFIG_X86_PAE */ |
668 | ||
7fd7d83d | 669 | #define __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 670 | static inline void arch_start_context_switch(struct task_struct *prev) |
f8822f42 | 671 | { |
224101ed | 672 | PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev); |
f8822f42 JF |
673 | } |
674 | ||
224101ed | 675 | static inline void arch_end_context_switch(struct task_struct *next) |
f8822f42 | 676 | { |
224101ed | 677 | PVOP_VCALL1(pv_cpu_ops.end_context_switch, next); |
f8822f42 JF |
678 | } |
679 | ||
9226d125 | 680 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
f8822f42 JF |
681 | static inline void arch_enter_lazy_mmu_mode(void) |
682 | { | |
8965c1c0 | 683 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
684 | } |
685 | ||
686 | static inline void arch_leave_lazy_mmu_mode(void) | |
687 | { | |
8965c1c0 | 688 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
689 | } |
690 | ||
511ba86e BO |
691 | static inline void arch_flush_lazy_mmu_mode(void) |
692 | { | |
693 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush); | |
694 | } | |
9226d125 | 695 | |
aeaaa59c | 696 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
3b3809ac | 697 | phys_addr_t phys, pgprot_t flags) |
aeaaa59c JF |
698 | { |
699 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
700 | } | |
701 | ||
b4ecc126 | 702 | #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS) |
4bb689ee | 703 | |
f233f7f1 PZI |
704 | static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock, |
705 | u32 val) | |
706 | { | |
707 | PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val); | |
708 | } | |
709 | ||
710 | static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock) | |
711 | { | |
712 | PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock); | |
713 | } | |
714 | ||
715 | static __always_inline void pv_wait(u8 *ptr, u8 val) | |
716 | { | |
717 | PVOP_VCALL2(pv_lock_ops.wait, ptr, val); | |
718 | } | |
719 | ||
720 | static __always_inline void pv_kick(int cpu) | |
721 | { | |
722 | PVOP_VCALL1(pv_lock_ops.kick, cpu); | |
723 | } | |
724 | ||
6c62985d | 725 | static __always_inline bool pv_vcpu_is_preempted(long cpu) |
3cded417 PZ |
726 | { |
727 | return PVOP_CALLEE1(bool, pv_lock_ops.vcpu_is_preempted, cpu); | |
728 | } | |
729 | ||
f233f7f1 | 730 | #endif /* SMP && PARAVIRT_SPINLOCKS */ |
4bb689ee | 731 | |
2e47d3e6 | 732 | #ifdef CONFIG_X86_32 |
ecb93d1c JF |
733 | #define PV_SAVE_REGS "pushl %ecx; pushl %edx;" |
734 | #define PV_RESTORE_REGS "popl %edx; popl %ecx;" | |
735 | ||
736 | /* save and restore all caller-save registers, except return value */ | |
e584f559 JF |
737 | #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" |
738 | #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" | |
ecb93d1c | 739 | |
2e47d3e6 GOC |
740 | #define PV_FLAGS_ARG "0" |
741 | #define PV_EXTRA_CLOBBERS | |
742 | #define PV_VEXTRA_CLOBBERS | |
743 | #else | |
ecb93d1c JF |
744 | /* save and restore all caller-save registers, except return value */ |
745 | #define PV_SAVE_ALL_CALLER_REGS \ | |
746 | "push %rcx;" \ | |
747 | "push %rdx;" \ | |
748 | "push %rsi;" \ | |
749 | "push %rdi;" \ | |
750 | "push %r8;" \ | |
751 | "push %r9;" \ | |
752 | "push %r10;" \ | |
753 | "push %r11;" | |
754 | #define PV_RESTORE_ALL_CALLER_REGS \ | |
755 | "pop %r11;" \ | |
756 | "pop %r10;" \ | |
757 | "pop %r9;" \ | |
758 | "pop %r8;" \ | |
759 | "pop %rdi;" \ | |
760 | "pop %rsi;" \ | |
761 | "pop %rdx;" \ | |
762 | "pop %rcx;" | |
763 | ||
2e47d3e6 GOC |
764 | /* We save some registers, but all of them, that's too much. We clobber all |
765 | * caller saved registers but the argument parameter */ | |
766 | #define PV_SAVE_REGS "pushq %%rdi;" | |
767 | #define PV_RESTORE_REGS "popq %%rdi;" | |
c24481e9 JF |
768 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi" |
769 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi" | |
2e47d3e6 GOC |
770 | #define PV_FLAGS_ARG "D" |
771 | #endif | |
772 | ||
ecb93d1c JF |
773 | /* |
774 | * Generate a thunk around a function which saves all caller-save | |
775 | * registers except for the return value. This allows C functions to | |
776 | * be called from assembler code where fewer than normal registers are | |
777 | * available. It may also help code generation around calls from C | |
778 | * code if the common case doesn't use many registers. | |
779 | * | |
780 | * When a callee is wrapped in a thunk, the caller can assume that all | |
781 | * arg regs and all scratch registers are preserved across the | |
782 | * call. The return value in rax/eax will not be saved, even for void | |
783 | * functions. | |
784 | */ | |
87b240cb | 785 | #define PV_THUNK_NAME(func) "__raw_callee_save_" #func |
ecb93d1c JF |
786 | #define PV_CALLEE_SAVE_REGS_THUNK(func) \ |
787 | extern typeof(func) __raw_callee_save_##func; \ | |
ecb93d1c JF |
788 | \ |
789 | asm(".pushsection .text;" \ | |
87b240cb JP |
790 | ".globl " PV_THUNK_NAME(func) ";" \ |
791 | ".type " PV_THUNK_NAME(func) ", @function;" \ | |
792 | PV_THUNK_NAME(func) ":" \ | |
793 | FRAME_BEGIN \ | |
ecb93d1c JF |
794 | PV_SAVE_ALL_CALLER_REGS \ |
795 | "call " #func ";" \ | |
796 | PV_RESTORE_ALL_CALLER_REGS \ | |
87b240cb | 797 | FRAME_END \ |
ecb93d1c JF |
798 | "ret;" \ |
799 | ".popsection") | |
800 | ||
801 | /* Get a reference to a callee-save function */ | |
802 | #define PV_CALLEE_SAVE(func) \ | |
803 | ((struct paravirt_callee_save) { __raw_callee_save_##func }) | |
804 | ||
805 | /* Promise that "func" already uses the right calling convention */ | |
806 | #define __PV_IS_CALLEE_SAVE(func) \ | |
807 | ((struct paravirt_callee_save) { func }) | |
808 | ||
b5908548 | 809 | static inline notrace unsigned long arch_local_save_flags(void) |
139ec7c4 | 810 | { |
71999d98 | 811 | return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl); |
139ec7c4 RR |
812 | } |
813 | ||
b5908548 | 814 | static inline notrace void arch_local_irq_restore(unsigned long f) |
139ec7c4 | 815 | { |
71999d98 | 816 | PVOP_VCALLEE1(pv_irq_ops.restore_fl, f); |
139ec7c4 RR |
817 | } |
818 | ||
b5908548 | 819 | static inline notrace void arch_local_irq_disable(void) |
139ec7c4 | 820 | { |
71999d98 | 821 | PVOP_VCALLEE0(pv_irq_ops.irq_disable); |
139ec7c4 RR |
822 | } |
823 | ||
b5908548 | 824 | static inline notrace void arch_local_irq_enable(void) |
139ec7c4 | 825 | { |
71999d98 | 826 | PVOP_VCALLEE0(pv_irq_ops.irq_enable); |
139ec7c4 RR |
827 | } |
828 | ||
b5908548 | 829 | static inline notrace unsigned long arch_local_irq_save(void) |
139ec7c4 RR |
830 | { |
831 | unsigned long f; | |
832 | ||
df9ee292 DH |
833 | f = arch_local_save_flags(); |
834 | arch_local_irq_disable(); | |
139ec7c4 RR |
835 | return f; |
836 | } | |
837 | ||
74d4affd | 838 | |
294688c0 | 839 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 840 | #undef PARAVIRT_CALL |
1a45b7aa JF |
841 | #undef __PVOP_CALL |
842 | #undef __PVOP_VCALL | |
f8822f42 JF |
843 | #undef PVOP_VCALL0 |
844 | #undef PVOP_CALL0 | |
845 | #undef PVOP_VCALL1 | |
846 | #undef PVOP_CALL1 | |
847 | #undef PVOP_VCALL2 | |
848 | #undef PVOP_CALL2 | |
849 | #undef PVOP_VCALL3 | |
850 | #undef PVOP_CALL3 | |
851 | #undef PVOP_VCALL4 | |
852 | #undef PVOP_CALL4 | |
139ec7c4 | 853 | |
6f30c1ac TG |
854 | extern void default_banner(void); |
855 | ||
d3561b7f RR |
856 | #else /* __ASSEMBLY__ */ |
857 | ||
658be9d3 | 858 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
859 | 771:; \ |
860 | ops; \ | |
861 | 772:; \ | |
862 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
863 | .align algn; \ |
864 | word 771b; \ | |
139ec7c4 RR |
865 | .byte ptype; \ |
866 | .byte 772b-771b; \ | |
867 | .short clobbers; \ | |
868 | .popsection | |
869 | ||
658be9d3 | 870 | |
9104a18d | 871 | #define COND_PUSH(set, mask, reg) \ |
ecb93d1c | 872 | .if ((~(set)) & mask); push %reg; .endif |
9104a18d | 873 | #define COND_POP(set, mask, reg) \ |
ecb93d1c | 874 | .if ((~(set)) & mask); pop %reg; .endif |
9104a18d | 875 | |
658be9d3 | 876 | #ifdef CONFIG_X86_64 |
9104a18d JF |
877 | |
878 | #define PV_SAVE_REGS(set) \ | |
879 | COND_PUSH(set, CLBR_RAX, rax); \ | |
880 | COND_PUSH(set, CLBR_RCX, rcx); \ | |
881 | COND_PUSH(set, CLBR_RDX, rdx); \ | |
882 | COND_PUSH(set, CLBR_RSI, rsi); \ | |
883 | COND_PUSH(set, CLBR_RDI, rdi); \ | |
884 | COND_PUSH(set, CLBR_R8, r8); \ | |
885 | COND_PUSH(set, CLBR_R9, r9); \ | |
886 | COND_PUSH(set, CLBR_R10, r10); \ | |
887 | COND_PUSH(set, CLBR_R11, r11) | |
888 | #define PV_RESTORE_REGS(set) \ | |
889 | COND_POP(set, CLBR_R11, r11); \ | |
890 | COND_POP(set, CLBR_R10, r10); \ | |
891 | COND_POP(set, CLBR_R9, r9); \ | |
892 | COND_POP(set, CLBR_R8, r8); \ | |
893 | COND_POP(set, CLBR_RDI, rdi); \ | |
894 | COND_POP(set, CLBR_RSI, rsi); \ | |
895 | COND_POP(set, CLBR_RDX, rdx); \ | |
896 | COND_POP(set, CLBR_RCX, rcx); \ | |
897 | COND_POP(set, CLBR_RAX, rax) | |
898 | ||
6057fc82 | 899 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) |
658be9d3 | 900 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 901 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 902 | #else |
9104a18d JF |
903 | #define PV_SAVE_REGS(set) \ |
904 | COND_PUSH(set, CLBR_EAX, eax); \ | |
905 | COND_PUSH(set, CLBR_EDI, edi); \ | |
906 | COND_PUSH(set, CLBR_ECX, ecx); \ | |
907 | COND_PUSH(set, CLBR_EDX, edx) | |
908 | #define PV_RESTORE_REGS(set) \ | |
909 | COND_POP(set, CLBR_EDX, edx); \ | |
910 | COND_POP(set, CLBR_ECX, ecx); \ | |
911 | COND_POP(set, CLBR_EDI, edi); \ | |
912 | COND_POP(set, CLBR_EAX, eax) | |
913 | ||
6057fc82 | 914 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) |
658be9d3 | 915 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 916 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
917 | #endif |
918 | ||
93b1eab3 JF |
919 | #define INTERRUPT_RETURN \ |
920 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 921 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
922 | |
923 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 924 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
ecb93d1c | 925 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 926 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ |
ecb93d1c | 927 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 JF |
928 | |
929 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 930 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
ecb93d1c | 931 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 932 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ |
ecb93d1c | 933 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 | 934 | |
6057fc82 | 935 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
936 | #define GET_CR0_INTO_EAX \ |
937 | push %ecx; push %edx; \ | |
938 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 939 | pop %edx; pop %ecx |
2be29982 | 940 | #else /* !CONFIG_X86_32 */ |
a00394f8 JF |
941 | |
942 | /* | |
943 | * If swapgs is used while the userspace stack is still current, | |
944 | * there's no way to call a pvop. The PV replacement *must* be | |
945 | * inlined, or the swapgs instruction must be trapped and emulated. | |
946 | */ | |
947 | #define SWAPGS_UNSAFE_STACK \ | |
948 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
949 | swapgs) | |
950 | ||
9104a18d JF |
951 | /* |
952 | * Note: swapgs is very special, and in practise is either going to be | |
953 | * implemented with a single "swapgs" instruction or something very | |
954 | * special. Either way, we don't need to save any registers for | |
955 | * it. | |
956 | */ | |
e801f864 GOC |
957 | #define SWAPGS \ |
958 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
9104a18d | 959 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \ |
e801f864 GOC |
960 | ) |
961 | ||
ffc4bc9c PA |
962 | #define GET_CR2_INTO_RAX \ |
963 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2) | |
4a8c4c4e | 964 | |
fab58420 JF |
965 | #define PARAVIRT_ADJUST_EXCEPTION_FRAME \ |
966 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \ | |
967 | CLBR_NONE, \ | |
968 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame)) | |
969 | ||
2be29982 JF |
970 | #define USERGS_SYSRET64 \ |
971 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ | |
d75cd22f | 972 | CLBR_NONE, \ |
2be29982 | 973 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) |
2be29982 | 974 | #endif /* CONFIG_X86_32 */ |
139ec7c4 | 975 | |
d3561b7f | 976 | #endif /* __ASSEMBLY__ */ |
6f30c1ac TG |
977 | #else /* CONFIG_PARAVIRT */ |
978 | # define default_banner x86_init_noop | |
a1ea1c03 DH |
979 | #ifndef __ASSEMBLY__ |
980 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, | |
981 | struct mm_struct *mm) | |
982 | { | |
983 | } | |
984 | ||
985 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) | |
986 | { | |
987 | } | |
988 | #endif /* __ASSEMBLY__ */ | |
6f30c1ac | 989 | #endif /* !CONFIG_PARAVIRT */ |
1965aae3 | 990 | #endif /* _ASM_X86_PARAVIRT_H */ |