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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1965aae3 PA |
2 | #ifndef _ASM_X86_PARAVIRT_H |
3 | #define _ASM_X86_PARAVIRT_H | |
d3561b7f RR |
4 | /* Various instructions on x86 need to be replaced for |
5 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
6 | |
7 | #ifdef CONFIG_PARAVIRT | |
54321d94 | 8 | #include <asm/pgtable_types.h> |
658be9d3 | 9 | #include <asm/asm.h> |
d3561b7f | 10 | |
ac5672f8 | 11 | #include <asm/paravirt_types.h> |
ecb93d1c | 12 | |
d3561b7f | 13 | #ifndef __ASSEMBLY__ |
187f1882 | 14 | #include <linux/bug.h> |
3dc494e8 | 15 | #include <linux/types.h> |
d4c10477 | 16 | #include <linux/cpumask.h> |
87b240cb | 17 | #include <asm/frame.h> |
1a45b7aa | 18 | |
faca6227 | 19 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
20 | struct thread_struct *thread) |
21 | { | |
faca6227 | 22 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
23 | } |
24 | ||
d3561b7f RR |
25 | /* The paravirtualized CPUID instruction. */ |
26 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
27 | unsigned int *ecx, unsigned int *edx) | |
28 | { | |
93b1eab3 | 29 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
30 | } |
31 | ||
32 | /* | |
33 | * These special macros can be used to get or set a debugging register | |
34 | */ | |
f8822f42 JF |
35 | static inline unsigned long paravirt_get_debugreg(int reg) |
36 | { | |
93b1eab3 | 37 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
38 | } |
39 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
40 | static inline void set_debugreg(unsigned long val, int reg) | |
41 | { | |
93b1eab3 | 42 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 43 | } |
d3561b7f | 44 | |
f8822f42 JF |
45 | static inline unsigned long read_cr0(void) |
46 | { | |
93b1eab3 | 47 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 48 | } |
d3561b7f | 49 | |
f8822f42 JF |
50 | static inline void write_cr0(unsigned long x) |
51 | { | |
93b1eab3 | 52 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
53 | } |
54 | ||
55 | static inline unsigned long read_cr2(void) | |
56 | { | |
93b1eab3 | 57 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
58 | } |
59 | ||
60 | static inline void write_cr2(unsigned long x) | |
61 | { | |
93b1eab3 | 62 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
63 | } |
64 | ||
6c690ee1 | 65 | static inline unsigned long __read_cr3(void) |
f8822f42 | 66 | { |
93b1eab3 | 67 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 68 | } |
d3561b7f | 69 | |
f8822f42 JF |
70 | static inline void write_cr3(unsigned long x) |
71 | { | |
93b1eab3 | 72 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 73 | } |
d3561b7f | 74 | |
1e02ce4c | 75 | static inline void __write_cr4(unsigned long x) |
f8822f42 | 76 | { |
93b1eab3 | 77 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 78 | } |
3dc494e8 | 79 | |
94ea03cd | 80 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
81 | static inline unsigned long read_cr8(void) |
82 | { | |
83 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
84 | } | |
85 | ||
86 | static inline void write_cr8(unsigned long x) | |
87 | { | |
88 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
89 | } | |
94ea03cd | 90 | #endif |
4c9890c2 | 91 | |
df9ee292 | 92 | static inline void arch_safe_halt(void) |
d3561b7f | 93 | { |
93b1eab3 | 94 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
95 | } |
96 | ||
97 | static inline void halt(void) | |
98 | { | |
c8217b83 | 99 | PVOP_VCALL0(pv_irq_ops.halt); |
f8822f42 JF |
100 | } |
101 | ||
102 | static inline void wbinvd(void) | |
103 | { | |
93b1eab3 | 104 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 105 | } |
d3561b7f | 106 | |
93b1eab3 | 107 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 108 | |
dd2f4a00 AL |
109 | static inline u64 paravirt_read_msr(unsigned msr) |
110 | { | |
111 | return PVOP_CALL1(u64, pv_cpu_ops.read_msr, msr); | |
112 | } | |
113 | ||
114 | static inline void paravirt_write_msr(unsigned msr, | |
115 | unsigned low, unsigned high) | |
116 | { | |
e8ad8bc4 | 117 | PVOP_VCALL3(pv_cpu_ops.write_msr, msr, low, high); |
dd2f4a00 AL |
118 | } |
119 | ||
c2ee03b2 | 120 | static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) |
f8822f42 | 121 | { |
c2ee03b2 | 122 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr_safe, msr, err); |
f8822f42 | 123 | } |
132ec92f | 124 | |
c2ee03b2 AL |
125 | static inline int paravirt_write_msr_safe(unsigned msr, |
126 | unsigned low, unsigned high) | |
f8822f42 | 127 | { |
c2ee03b2 | 128 | return PVOP_CALL3(int, pv_cpu_ops.write_msr_safe, msr, low, high); |
f8822f42 JF |
129 | } |
130 | ||
49cd740b JP |
131 | #define rdmsr(msr, val1, val2) \ |
132 | do { \ | |
4985ce15 | 133 | u64 _l = paravirt_read_msr(msr); \ |
f8822f42 JF |
134 | val1 = (u32)_l; \ |
135 | val2 = _l >> 32; \ | |
49cd740b | 136 | } while (0) |
d3561b7f | 137 | |
49cd740b JP |
138 | #define wrmsr(msr, val1, val2) \ |
139 | do { \ | |
4985ce15 | 140 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 141 | } while (0) |
d3561b7f | 142 | |
49cd740b JP |
143 | #define rdmsrl(msr, val) \ |
144 | do { \ | |
4985ce15 | 145 | val = paravirt_read_msr(msr); \ |
49cd740b | 146 | } while (0) |
d3561b7f | 147 | |
47edb651 AL |
148 | static inline void wrmsrl(unsigned msr, u64 val) |
149 | { | |
150 | wrmsr(msr, (u32)val, (u32)(val>>32)); | |
151 | } | |
152 | ||
c2ee03b2 | 153 | #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b) |
d3561b7f RR |
154 | |
155 | /* rdmsr with exception handling */ | |
c2ee03b2 AL |
156 | #define rdmsr_safe(msr, a, b) \ |
157 | ({ \ | |
158 | int _err; \ | |
159 | u64 _l = paravirt_read_msr_safe(msr, &_err); \ | |
160 | (*a) = (u32)_l; \ | |
161 | (*b) = _l >> 32; \ | |
162 | _err; \ | |
49cd740b | 163 | }) |
d3561b7f | 164 | |
1de87bd4 AK |
165 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
166 | { | |
167 | int err; | |
168 | ||
c2ee03b2 | 169 | *p = paravirt_read_msr_safe(msr, &err); |
1de87bd4 AK |
170 | return err; |
171 | } | |
177fed1e | 172 | |
688340ea JF |
173 | static inline unsigned long long paravirt_sched_clock(void) |
174 | { | |
93b1eab3 | 175 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 176 | } |
6cb9a835 | 177 | |
c5905afb IM |
178 | struct static_key; |
179 | extern struct static_key paravirt_steal_enabled; | |
180 | extern struct static_key paravirt_steal_rq_enabled; | |
3c404b57 GC |
181 | |
182 | static inline u64 paravirt_steal_clock(int cpu) | |
183 | { | |
184 | return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu); | |
185 | } | |
186 | ||
f8822f42 JF |
187 | static inline unsigned long long paravirt_read_pmc(int counter) |
188 | { | |
93b1eab3 | 189 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 190 | } |
d3561b7f | 191 | |
49cd740b JP |
192 | #define rdpmc(counter, low, high) \ |
193 | do { \ | |
f8822f42 JF |
194 | u64 _l = paravirt_read_pmc(counter); \ |
195 | low = (u32)_l; \ | |
196 | high = _l >> 32; \ | |
49cd740b | 197 | } while (0) |
3dc494e8 | 198 | |
1ff4d58a AK |
199 | #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) |
200 | ||
38ffbe66 JF |
201 | static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
202 | { | |
203 | PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries); | |
204 | } | |
205 | ||
206 | static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) | |
207 | { | |
208 | PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries); | |
209 | } | |
210 | ||
f8822f42 JF |
211 | static inline void load_TR_desc(void) |
212 | { | |
93b1eab3 | 213 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 214 | } |
6b68f01b | 215 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 216 | { |
93b1eab3 | 217 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 218 | } |
6b68f01b | 219 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 220 | { |
93b1eab3 | 221 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
222 | } |
223 | static inline void set_ldt(const void *addr, unsigned entries) | |
224 | { | |
93b1eab3 | 225 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 226 | } |
f8822f42 JF |
227 | static inline unsigned long paravirt_store_tr(void) |
228 | { | |
93b1eab3 | 229 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
230 | } |
231 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
232 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
233 | { | |
93b1eab3 | 234 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 235 | } |
75b8bb3e | 236 | |
9f9d489a JF |
237 | #ifdef CONFIG_X86_64 |
238 | static inline void load_gs_index(unsigned int gs) | |
239 | { | |
240 | PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs); | |
241 | } | |
242 | #endif | |
243 | ||
75b8bb3e GOC |
244 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, |
245 | const void *desc) | |
f8822f42 | 246 | { |
75b8bb3e | 247 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 248 | } |
014b15be GOC |
249 | |
250 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
251 | void *desc, int type) | |
f8822f42 | 252 | { |
014b15be | 253 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 254 | } |
014b15be | 255 | |
8d947344 | 256 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 257 | { |
8d947344 | 258 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
259 | } |
260 | static inline void set_iopl_mask(unsigned mask) | |
261 | { | |
93b1eab3 | 262 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 263 | } |
3dc494e8 | 264 | |
d3561b7f | 265 | /* The paravirtualized I/O functions */ |
49cd740b JP |
266 | static inline void slow_down_io(void) |
267 | { | |
93b1eab3 | 268 | pv_cpu_ops.io_delay(); |
d3561b7f | 269 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
270 | pv_cpu_ops.io_delay(); |
271 | pv_cpu_ops.io_delay(); | |
272 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
273 | #endif |
274 | } | |
275 | ||
d6dd61c8 JF |
276 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
277 | struct mm_struct *next) | |
278 | { | |
93b1eab3 | 279 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
280 | } |
281 | ||
a1ea1c03 DH |
282 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, |
283 | struct mm_struct *mm) | |
d6dd61c8 | 284 | { |
93b1eab3 | 285 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
286 | } |
287 | ||
a1ea1c03 | 288 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) |
d6dd61c8 | 289 | { |
93b1eab3 | 290 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
291 | } |
292 | ||
f8822f42 JF |
293 | static inline void __flush_tlb(void) |
294 | { | |
93b1eab3 | 295 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
296 | } |
297 | static inline void __flush_tlb_global(void) | |
298 | { | |
93b1eab3 | 299 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
300 | } |
301 | static inline void __flush_tlb_single(unsigned long addr) | |
302 | { | |
93b1eab3 | 303 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 304 | } |
da181a8b | 305 | |
4595f962 | 306 | static inline void flush_tlb_others(const struct cpumask *cpumask, |
a2055abe | 307 | const struct flush_tlb_info *info) |
d4c10477 | 308 | { |
a2055abe | 309 | PVOP_VCALL2(pv_mmu_ops.flush_tlb_others, cpumask, info); |
d4c10477 JF |
310 | } |
311 | ||
eba0045f JF |
312 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
313 | { | |
314 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
315 | } | |
316 | ||
317 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
318 | { | |
319 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
320 | } | |
321 | ||
f8639939 | 322 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 323 | { |
6944a9c8 | 324 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 325 | } |
f8639939 | 326 | static inline void paravirt_release_pte(unsigned long pfn) |
f8822f42 | 327 | { |
6944a9c8 | 328 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 329 | } |
c119ecce | 330 | |
f8639939 | 331 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 332 | { |
6944a9c8 | 333 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 334 | } |
c119ecce | 335 | |
f8639939 | 336 | static inline void paravirt_release_pmd(unsigned long pfn) |
da181a8b | 337 | { |
6944a9c8 | 338 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
339 | } |
340 | ||
f8639939 | 341 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn) |
2761fa09 JF |
342 | { |
343 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
344 | } | |
f8639939 | 345 | static inline void paravirt_release_pud(unsigned long pfn) |
2761fa09 JF |
346 | { |
347 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
348 | } | |
349 | ||
335437fb KS |
350 | static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn) |
351 | { | |
352 | PVOP_VCALL2(pv_mmu_ops.alloc_p4d, mm, pfn); | |
353 | } | |
354 | ||
355 | static inline void paravirt_release_p4d(unsigned long pfn) | |
356 | { | |
357 | PVOP_VCALL1(pv_mmu_ops.release_p4d, pfn); | |
358 | } | |
359 | ||
773221f4 | 360 | static inline pte_t __pte(pteval_t val) |
da181a8b | 361 | { |
773221f4 JF |
362 | pteval_t ret; |
363 | ||
364 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
365 | ret = PVOP_CALLEE2(pteval_t, |
366 | pv_mmu_ops.make_pte, | |
367 | val, (u64)val >> 32); | |
773221f4 | 368 | else |
da5de7c2 JF |
369 | ret = PVOP_CALLEE1(pteval_t, |
370 | pv_mmu_ops.make_pte, | |
371 | val); | |
773221f4 | 372 | |
c8e5393a | 373 | return (pte_t) { .pte = ret }; |
da181a8b RR |
374 | } |
375 | ||
773221f4 JF |
376 | static inline pteval_t pte_val(pte_t pte) |
377 | { | |
378 | pteval_t ret; | |
379 | ||
380 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
381 | ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val, |
382 | pte.pte, (u64)pte.pte >> 32); | |
773221f4 | 383 | else |
da5de7c2 JF |
384 | ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val, |
385 | pte.pte); | |
773221f4 JF |
386 | |
387 | return ret; | |
388 | } | |
389 | ||
ef38503e | 390 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 391 | { |
ef38503e JF |
392 | pgdval_t ret; |
393 | ||
394 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
395 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd, |
396 | val, (u64)val >> 32); | |
ef38503e | 397 | else |
da5de7c2 JF |
398 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd, |
399 | val); | |
ef38503e JF |
400 | |
401 | return (pgd_t) { ret }; | |
402 | } | |
403 | ||
404 | static inline pgdval_t pgd_val(pgd_t pgd) | |
405 | { | |
406 | pgdval_t ret; | |
407 | ||
408 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
409 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val, |
410 | pgd.pgd, (u64)pgd.pgd >> 32); | |
ef38503e | 411 | else |
da5de7c2 JF |
412 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val, |
413 | pgd.pgd); | |
ef38503e JF |
414 | |
415 | return ret; | |
f8822f42 JF |
416 | } |
417 | ||
08b882c6 JF |
418 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
419 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
420 | pte_t *ptep) | |
421 | { | |
422 | pteval_t ret; | |
423 | ||
424 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
425 | mm, addr, ptep); | |
426 | ||
427 | return (pte_t) { .pte = ret }; | |
428 | } | |
429 | ||
430 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
431 | pte_t *ptep, pte_t pte) | |
432 | { | |
433 | if (sizeof(pteval_t) > sizeof(long)) | |
434 | /* 5 arg words */ | |
435 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
436 | else | |
437 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
438 | mm, addr, ptep, pte.pte); | |
439 | } | |
440 | ||
4eed80cd JF |
441 | static inline void set_pte(pte_t *ptep, pte_t pte) |
442 | { | |
443 | if (sizeof(pteval_t) > sizeof(long)) | |
444 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
445 | pte.pte, (u64)pte.pte >> 32); | |
446 | else | |
447 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
448 | pte.pte); | |
449 | } | |
450 | ||
451 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
452 | pte_t *ptep, pte_t pte) | |
453 | { | |
454 | if (sizeof(pteval_t) > sizeof(long)) | |
455 | /* 5 arg words */ | |
456 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
457 | else | |
458 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
459 | } | |
460 | ||
60b3f626 JF |
461 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
462 | { | |
463 | pmdval_t val = native_pmd_val(pmd); | |
464 | ||
465 | if (sizeof(pmdval_t) > sizeof(long)) | |
466 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
467 | else | |
468 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
469 | } | |
470 | ||
98233368 | 471 | #if CONFIG_PGTABLE_LEVELS >= 3 |
1fe91514 GOC |
472 | static inline pmd_t __pmd(pmdval_t val) |
473 | { | |
474 | pmdval_t ret; | |
475 | ||
476 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
477 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd, |
478 | val, (u64)val >> 32); | |
1fe91514 | 479 | else |
da5de7c2 JF |
480 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd, |
481 | val); | |
1fe91514 GOC |
482 | |
483 | return (pmd_t) { ret }; | |
484 | } | |
485 | ||
486 | static inline pmdval_t pmd_val(pmd_t pmd) | |
487 | { | |
488 | pmdval_t ret; | |
489 | ||
490 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
491 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val, |
492 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1fe91514 | 493 | else |
da5de7c2 JF |
494 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val, |
495 | pmd.pmd); | |
1fe91514 GOC |
496 | |
497 | return ret; | |
498 | } | |
499 | ||
500 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
501 | { | |
502 | pudval_t val = native_pud_val(pud); | |
503 | ||
504 | if (sizeof(pudval_t) > sizeof(long)) | |
505 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
506 | val, (u64)val >> 32); | |
507 | else | |
508 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
509 | val); | |
510 | } | |
f2a6a705 | 511 | #if CONFIG_PGTABLE_LEVELS >= 4 |
9042219c EH |
512 | static inline pud_t __pud(pudval_t val) |
513 | { | |
514 | pudval_t ret; | |
515 | ||
516 | if (sizeof(pudval_t) > sizeof(long)) | |
da5de7c2 JF |
517 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud, |
518 | val, (u64)val >> 32); | |
9042219c | 519 | else |
da5de7c2 JF |
520 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud, |
521 | val); | |
9042219c EH |
522 | |
523 | return (pud_t) { ret }; | |
524 | } | |
525 | ||
526 | static inline pudval_t pud_val(pud_t pud) | |
527 | { | |
528 | pudval_t ret; | |
529 | ||
530 | if (sizeof(pudval_t) > sizeof(long)) | |
4767afbf JF |
531 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val, |
532 | pud.pud, (u64)pud.pud >> 32); | |
9042219c | 533 | else |
4767afbf JF |
534 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val, |
535 | pud.pud); | |
9042219c EH |
536 | |
537 | return ret; | |
538 | } | |
539 | ||
f2a6a705 KS |
540 | static inline void pud_clear(pud_t *pudp) |
541 | { | |
542 | set_pud(pudp, __pud(0)); | |
543 | } | |
544 | ||
545 | static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) | |
546 | { | |
547 | p4dval_t val = native_p4d_val(p4d); | |
548 | ||
549 | if (sizeof(p4dval_t) > sizeof(long)) | |
550 | PVOP_VCALL3(pv_mmu_ops.set_p4d, p4dp, | |
551 | val, (u64)val >> 32); | |
552 | else | |
553 | PVOP_VCALL2(pv_mmu_ops.set_p4d, p4dp, | |
554 | val); | |
555 | } | |
556 | ||
335437fb KS |
557 | #if CONFIG_PGTABLE_LEVELS >= 5 |
558 | ||
559 | static inline p4d_t __p4d(p4dval_t val) | |
f2a6a705 | 560 | { |
335437fb | 561 | p4dval_t ret = PVOP_CALLEE1(p4dval_t, pv_mmu_ops.make_p4d, val); |
f2a6a705 | 562 | |
335437fb KS |
563 | return (p4d_t) { ret }; |
564 | } | |
f2a6a705 | 565 | |
335437fb KS |
566 | static inline p4dval_t p4d_val(p4d_t p4d) |
567 | { | |
568 | return PVOP_CALLEE1(p4dval_t, pv_mmu_ops.p4d_val, p4d.p4d); | |
569 | } | |
f2a6a705 | 570 | |
9042219c EH |
571 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) |
572 | { | |
573 | pgdval_t val = native_pgd_val(pgd); | |
574 | ||
335437fb | 575 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, val); |
9042219c EH |
576 | } |
577 | ||
578 | static inline void pgd_clear(pgd_t *pgdp) | |
579 | { | |
580 | set_pgd(pgdp, __pgd(0)); | |
581 | } | |
582 | ||
f2a6a705 | 583 | #endif /* CONFIG_PGTABLE_LEVELS == 5 */ |
9042219c | 584 | |
335437fb KS |
585 | static inline void p4d_clear(p4d_t *p4dp) |
586 | { | |
587 | set_p4d(p4dp, __p4d(0)); | |
588 | } | |
589 | ||
98233368 | 590 | #endif /* CONFIG_PGTABLE_LEVELS == 4 */ |
9042219c | 591 | |
98233368 | 592 | #endif /* CONFIG_PGTABLE_LEVELS >= 3 */ |
1fe91514 | 593 | |
4eed80cd JF |
594 | #ifdef CONFIG_X86_PAE |
595 | /* Special-case pte-setting operations for PAE, which can't update a | |
596 | 64-bit pte atomically */ | |
597 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
598 | { | |
599 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
600 | pte.pte, pte.pte >> 32); | |
601 | } | |
602 | ||
4eed80cd JF |
603 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
604 | pte_t *ptep) | |
605 | { | |
606 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
607 | } | |
60b3f626 JF |
608 | |
609 | static inline void pmd_clear(pmd_t *pmdp) | |
610 | { | |
611 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
612 | } | |
4eed80cd JF |
613 | #else /* !CONFIG_X86_PAE */ |
614 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
615 | { | |
616 | set_pte(ptep, pte); | |
617 | } | |
618 | ||
4eed80cd JF |
619 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
620 | pte_t *ptep) | |
621 | { | |
622 | set_pte_at(mm, addr, ptep, __pte(0)); | |
623 | } | |
60b3f626 JF |
624 | |
625 | static inline void pmd_clear(pmd_t *pmdp) | |
626 | { | |
627 | set_pmd(pmdp, __pmd(0)); | |
628 | } | |
4eed80cd JF |
629 | #endif /* CONFIG_X86_PAE */ |
630 | ||
7fd7d83d | 631 | #define __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 632 | static inline void arch_start_context_switch(struct task_struct *prev) |
f8822f42 | 633 | { |
224101ed | 634 | PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev); |
f8822f42 JF |
635 | } |
636 | ||
224101ed | 637 | static inline void arch_end_context_switch(struct task_struct *next) |
f8822f42 | 638 | { |
224101ed | 639 | PVOP_VCALL1(pv_cpu_ops.end_context_switch, next); |
f8822f42 JF |
640 | } |
641 | ||
9226d125 | 642 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
f8822f42 JF |
643 | static inline void arch_enter_lazy_mmu_mode(void) |
644 | { | |
8965c1c0 | 645 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
646 | } |
647 | ||
648 | static inline void arch_leave_lazy_mmu_mode(void) | |
649 | { | |
8965c1c0 | 650 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
651 | } |
652 | ||
511ba86e BO |
653 | static inline void arch_flush_lazy_mmu_mode(void) |
654 | { | |
655 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush); | |
656 | } | |
9226d125 | 657 | |
aeaaa59c | 658 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
3b3809ac | 659 | phys_addr_t phys, pgprot_t flags) |
aeaaa59c JF |
660 | { |
661 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
662 | } | |
663 | ||
b4ecc126 | 664 | #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS) |
4bb689ee | 665 | |
f233f7f1 PZI |
666 | static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock, |
667 | u32 val) | |
668 | { | |
669 | PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val); | |
670 | } | |
671 | ||
672 | static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock) | |
673 | { | |
674 | PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock); | |
675 | } | |
676 | ||
677 | static __always_inline void pv_wait(u8 *ptr, u8 val) | |
678 | { | |
679 | PVOP_VCALL2(pv_lock_ops.wait, ptr, val); | |
680 | } | |
681 | ||
682 | static __always_inline void pv_kick(int cpu) | |
683 | { | |
684 | PVOP_VCALL1(pv_lock_ops.kick, cpu); | |
685 | } | |
686 | ||
6c62985d | 687 | static __always_inline bool pv_vcpu_is_preempted(long cpu) |
3cded417 PZ |
688 | { |
689 | return PVOP_CALLEE1(bool, pv_lock_ops.vcpu_is_preempted, cpu); | |
690 | } | |
691 | ||
f233f7f1 | 692 | #endif /* SMP && PARAVIRT_SPINLOCKS */ |
4bb689ee | 693 | |
2e47d3e6 | 694 | #ifdef CONFIG_X86_32 |
ecb93d1c JF |
695 | #define PV_SAVE_REGS "pushl %ecx; pushl %edx;" |
696 | #define PV_RESTORE_REGS "popl %edx; popl %ecx;" | |
697 | ||
698 | /* save and restore all caller-save registers, except return value */ | |
e584f559 JF |
699 | #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" |
700 | #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" | |
ecb93d1c | 701 | |
2e47d3e6 GOC |
702 | #define PV_FLAGS_ARG "0" |
703 | #define PV_EXTRA_CLOBBERS | |
704 | #define PV_VEXTRA_CLOBBERS | |
705 | #else | |
ecb93d1c JF |
706 | /* save and restore all caller-save registers, except return value */ |
707 | #define PV_SAVE_ALL_CALLER_REGS \ | |
708 | "push %rcx;" \ | |
709 | "push %rdx;" \ | |
710 | "push %rsi;" \ | |
711 | "push %rdi;" \ | |
712 | "push %r8;" \ | |
713 | "push %r9;" \ | |
714 | "push %r10;" \ | |
715 | "push %r11;" | |
716 | #define PV_RESTORE_ALL_CALLER_REGS \ | |
717 | "pop %r11;" \ | |
718 | "pop %r10;" \ | |
719 | "pop %r9;" \ | |
720 | "pop %r8;" \ | |
721 | "pop %rdi;" \ | |
722 | "pop %rsi;" \ | |
723 | "pop %rdx;" \ | |
724 | "pop %rcx;" | |
725 | ||
2e47d3e6 GOC |
726 | /* We save some registers, but all of them, that's too much. We clobber all |
727 | * caller saved registers but the argument parameter */ | |
728 | #define PV_SAVE_REGS "pushq %%rdi;" | |
729 | #define PV_RESTORE_REGS "popq %%rdi;" | |
c24481e9 JF |
730 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi" |
731 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi" | |
2e47d3e6 GOC |
732 | #define PV_FLAGS_ARG "D" |
733 | #endif | |
734 | ||
ecb93d1c JF |
735 | /* |
736 | * Generate a thunk around a function which saves all caller-save | |
737 | * registers except for the return value. This allows C functions to | |
738 | * be called from assembler code where fewer than normal registers are | |
739 | * available. It may also help code generation around calls from C | |
740 | * code if the common case doesn't use many registers. | |
741 | * | |
742 | * When a callee is wrapped in a thunk, the caller can assume that all | |
743 | * arg regs and all scratch registers are preserved across the | |
744 | * call. The return value in rax/eax will not be saved, even for void | |
745 | * functions. | |
746 | */ | |
87b240cb | 747 | #define PV_THUNK_NAME(func) "__raw_callee_save_" #func |
ecb93d1c JF |
748 | #define PV_CALLEE_SAVE_REGS_THUNK(func) \ |
749 | extern typeof(func) __raw_callee_save_##func; \ | |
ecb93d1c JF |
750 | \ |
751 | asm(".pushsection .text;" \ | |
87b240cb JP |
752 | ".globl " PV_THUNK_NAME(func) ";" \ |
753 | ".type " PV_THUNK_NAME(func) ", @function;" \ | |
754 | PV_THUNK_NAME(func) ":" \ | |
755 | FRAME_BEGIN \ | |
ecb93d1c JF |
756 | PV_SAVE_ALL_CALLER_REGS \ |
757 | "call " #func ";" \ | |
758 | PV_RESTORE_ALL_CALLER_REGS \ | |
87b240cb | 759 | FRAME_END \ |
ecb93d1c JF |
760 | "ret;" \ |
761 | ".popsection") | |
762 | ||
763 | /* Get a reference to a callee-save function */ | |
764 | #define PV_CALLEE_SAVE(func) \ | |
765 | ((struct paravirt_callee_save) { __raw_callee_save_##func }) | |
766 | ||
767 | /* Promise that "func" already uses the right calling convention */ | |
768 | #define __PV_IS_CALLEE_SAVE(func) \ | |
769 | ((struct paravirt_callee_save) { func }) | |
770 | ||
b5908548 | 771 | static inline notrace unsigned long arch_local_save_flags(void) |
139ec7c4 | 772 | { |
71999d98 | 773 | return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl); |
139ec7c4 RR |
774 | } |
775 | ||
b5908548 | 776 | static inline notrace void arch_local_irq_restore(unsigned long f) |
139ec7c4 | 777 | { |
71999d98 | 778 | PVOP_VCALLEE1(pv_irq_ops.restore_fl, f); |
139ec7c4 RR |
779 | } |
780 | ||
b5908548 | 781 | static inline notrace void arch_local_irq_disable(void) |
139ec7c4 | 782 | { |
71999d98 | 783 | PVOP_VCALLEE0(pv_irq_ops.irq_disable); |
139ec7c4 RR |
784 | } |
785 | ||
b5908548 | 786 | static inline notrace void arch_local_irq_enable(void) |
139ec7c4 | 787 | { |
71999d98 | 788 | PVOP_VCALLEE0(pv_irq_ops.irq_enable); |
139ec7c4 RR |
789 | } |
790 | ||
b5908548 | 791 | static inline notrace unsigned long arch_local_irq_save(void) |
139ec7c4 RR |
792 | { |
793 | unsigned long f; | |
794 | ||
df9ee292 DH |
795 | f = arch_local_save_flags(); |
796 | arch_local_irq_disable(); | |
139ec7c4 RR |
797 | return f; |
798 | } | |
799 | ||
74d4affd | 800 | |
294688c0 | 801 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 802 | #undef PARAVIRT_CALL |
1a45b7aa JF |
803 | #undef __PVOP_CALL |
804 | #undef __PVOP_VCALL | |
f8822f42 JF |
805 | #undef PVOP_VCALL0 |
806 | #undef PVOP_CALL0 | |
807 | #undef PVOP_VCALL1 | |
808 | #undef PVOP_CALL1 | |
809 | #undef PVOP_VCALL2 | |
810 | #undef PVOP_CALL2 | |
811 | #undef PVOP_VCALL3 | |
812 | #undef PVOP_CALL3 | |
813 | #undef PVOP_VCALL4 | |
814 | #undef PVOP_CALL4 | |
139ec7c4 | 815 | |
6f30c1ac TG |
816 | extern void default_banner(void); |
817 | ||
d3561b7f RR |
818 | #else /* __ASSEMBLY__ */ |
819 | ||
658be9d3 | 820 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
821 | 771:; \ |
822 | ops; \ | |
823 | 772:; \ | |
824 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
825 | .align algn; \ |
826 | word 771b; \ | |
139ec7c4 RR |
827 | .byte ptype; \ |
828 | .byte 772b-771b; \ | |
829 | .short clobbers; \ | |
830 | .popsection | |
831 | ||
658be9d3 | 832 | |
9104a18d | 833 | #define COND_PUSH(set, mask, reg) \ |
ecb93d1c | 834 | .if ((~(set)) & mask); push %reg; .endif |
9104a18d | 835 | #define COND_POP(set, mask, reg) \ |
ecb93d1c | 836 | .if ((~(set)) & mask); pop %reg; .endif |
9104a18d | 837 | |
658be9d3 | 838 | #ifdef CONFIG_X86_64 |
9104a18d JF |
839 | |
840 | #define PV_SAVE_REGS(set) \ | |
841 | COND_PUSH(set, CLBR_RAX, rax); \ | |
842 | COND_PUSH(set, CLBR_RCX, rcx); \ | |
843 | COND_PUSH(set, CLBR_RDX, rdx); \ | |
844 | COND_PUSH(set, CLBR_RSI, rsi); \ | |
845 | COND_PUSH(set, CLBR_RDI, rdi); \ | |
846 | COND_PUSH(set, CLBR_R8, r8); \ | |
847 | COND_PUSH(set, CLBR_R9, r9); \ | |
848 | COND_PUSH(set, CLBR_R10, r10); \ | |
849 | COND_PUSH(set, CLBR_R11, r11) | |
850 | #define PV_RESTORE_REGS(set) \ | |
851 | COND_POP(set, CLBR_R11, r11); \ | |
852 | COND_POP(set, CLBR_R10, r10); \ | |
853 | COND_POP(set, CLBR_R9, r9); \ | |
854 | COND_POP(set, CLBR_R8, r8); \ | |
855 | COND_POP(set, CLBR_RDI, rdi); \ | |
856 | COND_POP(set, CLBR_RSI, rsi); \ | |
857 | COND_POP(set, CLBR_RDX, rdx); \ | |
858 | COND_POP(set, CLBR_RCX, rcx); \ | |
859 | COND_POP(set, CLBR_RAX, rax) | |
860 | ||
6057fc82 | 861 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) |
658be9d3 | 862 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 863 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 864 | #else |
9104a18d JF |
865 | #define PV_SAVE_REGS(set) \ |
866 | COND_PUSH(set, CLBR_EAX, eax); \ | |
867 | COND_PUSH(set, CLBR_EDI, edi); \ | |
868 | COND_PUSH(set, CLBR_ECX, ecx); \ | |
869 | COND_PUSH(set, CLBR_EDX, edx) | |
870 | #define PV_RESTORE_REGS(set) \ | |
871 | COND_POP(set, CLBR_EDX, edx); \ | |
872 | COND_POP(set, CLBR_ECX, ecx); \ | |
873 | COND_POP(set, CLBR_EDI, edi); \ | |
874 | COND_POP(set, CLBR_EAX, eax) | |
875 | ||
6057fc82 | 876 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) |
658be9d3 | 877 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 878 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
879 | #endif |
880 | ||
93b1eab3 JF |
881 | #define INTERRUPT_RETURN \ |
882 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 883 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
884 | |
885 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 886 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
ecb93d1c | 887 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 888 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ |
ecb93d1c | 889 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 JF |
890 | |
891 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 892 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
ecb93d1c | 893 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 894 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ |
ecb93d1c | 895 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 | 896 | |
6057fc82 | 897 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
898 | #define GET_CR0_INTO_EAX \ |
899 | push %ecx; push %edx; \ | |
900 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 901 | pop %edx; pop %ecx |
2be29982 | 902 | #else /* !CONFIG_X86_32 */ |
a00394f8 JF |
903 | |
904 | /* | |
905 | * If swapgs is used while the userspace stack is still current, | |
906 | * there's no way to call a pvop. The PV replacement *must* be | |
907 | * inlined, or the swapgs instruction must be trapped and emulated. | |
908 | */ | |
909 | #define SWAPGS_UNSAFE_STACK \ | |
910 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
911 | swapgs) | |
912 | ||
9104a18d JF |
913 | /* |
914 | * Note: swapgs is very special, and in practise is either going to be | |
915 | * implemented with a single "swapgs" instruction or something very | |
916 | * special. Either way, we don't need to save any registers for | |
917 | * it. | |
918 | */ | |
e801f864 GOC |
919 | #define SWAPGS \ |
920 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
9104a18d | 921 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \ |
e801f864 GOC |
922 | ) |
923 | ||
ffc4bc9c PA |
924 | #define GET_CR2_INTO_RAX \ |
925 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2) | |
4a8c4c4e | 926 | |
2be29982 JF |
927 | #define USERGS_SYSRET64 \ |
928 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ | |
d75cd22f | 929 | CLBR_NONE, \ |
2be29982 | 930 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) |
2be29982 | 931 | #endif /* CONFIG_X86_32 */ |
139ec7c4 | 932 | |
d3561b7f | 933 | #endif /* __ASSEMBLY__ */ |
6f30c1ac TG |
934 | #else /* CONFIG_PARAVIRT */ |
935 | # define default_banner x86_init_noop | |
a1ea1c03 DH |
936 | #ifndef __ASSEMBLY__ |
937 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, | |
938 | struct mm_struct *mm) | |
939 | { | |
940 | } | |
941 | ||
942 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) | |
943 | { | |
944 | } | |
945 | #endif /* __ASSEMBLY__ */ | |
6f30c1ac | 946 | #endif /* !CONFIG_PARAVIRT */ |
1965aae3 | 947 | #endif /* _ASM_X86_PARAVIRT_H */ |