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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Low-Level PCI Access for i386 machines. | |
3 | * | |
4 | * (c) 1999 Martin Mares <mj@ucw.cz> | |
5 | */ | |
6 | ||
5520b7e7 IM |
7 | #include <linux/ioport.h> |
8 | ||
1da177e4 LT |
9 | #undef DEBUG |
10 | ||
11 | #ifdef DEBUG | |
c767a54b | 12 | #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__) |
1da177e4 | 13 | #else |
c767a54b JP |
14 | #define DBG(fmt, ...) \ |
15 | do { \ | |
16 | if (0) \ | |
17 | printk(fmt, ##__VA_ARGS__); \ | |
18 | } while (0) | |
1da177e4 LT |
19 | #endif |
20 | ||
21 | #define PCI_PROBE_BIOS 0x0001 | |
22 | #define PCI_PROBE_CONF1 0x0002 | |
23 | #define PCI_PROBE_CONF2 0x0004 | |
24 | #define PCI_PROBE_MMCONF 0x0008 | |
79e453d4 | 25 | #define PCI_PROBE_MASK 0x000f |
0637a70a | 26 | #define PCI_PROBE_NOEARLY 0x0010 |
1da177e4 | 27 | |
1da177e4 LT |
28 | #define PCI_NO_CHECKS 0x0400 |
29 | #define PCI_USE_PIRQ_MASK 0x0800 | |
30 | #define PCI_ASSIGN_ROMS 0x1000 | |
31 | #define PCI_BIOS_IRQ_SCAN 0x2000 | |
32 | #define PCI_ASSIGN_ALL_BUSSES 0x4000 | |
036fff4c | 33 | #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 |
236e946b | 34 | #define PCI_USE__CRS 0x10000 |
5f0b2976 | 35 | #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 |
3a27dd1c | 36 | #define PCI_HAS_IO_ECS 0x40000 |
dc7c65db | 37 | #define PCI_NOASSIGN_ROMS 0x80000 |
7bc5e3f2 | 38 | #define PCI_ROOT_NO_CRS 0x100000 |
7bd1c365 | 39 | #define PCI_NOASSIGN_BARS 0x200000 |
1da177e4 LT |
40 | |
41 | extern unsigned int pci_probe; | |
120bb424 | 42 | extern unsigned long pirq_table_addr; |
1da177e4 | 43 | |
6b4b78fe MD |
44 | enum pci_bf_sort_state { |
45 | pci_bf_sort_default, | |
46 | pci_force_nobf, | |
47 | pci_force_bf, | |
48 | pci_dmi_bf, | |
49 | }; | |
50 | ||
1da177e4 LT |
51 | /* pci-i386.c */ |
52 | ||
1da177e4 | 53 | void pcibios_resource_survey(void); |
44de3395 | 54 | void pcibios_set_cache_line_size(void); |
1da177e4 LT |
55 | |
56 | /* pci-pc.c */ | |
57 | ||
58 | extern int pcibios_last_bus; | |
1da177e4 LT |
59 | extern struct pci_ops pci_root_ops; |
60 | ||
5707b24a AR |
61 | void pcibios_scan_specific_bus(int busn); |
62 | ||
1da177e4 LT |
63 | /* pci-irq.c */ |
64 | ||
65 | struct irq_info { | |
66 | u8 bus, devfn; /* Bus, device and function */ | |
67 | struct { | |
82487711 JSR |
68 | u8 link; /* IRQ line ID, chipset dependent, |
69 | 0 = not routed */ | |
1da177e4 LT |
70 | u16 bitmap; /* Available IRQs */ |
71 | } __attribute__((packed)) irq[4]; | |
72 | u8 slot; /* Slot number, 0=onboard */ | |
73 | u8 rfu; | |
74 | } __attribute__((packed)); | |
75 | ||
76 | struct irq_routing_table { | |
77 | u32 signature; /* PIRQ_SIGNATURE should be here */ | |
78 | u16 version; /* PIRQ_VERSION */ | |
79 | u16 size; /* Table size in bytes */ | |
80 | u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ | |
82487711 JSR |
81 | u16 exclusive_irqs; /* IRQs devoted exclusively to |
82 | PCI usage */ | |
83 | u16 rtr_vendor, rtr_device; /* Vendor and device ID of | |
84 | interrupt router */ | |
1da177e4 LT |
85 | u32 miniport_data; /* Crap */ |
86 | u8 rfu[11]; | |
82487711 | 87 | u8 checksum; /* Modulo 256 checksum must give 0 */ |
1da177e4 LT |
88 | struct irq_info slots[0]; |
89 | } __attribute__((packed)); | |
90 | ||
91 | extern unsigned int pcibios_irq_mask; | |
92 | ||
d19f61f0 | 93 | extern raw_spinlock_t pci_config_lock; |
1da177e4 LT |
94 | |
95 | extern int (*pcibios_enable_irq)(struct pci_dev *dev); | |
87bec66b | 96 | extern void (*pcibios_disable_irq)(struct pci_dev *dev); |
928cf8c6 | 97 | |
6c777e87 BH |
98 | extern bool mp_should_keep_irq(struct device *dev); |
99 | ||
b6ce068a MW |
100 | struct pci_raw_ops { |
101 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, | |
102 | int reg, int len, u32 *val); | |
103 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, | |
104 | int reg, int len, u32 val); | |
105 | }; | |
106 | ||
72da0b07 JB |
107 | extern const struct pci_raw_ops *raw_pci_ops; |
108 | extern const struct pci_raw_ops *raw_pci_ext_ops; | |
b6ce068a | 109 | |
c0fa4078 | 110 | extern const struct pci_raw_ops pci_mmcfg; |
72da0b07 | 111 | extern const struct pci_raw_ops pci_direct_conf1; |
14d7ca5c | 112 | extern bool port_cf9_safe; |
928cf8c6 | 113 | |
8dd779b1 | 114 | /* arch_initcall level */ |
5e544d61 AK |
115 | extern int pci_direct_probe(void); |
116 | extern void pci_direct_init(int type); | |
92c05fc1 | 117 | extern void pci_pcbios_init(void); |
8dd779b1 RR |
118 | extern void __init dmi_check_pciprobe(void); |
119 | extern void __init dmi_check_skip_isa_align(void); | |
120 | ||
121 | /* some common used subsys_initcalls */ | |
122 | extern int __init pci_acpi_init(void); | |
ab3b3793 | 123 | extern void __init pcibios_irq_init(void); |
8dd779b1 | 124 | extern int __init pcibios_init(void); |
b72d0db9 | 125 | extern int pci_legacy_init(void); |
9325a28c | 126 | extern void pcibios_fixup_irqs(void); |
5e544d61 | 127 | |
b7867394 OG |
128 | /* pci-mmconfig.c */ |
129 | ||
56ddf4d3 BH |
130 | /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ |
131 | #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) | |
132 | ||
d215a9c8 | 133 | struct pci_mmcfg_region { |
ff097ddd | 134 | struct list_head list; |
56ddf4d3 | 135 | struct resource res; |
d215a9c8 | 136 | u64 address; |
3f0f5503 | 137 | char __iomem *virt; |
d7e6b66f BH |
138 | u16 segment; |
139 | u8 start_bus; | |
140 | u8 end_bus; | |
56ddf4d3 | 141 | char name[PCI_MMCFG_RESOURCE_NAME_LEN]; |
d215a9c8 BH |
142 | }; |
143 | ||
429d512e | 144 | extern int __init pci_mmcfg_arch_init(void); |
0b64ad71 | 145 | extern void __init pci_mmcfg_arch_free(void); |
a18e3690 | 146 | extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); |
9cf0105d | 147 | extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); |
a18e3690 GKH |
148 | extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, |
149 | phys_addr_t addr); | |
9c95111b | 150 | extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); |
f6e1d8cc | 151 | extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); |
3320ad99 | 152 | |
ff097ddd | 153 | extern struct list_head pci_mmcfg_list; |
c4bf2f37 | 154 | |
df5eb1d6 BH |
155 | #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) |
156 | ||
3320ad99 | 157 | /* |
21461775 TN |
158 | * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use |
159 | * %eax. No other source or target registers may be used. The following | |
160 | * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's | |
161 | * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, | |
162 | * "MMIO Configuration Coding Requirements". | |
3320ad99 | 163 | */ |
164 | static inline unsigned char mmio_config_readb(void __iomem *pos) | |
165 | { | |
166 | u8 val; | |
167 | asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); | |
168 | return val; | |
169 | } | |
170 | ||
171 | static inline unsigned short mmio_config_readw(void __iomem *pos) | |
172 | { | |
173 | u16 val; | |
174 | asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); | |
175 | return val; | |
176 | } | |
177 | ||
178 | static inline unsigned int mmio_config_readl(void __iomem *pos) | |
179 | { | |
180 | u32 val; | |
181 | asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); | |
182 | return val; | |
183 | } | |
184 | ||
185 | static inline void mmio_config_writeb(void __iomem *pos, u8 val) | |
186 | { | |
82487711 | 187 | asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory"); |
3320ad99 | 188 | } |
189 | ||
190 | static inline void mmio_config_writew(void __iomem *pos, u16 val) | |
191 | { | |
82487711 | 192 | asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory"); |
3320ad99 | 193 | } |
194 | ||
195 | static inline void mmio_config_writel(void __iomem *pos, u32 val) | |
196 | { | |
82487711 | 197 | asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory"); |
3320ad99 | 198 | } |
b72d0db9 TG |
199 | |
200 | #ifdef CONFIG_PCI | |
201 | # ifdef CONFIG_ACPI | |
202 | # define x86_default_pci_init pci_acpi_init | |
203 | # else | |
204 | # define x86_default_pci_init pci_legacy_init | |
205 | # endif | |
ab3b3793 | 206 | # define x86_default_pci_init_irq pcibios_irq_init |
9325a28c | 207 | # define x86_default_pci_fixup_irqs pcibios_fixup_irqs |
b72d0db9 TG |
208 | #else |
209 | # define x86_default_pci_init NULL | |
ab3b3793 | 210 | # define x86_default_pci_init_irq NULL |
9325a28c | 211 | # define x86_default_pci_fixup_irqs NULL |
b72d0db9 | 212 | #endif |