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5c167b85 IM |
1 | #ifndef _ASM_X86_PERF_COUNTER_H |
2 | #define _ASM_X86_PERF_COUNTER_H | |
003a46cf | 3 | |
241771ef IM |
4 | #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 |
5 | #define MSR_ARCH_PERFMON_PERFCTR1 0xc2 | |
003a46cf | 6 | |
241771ef IM |
7 | #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 |
8 | #define MSR_ARCH_PERFMON_EVENTSEL1 0x187 | |
003a46cf | 9 | |
241771ef IM |
10 | #define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22) |
11 | #define ARCH_PERFMON_EVENTSEL_INT (1 << 20) | |
12 | #define ARCH_PERFMON_EVENTSEL_OS (1 << 17) | |
13 | #define ARCH_PERFMON_EVENTSEL_USR (1 << 16) | |
003a46cf | 14 | |
241771ef IM |
15 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
16 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) | |
17 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 | |
003a46cf | 18 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ |
241771ef IM |
19 | (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) |
20 | ||
21 | #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 | |
003a46cf TG |
22 | |
23 | union cpuid10_eax { | |
24 | struct { | |
25 | unsigned int version_id:8; | |
26 | unsigned int num_counters:8; | |
27 | unsigned int bit_width:8; | |
28 | unsigned int mask_length:8; | |
29 | } split; | |
30 | unsigned int full; | |
31 | }; | |
32 | ||
241771ef IM |
33 | #ifdef CONFIG_PERF_COUNTERS |
34 | extern void init_hw_perf_counters(void); | |
35 | extern void perf_counters_lapic_init(int nmi); | |
36 | #else | |
37 | static inline void init_hw_perf_counters(void) { } | |
38 | static inline void perf_counters_lapic_init(int nmi) { } | |
39 | #endif | |
40 | ||
5c167b85 | 41 | #endif /* _ASM_X86_PERF_COUNTER_H */ |