[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / perf_event.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define INTEL_PMC_MAX_GENERIC				       32
#define INTEL_PMC_MAX_FIXED					3
#define INTEL_PMC_IDX_FIXED				       32

#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL		(1ULL << 19)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define HSW_IN_TX					(1ULL << 32)
#define HSW_IN_TX_CHECKPOINTED				(1ULL << 33)

#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
#define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
#define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)

#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define X86_ALL_EVENT_FLAGS  			\
	(ARCH_PERFMON_EVENTSEL_EDGE |  		\
	 ARCH_PERFMON_EVENTSEL_INV | 		\
	 ARCH_PERFMON_EVENTSEL_CMASK | 		\
	 ARCH_PERFMON_EVENTSEL_ANY | 		\
	 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | 	\
	 HSW_IN_TX | 				\
	 HSW_IN_TX_CHECKPOINTED)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)
#define AMD64_RAW_EVENT_MASK_NB		\
	(AMD64_EVENTSEL_EVENT        |  \
	 ARCH_PERFMON_EVENTSEL_UMASK)
#define AMD64_NUM_COUNTERS				4
#define AMD64_NUM_COUNTERS_CORE				6
#define AMD64_NUM_COUNTERS_NB				4

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX		0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
#define ARCH_PERFMON_EVENTS_COUNT			7

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_ebx {
	struct {
		unsigned int no_unhalted_core_cycles:1;
		unsigned int no_instructions_retired:1;
		unsigned int no_unhalted_reference_cycles:1;
		unsigned int no_llc_reference:1;
		unsigned int no_llc_misses:1;
		unsigned int no_branch_instruction_retired:1;
		unsigned int no_branch_misses_retired:1;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:5;
		unsigned int bit_width_fixed:8;
		unsigned int reserved:19;
	} split;
	unsigned int full;
};

struct x86_pmu_capability {
	int		version;
	int		num_counters_gp;
	int		num_counters_fixed;
	int		bit_width_gp;
	int		bit_width_fixed;
	unsigned int	events_mask;
	int		events_mask_len;
};

/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS	(INTEL_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
#define INTEL_PMC_IDX_FIXED_CPU_CYCLES	(INTEL_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
#define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)
#define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define INTEL_PMC_IDX_FIXED_BTS				(INTEL_PMC_IDX_FIXED + 16)

#define GLOBAL_STATUS_COND_CHG				BIT_ULL(63)
#define GLOBAL_STATUS_BUFFER_OVF			BIT_ULL(62)
#define GLOBAL_STATUS_UNC_OVF				BIT_ULL(61)
#define GLOBAL_STATUS_ASIF				BIT_ULL(60)
#define GLOBAL_STATUS_COUNTERS_FROZEN			BIT_ULL(59)
#define GLOBAL_STATUS_LBRS_FROZEN			BIT_ULL(58)
#define GLOBAL_STATUS_TRACE_TOPAPMI			BIT_ULL(55)

/*
 * IBS cpuid feature detection
 */

#define IBS_CPUID_FEATURES		0x8000001b

/*
 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
 * bit 0 is used to indicate the existence of IBS.
 */
#define IBS_CAPS_AVAIL			(1U<<0)
#define IBS_CAPS_FETCHSAM		(1U<<1)
#define IBS_CAPS_OPSAM			(1U<<2)
#define IBS_CAPS_RDWROPCNT		(1U<<3)
#define IBS_CAPS_OPCNT			(1U<<4)
#define IBS_CAPS_BRNTRGT		(1U<<5)
#define IBS_CAPS_OPCNTEXT		(1U<<6)
#define IBS_CAPS_RIPINVALIDCHK		(1U<<7)
#define IBS_CAPS_OPBRNFUSE		(1U<<8)
#define IBS_CAPS_FETCHCTLEXTD		(1U<<9)
#define IBS_CAPS_OPDATA4		(1U<<10)

#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
					 | IBS_CAPS_FETCHSAM	\
					 | IBS_CAPS_OPSAM)

/*
 * IBS APIC setup
 */
#define IBSCTL				0x1cc
#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)
#define IBSCTL_LVT_OFFSET_MASK		0x0F

/* ibs fetch bits/masks */
#define IBS_FETCH_RAND_EN	(1ULL<<57)
#define IBS_FETCH_VAL		(1ULL<<49)
#define IBS_FETCH_ENABLE	(1ULL<<48)
#define IBS_FETCH_CNT		0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT	0x0000FFFFULL

/* ibs op bits/masks */
/* lower 4 bits of the current count are ignored: */
#define IBS_OP_CUR_CNT		(0xFFFF0ULL<<32)
#define IBS_OP_CNT_CTL		(1ULL<<19)
#define IBS_OP_VAL		(1ULL<<18)
#define IBS_OP_ENABLE		(1ULL<<17)
#define IBS_OP_MAX_CNT		0x0000FFFFULL
#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
#define IBS_RIP_INVALID		(1ULL<<38)

#ifdef CONFIG_X86_LOCAL_APIC
extern u32 get_ibs_caps(void);
#else
static inline u32 get_ibs_caps(void) { return 0; }
#endif

#ifdef CONFIG_PERF_EVENTS
extern void perf_events_lapic_init(void);

/*
 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
 * unused and ABI specified to be 0, so nobody should care what we do with
 * them.
 *
 * EXACT - the IP points to the exact instruction that triggered the
 *         event (HW bugs exempt).
 * VM    - original X86_VM_MASK; see set_linear_ip().
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)
#define PERF_EFLAGS_VM		(1UL << 5)

struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#include <asm/stacktrace.h>

/*
 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 * and the comment with PERF_EFLAGS_EXACT.
 */
#define perf_arch_fetch_caller_regs(regs, __ip)		{	\
	(regs)->ip = (__ip);					\
	(regs)->bp = caller_frame_pointer();			\
	(regs)->cs = __KERNEL_CS;				\
	regs->flags = 0;					\
	asm volatile(						\
		_ASM_MOV "%%"_ASM_SP ", %0\n"			\
		: "=m" ((regs)->sp)				\
		:: "memory"					\
	);							\
}

struct perf_guest_switch_msr {
	unsigned msr;
	u64 host, guest;
};

extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
extern void perf_check_microcode(void);
#else
static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
{
	*nr = 0;
	return NULL;
}

static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	memset(cap, 0, sizeof(*cap));
}

static inline void perf_events_lapic_init(void)	{ }
static inline void perf_check_microcode(void) { }
#endif

#ifdef CONFIG_CPU_SUP_INTEL
 extern void intel_pt_handle_vmx(int on);
#endif

#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 extern void amd_pmu_enable_virt(void);
 extern void amd_pmu_disable_virt(void);
#else
 static inline void amd_pmu_enable_virt(void) { }
 static inline void amd_pmu_disable_virt(void) { }
#endif

#define arch_perf_out_copy_user copy_from_user_nmi

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
cdd6c482 IM	2	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	3	#define _ASM_X86_PERF_EVENT_H
003a46cf	4
eb2b8618	5	/*
cdd6c482	6	* Performance event hw details:
eb2b8618 IM	7	*/
eb2b8618 IM	8
15c7ad51 RR	9	#define INTEL_PMC_MAX_GENERIC 32
	10	#define INTEL_PMC_MAX_FIXED 3
	11	#define INTEL_PMC_IDX_FIXED 32
eb2b8618	12
862a1a5f IM	13	#define X86_PMC_IDX_MAX 64
862a1a5f IM	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
a098f448 RR	21	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	22	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	23	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	24	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	25	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
a7b9d2cc	26	#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
a098f448 RR	27	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	28	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	29	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	30	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	31	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	32
3a632cb2 AK	33	#define HSW_IN_TX (1ULL << 32)
	34	#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
	35
e259514e	36	#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
9f19010a JS	37	#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
9f19010a JS	38	#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
011af857	39
e259514e JS	40	#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
	41	#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
	42	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
	43
a098f448 RR	44	#define AMD64_EVENTSEL_EVENT \
	45	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	46	#define INTEL_ARCH_EVENT_MASK \
	47	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	48
	49	#define X86_RAW_EVENT_MASK \
	50	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	51	ARCH_PERFMON_EVENTSEL_UMASK \| \
	52	ARCH_PERFMON_EVENTSEL_EDGE \| \
	53	ARCH_PERFMON_EVENTSEL_INV \| \
	54	ARCH_PERFMON_EVENTSEL_CMASK)
86a04461 AK	55	#define X86_ALL_EVENT_FLAGS \
	56	(ARCH_PERFMON_EVENTSEL_EDGE \| \
	57	ARCH_PERFMON_EVENTSEL_INV \| \
	58	ARCH_PERFMON_EVENTSEL_CMASK \| \
	59	ARCH_PERFMON_EVENTSEL_ANY \| \
	60	ARCH_PERFMON_EVENTSEL_PIN_CONTROL \| \
	61	HSW_IN_TX \| \
	62	HSW_IN_TX_CHECKPOINTED)
a098f448 RR	63	#define AMD64_RAW_EVENT_MASK \
	64	(X86_RAW_EVENT_MASK \| \
	65	AMD64_EVENTSEL_EVENT)
e259514e JS	66	#define AMD64_RAW_EVENT_MASK_NB \
	67	(AMD64_EVENTSEL_EVENT \| \
	68	ARCH_PERFMON_EVENTSEL_UMASK)
ee5789db	69	#define AMD64_NUM_COUNTERS 4
b1dc3c48	70	#define AMD64_NUM_COUNTERS_CORE 6
e259514e	71	#define AMD64_NUM_COUNTERS_NB 4
04a705df	72
ee5789db	73	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef	74	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
ee5789db	75	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	76	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	77	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
241771ef IM	78
ee5789db	79	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
ffb871bc	80	#define ARCH_PERFMON_EVENTS_COUNT 7
003a46cf	81
eb2b8618 IM	82	/*
	83	* Intel "Architectural Performance Monitoring" CPUID
	84	* detection/enumeration details:
	85	*/
003a46cf TG	86	union cpuid10_eax {
	87	struct {
	88	unsigned int version_id:8;
948b1bb8	89	unsigned int num_counters:8;
003a46cf TG	90	unsigned int bit_width:8;
	91	unsigned int mask_length:8;
	92	} split;
	93	unsigned int full;
	94	};
	95
ffb871bc GN	96	union cpuid10_ebx {
	97	struct {
	98	unsigned int no_unhalted_core_cycles:1;
	99	unsigned int no_instructions_retired:1;
	100	unsigned int no_unhalted_reference_cycles:1;
	101	unsigned int no_llc_reference:1;
	102	unsigned int no_llc_misses:1;
	103	unsigned int no_branch_instruction_retired:1;
	104	unsigned int no_branch_misses_retired:1;
	105	} split;
	106	unsigned int full;
	107	};
	108
703e937c IM	109	union cpuid10_edx {
703e937c IM	110	struct {
e768aee8 LS	111	unsigned int num_counters_fixed:5;
	112	unsigned int bit_width_fixed:8;
	113	unsigned int reserved:19;
703e937c IM	114	} split;
	115	unsigned int full;
	116	};
	117
b3d9468a GN	118	struct x86_pmu_capability {
	119	int version;
	120	int num_counters_gp;
	121	int num_counters_fixed;
	122	int bit_width_gp;
	123	int bit_width_fixed;
	124	unsigned int events_mask;
	125	int events_mask_len;
	126	};
703e937c IM	127
703e937c IM	128	/*
cdd6c482	129	* Fixed-purpose performance events:
703e937c IM	130	*/
703e937c IM	131
862a1a5f IM	132	/*
	133	* All 3 fixed-mode PMCs are configured via this single MSR:
	134	*/
cd09c0c4	135	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
862a1a5f IM	136
	137	/*
	138	* The counts are available in three separate MSRs:
	139	*/
	140
703e937c	141	/* Instr_Retired.Any: */
cd09c0c4	142	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
15c7ad51	143	#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
703e937c IM	144
703e937c IM	145	/* CPU_CLK_Unhalted.Core: */
cd09c0c4	146	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
15c7ad51	147	#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
703e937c IM	148
703e937c IM	149	/* CPU_CLK_Unhalted.Ref: */
cd09c0c4	150	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
15c7ad51 RR	151	#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
15c7ad51 RR	152	#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
703e937c	153
30dd568c MM	154	/*
	155	* We model BTS tracing as another fixed-mode PMC.
	156	*
cdd6c482 IM	157	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	158	* values are used by actual fixed events and higher values are used
30dd568c MM	159	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
30dd568c MM	160	*/
15c7ad51	161	#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
30dd568c	162
b83ff1c8 AK	163	#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
	164	#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
	165	#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
	166	#define GLOBAL_STATUS_ASIF BIT_ULL(60)
	167	#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
	168	#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
5690ae28	169	#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
b83ff1c8	170
ee5789db RR	171	/*
	172	* IBS cpuid feature detection
	173	*/
	174
	175	#define IBS_CPUID_FEATURES 0x8000001b
	176
	177	/*
	178	* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
	179	* bit 0 is used to indicate the existence of IBS.
	180	*/
	181	#define IBS_CAPS_AVAIL (1U<<0)
	182	#define IBS_CAPS_FETCHSAM (1U<<1)
	183	#define IBS_CAPS_OPSAM (1U<<2)
	184	#define IBS_CAPS_RDWROPCNT (1U<<3)
	185	#define IBS_CAPS_OPCNT (1U<<4)
	186	#define IBS_CAPS_BRNTRGT (1U<<5)
	187	#define IBS_CAPS_OPCNTEXT (1U<<6)
d47e8238	188	#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
904cb367 AG	189	#define IBS_CAPS_OPBRNFUSE (1U<<8)
	190	#define IBS_CAPS_FETCHCTLEXTD (1U<<9)
	191	#define IBS_CAPS_OPDATA4 (1U<<10)
ee5789db RR	192
	193	#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
	194	\| IBS_CAPS_FETCHSAM \
	195	\| IBS_CAPS_OPSAM)
	196
	197	/*
	198	* IBS APIC setup
	199	*/
	200	#define IBSCTL 0x1cc
	201	#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
	202	#define IBSCTL_LVT_OFFSET_MASK 0x0F
	203
d47e8238	204	/* ibs fetch bits/masks */
b47fad3b RR	205	#define IBS_FETCH_RAND_EN (1ULL<<57)
	206	#define IBS_FETCH_VAL (1ULL<<49)
	207	#define IBS_FETCH_ENABLE (1ULL<<48)
	208	#define IBS_FETCH_CNT 0xFFFF0000ULL
	209	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1	210
d47e8238	211	/* ibs op bits/masks */
db98c5fa RR	212	/* lower 4 bits of the current count are ignored: */
db98c5fa RR	213	#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
b47fad3b RR	214	#define IBS_OP_CNT_CTL (1ULL<<19)
	215	#define IBS_OP_VAL (1ULL<<18)
	216	#define IBS_OP_ENABLE (1ULL<<17)
	217	#define IBS_OP_MAX_CNT 0x0000FFFFULL
	218	#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
d47e8238	219	#define IBS_RIP_INVALID (1ULL<<38)
30dd568c	220
978da300	221	#ifdef CONFIG_X86_LOCAL_APIC
b7169166	222	extern u32 get_ibs_caps(void);
978da300 RR	223	#else
	224	static inline u32 get_ibs_caps(void) { return 0; }
	225	#endif
b7169166	226
cdd6c482	227	#ifdef CONFIG_PERF_EVENTS
cdd6c482	228	extern void perf_events_lapic_init(void);
194002b2	229
ef21f683	230	/*
d07bdfd3 PZ	231	* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
	232	* unused and ABI specified to be 0, so nobody should care what we do with
	233	* them.
	234	*
	235	* EXACT - the IP points to the exact instruction that triggered the
	236	* event (HW bugs exempt).
	237	* VM - original X86_VM_MASK; see set_linear_ip().
ef21f683 PZ	238	*/
ef21f683 PZ	239	#define PERF_EFLAGS_EXACT (1UL << 3)
d07bdfd3	240	#define PERF_EFLAGS_VM (1UL << 5)
ef21f683	241
39447b38 ZY	242	struct pt_regs;
	243	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	244	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	245	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	246
b0f82b81 FW	247	#include <asm/stacktrace.h>
	248
	249	/*
	250	* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
	251	* and the comment with PERF_EFLAGS_EXACT.
	252	*/
	253	#define perf_arch_fetch_caller_regs(regs, __ip) { \
	254	(regs)->ip = (__ip); \
	255	(regs)->bp = caller_frame_pointer(); \
	256	(regs)->cs = __KERNEL_CS; \
	257	regs->flags = 0; \
9e46294d FW	258	asm volatile( \
	259	_ASM_MOV "%%"_ASM_SP ", %0\n" \
	260	: "=m" ((regs)->sp) \
	261	:: "memory" \
	262	); \
b0f82b81 FW	263	}
b0f82b81 FW	264
144d31e6 GN	265	struct perf_guest_switch_msr {
	266	unsigned msr;
	267	u64 host, guest;
	268	};
	269
	270	extern struct perf_guest_switch_msr perf_guest_get_msrs(int nr);
b3d9468a	271	extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
c93dc84c	272	extern void perf_check_microcode(void);
241771ef	273	#else
35d56ca9	274	static inline struct perf_guest_switch_msr perf_guest_get_msrs(int nr)
144d31e6 GN	275	{
	276	*nr = 0;
	277	return NULL;
	278	}
	279
b3d9468a GN	280	static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
	281	{
	282	memset(cap, 0, sizeof(*cap));
	283	}
	284
cdd6c482	285	static inline void perf_events_lapic_init(void) { }
c93dc84c	286	static inline void perf_check_microcode(void) { }
241771ef IM	287	#endif
241771ef IM	288
1c5ac21a AS	289	#ifdef CONFIG_CPU_SUP_INTEL
	290	extern void intel_pt_handle_vmx(int on);
	291	#endif
	292
1018faa6 JR	293	#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
	294	extern void amd_pmu_enable_virt(void);
	295	extern void amd_pmu_disable_virt(void);
	296	#else
	297	static inline void amd_pmu_enable_virt(void) { }
	298	static inline void amd_pmu_disable_virt(void) { }
	299	#endif
	300
91d7753a FW	301	#define arch_perf_out_copy_user copy_from_user_nmi
91d7753a FW	302
cdd6c482	303	#endif /* _ASM_X86_PERF_EVENT_H */