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perf: Fix unexported generic perf_arch_fetch_caller_regs
[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / perf_event_p4.h
CommitLineData
a072738e
CG		 1/*
2 * Netburst Perfomance Events (P4, old Xeon)
3 */
4
5#ifndef PERF_EVENT_P4_H
6#define PERF_EVENT_P4_H
7
8#include <linux/cpu.h>
9#include <linux/bitops.h>
10
11/*
12 * NetBurst has perfomance MSRs shared between
13 * threads if HT is turned on, ie for both logical
14 * processors (mem: in turn in Atom with HT support
15 * perf-MSRs are not shared and every thread has its
16 * own perf-MSRs set)
17 */
18#define ARCH_P4_TOTAL_ESCR (46)
19#define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */
20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
21#define ARCH_P4_MAX_CCCR (18)
22#define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2)
23
24#define P4_EVNTSEL_EVENT_MASK 0x7e000000U
25#define P4_EVNTSEL_EVENT_SHIFT 25
26#define P4_EVNTSEL_EVENTMASK_MASK 0x01fffe00U
27#define P4_EVNTSEL_EVENTMASK_SHIFT 9
28#define P4_EVNTSEL_TAG_MASK 0x000001e0U
29#define P4_EVNTSEL_TAG_SHIFT 5
30#define P4_EVNTSEL_TAG_ENABLE 0x00000010U
31#define P4_EVNTSEL_T0_OS 0x00000008U
32#define P4_EVNTSEL_T0_USR 0x00000004U
33#define P4_EVNTSEL_T1_OS 0x00000002U
34#define P4_EVNTSEL_T1_USR 0x00000001U
35
36/* Non HT mask */
37#define P4_EVNTSEL_MASK \
38 (P4_EVNTSEL_EVENT_MASK | \
39 P4_EVNTSEL_EVENTMASK_MASK | \
40 P4_EVNTSEL_TAG_MASK | \
41 P4_EVNTSEL_TAG_ENABLE | \
42 P4_EVNTSEL_T0_OS | \
43 P4_EVNTSEL_T0_USR)
44
45/* HT mask */
46#define P4_EVNTSEL_MASK_HT \
47 (P4_EVNTSEL_MASK | \
48 P4_EVNTSEL_T1_OS | \
49 P4_EVNTSEL_T1_USR)
50
51#define P4_CCCR_OVF 0x80000000U
52#define P4_CCCR_CASCADE 0x40000000U
53#define P4_CCCR_OVF_PMI_T0 0x04000000U
54#define P4_CCCR_OVF_PMI_T1 0x08000000U
55#define P4_CCCR_FORCE_OVF 0x02000000U
56#define P4_CCCR_EDGE 0x01000000U
57#define P4_CCCR_THRESHOLD_MASK 0x00f00000U
58#define P4_CCCR_THRESHOLD_SHIFT 20
59#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
60#define P4_CCCR_COMPLEMENT 0x00080000U
61#define P4_CCCR_COMPARE 0x00040000U
62#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U
63#define P4_CCCR_ESCR_SELECT_SHIFT 13
64#define P4_CCCR_ENABLE 0x00001000U
65#define P4_CCCR_THREAD_SINGLE 0x00010000U
66#define P4_CCCR_THREAD_BOTH 0x00020000U
67#define P4_CCCR_THREAD_ANY 0x00030000U
68
69/* Non HT mask */
70#define P4_CCCR_MASK \
71 (P4_CCCR_OVF | \
72 P4_CCCR_CASCADE | \
73 P4_CCCR_OVF_PMI_T0 | \
74 P4_CCCR_FORCE_OVF | \
75 P4_CCCR_EDGE | \
76 P4_CCCR_THRESHOLD_MASK | \
77 P4_CCCR_COMPLEMENT | \
78 P4_CCCR_COMPARE | \
79 P4_CCCR_ESCR_SELECT_MASK | \
80 P4_CCCR_ENABLE)
81
82/* HT mask */
83#define P4_CCCR_MASK_HT \
84 (P4_CCCR_MASK | \
85 P4_CCCR_THREAD_ANY)
86
87/*
88 * format is 32 bit: ee ss aa aa
89 * where
90 * ee - 8 bit event
91 * ss - 8 bit selector
92 * aa aa - 16 bits reserved for tags/attributes
93 */
94#define P4_EVENT_PACK(event, selector) (((event) << 24) | ((selector) << 16))
95#define P4_EVENT_UNPACK_EVENT(packed) (((packed) >> 24) & 0xff)
96#define P4_EVENT_UNPACK_SELECTOR(packed) (((packed) >> 16) & 0xff)
97#define P4_EVENT_PACK_ATTR(attr) ((attr))
98#define P4_EVENT_UNPACK_ATTR(packed) ((packed) & 0xffff)
99#define P4_MAKE_EVENT_ATTR(class, name, bit) class##_##name = (1 << bit)
100#define P4_EVENT_ATTR(class, name) class##_##name
101#define P4_EVENT_ATTR_STR(class, name) __stringify(class##_##name)
102
103/*
104 * config field is 64bit width and consists of
105 * HT << 63 | ESCR << 32 | CCCR
106 * where HT is HyperThreading bit (since ESCR
107 * has it reserved we may use it for own purpose)
108 *
109 * note that this is NOT the addresses of respective
110 * ESCR and CCCR but rather an only packed value should
111 * be unpacked and written to a proper addresses
112 *
113 * the base idea is to pack as much info as
114 * possible
115 */
116#define p4_config_pack_escr(v) (((u64)(v)) << 32)
117#define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL)
118#define p4_config_unpack_escr(v) (((u64)(v)) >> 32)
119#define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL)
120
121#define p4_config_unpack_emask(v) \
122 ({ \
123 u32 t = p4_config_unpack_escr((v)); \
124 t &= P4_EVNTSEL_EVENTMASK_MASK; \
125 t >>= P4_EVNTSEL_EVENTMASK_SHIFT; \
126 t; \
127 })
128
129#define P4_CONFIG_HT_SHIFT 63
130#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)
131
132static inline u32 p4_config_unpack_opcode(u64 config)
133{
134 u32 e, s;
135
136 /*
137 * we don't care about HT presence here since
138 * event opcode doesn't depend on it
139 */
140 e = (p4_config_unpack_escr(config) & P4_EVNTSEL_EVENT_MASK) >> P4_EVNTSEL_EVENT_SHIFT;
141 s = (p4_config_unpack_cccr(config) & P4_CCCR_ESCR_SELECT_MASK) >> P4_CCCR_ESCR_SELECT_SHIFT;
142
143 return P4_EVENT_PACK(e, s);
144}
145
146static inline bool p4_is_event_cascaded(u64 config)
147{
148 u32 cccr = p4_config_unpack_cccr(config);
149 return !!(cccr & P4_CCCR_CASCADE);
150}
151
152static inline int p4_ht_config_thread(u64 config)
153{
154 return !!(config & P4_CONFIG_HT);
155}
156
157static inline u64 p4_set_ht_bit(u64 config)
158{
159 return config | P4_CONFIG_HT;
160}
161
162static inline u64 p4_clear_ht_bit(u64 config)
163{
164 return config & ~P4_CONFIG_HT;
165}
166
167static inline int p4_ht_active(void)
168{
169#ifdef CONFIG_SMP
170 return smp_num_siblings > 1;
171#endif
172 return 0;
173}
174
175static inline int p4_ht_thread(int cpu)
176{
177#ifdef CONFIG_SMP
178 if (smp_num_siblings == 2)
179 return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map));
180#endif
181 return 0;
182}
183
184static inline int p4_should_swap_ts(u64 config, int cpu)
185{
186 return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
187}
188
189static inline u32 p4_default_cccr_conf(int cpu)
190{
191 /*
192 * Note that P4_CCCR_THREAD_ANY is "required" on
193 * non-HT machines (on HT machines we count TS events
194 * regardless the state of second logical processor
195 */
196 u32 cccr = P4_CCCR_THREAD_ANY;
197
198 if (!p4_ht_thread(cpu))
199 cccr |= P4_CCCR_OVF_PMI_T0;
200 else
201 cccr |= P4_CCCR_OVF_PMI_T1;
202
203 return cccr;
204}
205
206static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
207{
208 u32 escr = 0;
209
210 if (!p4_ht_thread(cpu)) {
211 if (!exclude_os)
212 escr |= P4_EVNTSEL_T0_OS;
213 if (!exclude_usr)
214 escr |= P4_EVNTSEL_T0_USR;
215 } else {
216 if (!exclude_os)
217 escr |= P4_EVNTSEL_T1_OS;
218 if (!exclude_usr)
219 escr |= P4_EVNTSEL_T1_USR;
220 }
221
222 return escr;
223}
224
225/*
226 * Comments below the event represent ESCR restriction
227 * for this event and counter index per ESCR
228 *
229 * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
230 * processor builds (family 0FH, models 01H-02H). These MSRs
231 * are not available on later versions, so that we don't use
232 * them completely
233 *
234 * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
235 * working so that we should not use this CCCR and respective
236 * counter as result
237 */
238#define P4_TC_DELIVER_MODE P4_EVENT_PACK(0x01, 0x01)
239 /*
240 * MSR_P4_TC_ESCR0: 4, 5
241 * MSR_P4_TC_ESCR1: 6, 7
242 */
243
244#define P4_BPU_FETCH_REQUEST P4_EVENT_PACK(0x03, 0x00)
245 /*
246 * MSR_P4_BPU_ESCR0: 0, 1
247 * MSR_P4_BPU_ESCR1: 2, 3
248 */
249
250#define P4_ITLB_REFERENCE P4_EVENT_PACK(0x18, 0x03)
251 /*
252 * MSR_P4_ITLB_ESCR0: 0, 1
253 * MSR_P4_ITLB_ESCR1: 2, 3
254 */
255
256#define P4_MEMORY_CANCEL P4_EVENT_PACK(0x02, 0x05)
257 /*
258 * MSR_P4_DAC_ESCR0: 8, 9
259 * MSR_P4_DAC_ESCR1: 10, 11
260 */
261
262#define P4_MEMORY_COMPLETE P4_EVENT_PACK(0x08, 0x02)
263 /*
264 * MSR_P4_SAAT_ESCR0: 8, 9
265 * MSR_P4_SAAT_ESCR1: 10, 11
266 */
267
268#define P4_LOAD_PORT_REPLAY P4_EVENT_PACK(0x04, 0x02)
269 /*
270 * MSR_P4_SAAT_ESCR0: 8, 9
271 * MSR_P4_SAAT_ESCR1: 10, 11
272 */
273
274#define P4_STORE_PORT_REPLAY P4_EVENT_PACK(0x05, 0x02)
275 /*
276 * MSR_P4_SAAT_ESCR0: 8, 9
277 * MSR_P4_SAAT_ESCR1: 10, 11
278 */
279
280#define P4_MOB_LOAD_REPLAY P4_EVENT_PACK(0x03, 0x02)
281 /*
282 * MSR_P4_MOB_ESCR0: 0, 1
283 * MSR_P4_MOB_ESCR1: 2, 3
284 */
285
286#define P4_PAGE_WALK_TYPE P4_EVENT_PACK(0x01, 0x04)
287 /*
288 * MSR_P4_PMH_ESCR0: 0, 1
289 * MSR_P4_PMH_ESCR1: 2, 3
290 */
291
292#define P4_BSQ_CACHE_REFERENCE P4_EVENT_PACK(0x0c, 0x07)
293 /*
294 * MSR_P4_BSU_ESCR0: 0, 1
295 * MSR_P4_BSU_ESCR1: 2, 3
296 */
297
298#define P4_IOQ_ALLOCATION P4_EVENT_PACK(0x03, 0x06)
299 /*
300 * MSR_P4_FSB_ESCR0: 0, 1
301 * MSR_P4_FSB_ESCR1: 2, 3
302 */
303
304#define P4_IOQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x1a, 0x06)
305 /*
306 * MSR_P4_FSB_ESCR1: 2, 3
307 */
308
309#define P4_FSB_DATA_ACTIVITY P4_EVENT_PACK(0x17, 0x06)
310 /*
311 * MSR_P4_FSB_ESCR0: 0, 1
312 * MSR_P4_FSB_ESCR1: 2, 3
313 */
314
315#define P4_BSQ_ALLOCATION P4_EVENT_PACK(0x05, 0x07)
316 /*
317 * MSR_P4_BSU_ESCR0: 0, 1
318 */
319
320#define P4_BSQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x06, 0x07)
321 /*
322 * MSR_P4_BSU_ESCR1: 2, 3
323 */
324
325#define P4_SSE_INPUT_ASSIST P4_EVENT_PACK(0x34, 0x01)
326 /*
e4495262
CG		 327 * MSR_P4_FIRM_ESCR0: 8, 9
328 * MSR_P4_FIRM_ESCR1: 10, 11
a072738e
CG		 329 */
330
331#define P4_PACKED_SP_UOP P4_EVENT_PACK(0x08, 0x01)
332 /*
333 * MSR_P4_FIRM_ESCR0: 8, 9
334 * MSR_P4_FIRM_ESCR1: 10, 11
335 */
336
337#define P4_PACKED_DP_UOP P4_EVENT_PACK(0x0c, 0x01)
338 /*
339 * MSR_P4_FIRM_ESCR0: 8, 9
340 * MSR_P4_FIRM_ESCR1: 10, 11
341 */
342
343#define P4_SCALAR_SP_UOP P4_EVENT_PACK(0x0a, 0x01)
344 /*
345 * MSR_P4_FIRM_ESCR0: 8, 9
346 * MSR_P4_FIRM_ESCR1: 10, 11
347 */
348
349#define P4_SCALAR_DP_UOP P4_EVENT_PACK(0x0e, 0x01)
350 /*
351 * MSR_P4_FIRM_ESCR0: 8, 9
352 * MSR_P4_FIRM_ESCR1: 10, 11
353 */
354
355#define P4_64BIT_MMX_UOP P4_EVENT_PACK(0x02, 0x01)
356 /*
357 * MSR_P4_FIRM_ESCR0: 8, 9
358 * MSR_P4_FIRM_ESCR1: 10, 11
359 */
360
361#define P4_128BIT_MMX_UOP P4_EVENT_PACK(0x1a, 0x01)
362 /*
363 * MSR_P4_FIRM_ESCR0: 8, 9
364 * MSR_P4_FIRM_ESCR1: 10, 11
365 */
366
367#define P4_X87_FP_UOP P4_EVENT_PACK(0x04, 0x01)
368 /*
369 * MSR_P4_FIRM_ESCR0: 8, 9
370 * MSR_P4_FIRM_ESCR1: 10, 11
371 */
372
373#define P4_TC_MISC P4_EVENT_PACK(0x06, 0x01)
374 /*
375 * MSR_P4_TC_ESCR0: 4, 5
376 * MSR_P4_TC_ESCR1: 6, 7
377 */
378
379#define P4_GLOBAL_POWER_EVENTS P4_EVENT_PACK(0x13, 0x06)
380 /*
381 * MSR_P4_FSB_ESCR0: 0, 1
382 * MSR_P4_FSB_ESCR1: 2, 3
383 */
384
385#define P4_TC_MS_XFER P4_EVENT_PACK(0x05, 0x00)
386 /*
387 * MSR_P4_MS_ESCR0: 4, 5
388 * MSR_P4_MS_ESCR1: 6, 7
389 */
390
391#define P4_UOP_QUEUE_WRITES P4_EVENT_PACK(0x09, 0x00)
392 /*
393 * MSR_P4_MS_ESCR0: 4, 5
394 * MSR_P4_MS_ESCR1: 6, 7
395 */
396
397#define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02)
398 /*
399 * MSR_P4_TBPU_ESCR0: 4, 5
400 * MSR_P4_TBPU_ESCR0: 6, 7
401 */
402
403#define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02)
404 /*
405 * MSR_P4_TBPU_ESCR0: 4, 5
406 * MSR_P4_TBPU_ESCR0: 6, 7
407 */
408
409#define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01)
410 /*
411 * MSR_P4_ALF_ESCR0: 12, 13, 16
412 * MSR_P4_ALF_ESCR1: 14, 15, 17
413 */
414
415#define P4_WC_BUFFER P4_EVENT_PACK(0x05, 0x05)
416 /*
417 * MSR_P4_DAC_ESCR0: 8, 9
418 * MSR_P4_DAC_ESCR1: 10, 11
419 */
420
421#define P4_B2B_CYCLES P4_EVENT_PACK(0x16, 0x03)
422 /*
423 * MSR_P4_FSB_ESCR0: 0, 1
424 * MSR_P4_FSB_ESCR1: 2, 3
425 */
426
427#define P4_BNR P4_EVENT_PACK(0x08, 0x03)
428 /*
429 * MSR_P4_FSB_ESCR0: 0, 1
430 * MSR_P4_FSB_ESCR1: 2, 3
431 */
432
433#define P4_SNOOP P4_EVENT_PACK(0x06, 0x03)
434 /*
435 * MSR_P4_FSB_ESCR0: 0, 1
436 * MSR_P4_FSB_ESCR1: 2, 3
437 */
438
439#define P4_RESPONSE P4_EVENT_PACK(0x04, 0x03)
440 /*
441 * MSR_P4_FSB_ESCR0: 0, 1
442 * MSR_P4_FSB_ESCR1: 2, 3
443 */
444
445#define P4_FRONT_END_EVENT P4_EVENT_PACK(0x08, 0x05)
446 /*
447 * MSR_P4_CRU_ESCR2: 12, 13, 16
448 * MSR_P4_CRU_ESCR3: 14, 15, 17
449 */
450
451#define P4_EXECUTION_EVENT P4_EVENT_PACK(0x0c, 0x05)
452 /*
453 * MSR_P4_CRU_ESCR2: 12, 13, 16
454 * MSR_P4_CRU_ESCR3: 14, 15, 17
455 */
456
457#define P4_REPLAY_EVENT P4_EVENT_PACK(0x09, 0x05)
458 /*
459 * MSR_P4_CRU_ESCR2: 12, 13, 16
460 * MSR_P4_CRU_ESCR3: 14, 15, 17
461 */
462
463#define P4_INSTR_RETIRED P4_EVENT_PACK(0x02, 0x04)
464 /*
e4495262
CG		 465 * MSR_P4_CRU_ESCR0: 12, 13, 16
466 * MSR_P4_CRU_ESCR1: 14, 15, 17
a072738e
CG		 467 */
468
469#define P4_UOPS_RETIRED P4_EVENT_PACK(0x01, 0x04)
470 /*
471 * MSR_P4_CRU_ESCR2: 12, 13, 16
472 * MSR_P4_CRU_ESCR3: 14, 15, 17
473 */
474
475#define P4_UOP_TYPE P4_EVENT_PACK(0x02, 0x02)
476 /*
477 * MSR_P4_RAT_ESCR0: 12, 13, 16
478 * MSR_P4_RAT_ESCR1: 14, 15, 17
479 */
480
481#define P4_BRANCH_RETIRED P4_EVENT_PACK(0x06, 0x05)
482 /*
483 * MSR_P4_CRU_ESCR2: 12, 13, 16
484 * MSR_P4_CRU_ESCR3: 14, 15, 17
485 */
486
487#define P4_MISPRED_BRANCH_RETIRED P4_EVENT_PACK(0x03, 0x04)
488 /*
489 * MSR_P4_CRU_ESCR0: 12, 13, 16
490 * MSR_P4_CRU_ESCR1: 14, 15, 17
491 */
492
493#define P4_X87_ASSIST P4_EVENT_PACK(0x03, 0x05)
494 /*
495 * MSR_P4_CRU_ESCR2: 12, 13, 16
496 * MSR_P4_CRU_ESCR3: 14, 15, 17
497 */
498
499#define P4_MACHINE_CLEAR P4_EVENT_PACK(0x02, 0x05)
500 /*
501 * MSR_P4_CRU_ESCR2: 12, 13, 16
502 * MSR_P4_CRU_ESCR3: 14, 15, 17
503 */
504
505#define P4_INSTR_COMPLETED P4_EVENT_PACK(0x07, 0x04)
506 /*
507 * MSR_P4_CRU_ESCR0: 12, 13, 16
508 * MSR_P4_CRU_ESCR1: 14, 15, 17
509 */
510
511/*
512 * a caller should use P4_EVENT_ATTR helper to
513 * pick the attribute needed, for example
514 *
515 * P4_EVENT_ATTR(P4_TC_DELIVER_MODE, DD)
516 */
517enum P4_EVENTS_ATTR {
518 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DD, 0),
519 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DB, 1),
520 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DI, 2),
521 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BD, 3),
522 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BB, 4),
523 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BI, 5),
524 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, ID, 6),
525
526 P4_MAKE_EVENT_ATTR(P4_BPU_FETCH_REQUEST, TCMISS, 0),
527
528 P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT, 0),
529 P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, MISS, 1),
530 P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT_UK, 2),
531
532 P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, ST_RB_FULL, 2),
533 P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, 64K_CONF, 3),
534
535 P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, LSC, 0),
536 P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, SSC, 1),
537
538 P4_MAKE_EVENT_ATTR(P4_LOAD_PORT_REPLAY, SPLIT_LD, 1),
539
540 P4_MAKE_EVENT_ATTR(P4_STORE_PORT_REPLAY, SPLIT_ST, 1),
541
542 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STA, 1),
543 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STD, 3),
544 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
545 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
546
547 P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, DTMISS, 0),
548 P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, ITMISS, 1),
549
550 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
551 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
552 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
553 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
554 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
555 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
556 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
557 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
558 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
559
560 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, DEFAULT, 0),
561 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_READ, 5),
562 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_WRITE, 6),
563 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_UC, 7),
564 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WC, 8),
565 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WT, 9),
566 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WP, 10),
567 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WB, 11),
568 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OWN, 13),
569 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OTHER, 14),
570 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, PREFETCH, 15),
571
572 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
573 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
574 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
575 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
576 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
577 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
578 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
579 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
580 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OWN, 13),
581 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OTHER, 14),
582 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
583
584 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
585 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
586 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
587 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
588 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
589 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
590
591 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE0, 0),
592 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE1, 1),
593 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN0, 2),
594 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN1, 3),
595 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
596 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
597 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
598 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
599 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
600 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
601 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE0, 11),
602 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE1, 12),
603 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE2, 13),
604
605 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
606 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
607 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
608 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
609 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
610 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
611 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
612 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
613 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
614 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
615 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
616 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
617 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
618
619 P4_MAKE_EVENT_ATTR(P4_SSE_INPUT_ASSIST, ALL, 15),
620
621 P4_MAKE_EVENT_ATTR(P4_PACKED_SP_UOP, ALL, 15),
622
623 P4_MAKE_EVENT_ATTR(P4_PACKED_DP_UOP, ALL, 15),
624
625 P4_MAKE_EVENT_ATTR(P4_SCALAR_SP_UOP, ALL, 15),
626
627 P4_MAKE_EVENT_ATTR(P4_SCALAR_DP_UOP, ALL, 15),
628
629 P4_MAKE_EVENT_ATTR(P4_64BIT_MMX_UOP, ALL, 15),
630
631 P4_MAKE_EVENT_ATTR(P4_128BIT_MMX_UOP, ALL, 15),
632
633 P4_MAKE_EVENT_ATTR(P4_X87_FP_UOP, ALL, 15),
634
635 P4_MAKE_EVENT_ATTR(P4_TC_MISC, FLUSH, 4),
636
637 P4_MAKE_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING, 0),
638
639 P4_MAKE_EVENT_ATTR(P4_TC_MS_XFER, CISC, 0),
640
641 P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
642 P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
643 P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_ROM, 2),
644
645 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
646 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
647 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
648 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
649
650 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
651 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL, 2),
652 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN, 3),
653 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT, 4),
654
655 P4_MAKE_EVENT_ATTR(P4_RESOURCE_STALL, SBFULL, 5),
656
657 P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_EVICTS, 0),
658 P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_FULL_EVICTS, 1),
659
660 P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, NBOGUS, 0),
661 P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, BOGUS, 1),
662
663 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS0, 0),
664 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS1, 1),
665 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS2, 2),
666 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS3, 3),
667 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS0, 4),
668 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS1, 5),
669 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS2, 6),
670 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS3, 7),
671
672 P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS, 0),
673 P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, BOGUS, 1),
674
675 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG, 0),
676 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSTAG, 1),
677 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG, 2),
678 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSTAG, 3),
679
680 P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, NBOGUS, 0),
681 P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, BOGUS, 1),
682
683 P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS, 1),
684 P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES, 2),
685
686 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNP, 0),
687 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNM, 1),
688 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTP, 2),
689 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTM, 3),
690
691 P4_MAKE_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
692
693 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSU, 0),
694 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSO, 1),
695 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAO, 2),
696 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAU, 3),
697 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, PREA, 4),
698
699 P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, CLEAR, 0),
700 P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, MOCLEAR, 1),
701 P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, SMCLEAR, 2),
702
703 P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, NBOGUS, 0),
704 P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1),
705};
706
707#endif /* PERF_EVENT_P4_H */
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