[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / pgtable_types.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_PGTABLE_DEFS_H
#define _ASM_X86_PGTABLE_DEFS_H

#include <linux/const.h>
#include <linux/mem_encrypt.h>

#include <asm/page_types.h>

#define FIRST_USER_ADDRESS	0UL

#define _PAGE_BIT_PRESENT	0	/* is present */
#define _PAGE_BIT_RW		1	/* writeable */
#define _PAGE_BIT_USER		2	/* userspace addressable */
#define _PAGE_BIT_PWT		3	/* page write through */
#define _PAGE_BIT_PCD		4	/* page cache disabled */
#define _PAGE_BIT_ACCESSED	5	/* was accessed (raised by CPU) */
#define _PAGE_BIT_DIRTY		6	/* was written to (raised by CPU) */
#define _PAGE_BIT_PSE		7	/* 4 MB (or 2MB) page */
#define _PAGE_BIT_PAT		7	/* on 4KB pages */
#define _PAGE_BIT_GLOBAL	8	/* Global TLB entry PPro+ */
#define _PAGE_BIT_SOFTW1	9	/* available for programmer */
#define _PAGE_BIT_SOFTW2	10	/* " */
#define _PAGE_BIT_SOFTW3	11	/* " */
#define _PAGE_BIT_PAT_LARGE	12	/* On 2MB or 1GB pages */
#define _PAGE_BIT_SOFTW4	58	/* available for programmer */
#define _PAGE_BIT_PKEY_BIT0	59	/* Protection Keys, bit 1/4 */
#define _PAGE_BIT_PKEY_BIT1	60	/* Protection Keys, bit 2/4 */
#define _PAGE_BIT_PKEY_BIT2	61	/* Protection Keys, bit 3/4 */
#define _PAGE_BIT_PKEY_BIT3	62	/* Protection Keys, bit 4/4 */
#define _PAGE_BIT_NX		63	/* No execute: only valid after cpuid check */

#define _PAGE_BIT_SPECIAL	_PAGE_BIT_SOFTW1
#define _PAGE_BIT_CPA_TEST	_PAGE_BIT_SOFTW1
#define _PAGE_BIT_SOFT_DIRTY	_PAGE_BIT_SOFTW3 /* software dirty tracking */
#define _PAGE_BIT_DEVMAP	_PAGE_BIT_SOFTW4

/* If _PAGE_BIT_PRESENT is clear, we use these: */
/* - if the user mapped it with PROT_NONE; pte_present gives true */
#define _PAGE_BIT_PROTNONE	_PAGE_BIT_GLOBAL

#define _PAGE_PRESENT	(_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
#define _PAGE_RW	(_AT(pteval_t, 1) << _PAGE_BIT_RW)
#define _PAGE_USER	(_AT(pteval_t, 1) << _PAGE_BIT_USER)
#define _PAGE_PWT	(_AT(pteval_t, 1) << _PAGE_BIT_PWT)
#define _PAGE_PCD	(_AT(pteval_t, 1) << _PAGE_BIT_PCD)
#define _PAGE_ACCESSED	(_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
#define _PAGE_DIRTY	(_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
#define _PAGE_PSE	(_AT(pteval_t, 1) << _PAGE_BIT_PSE)
#define _PAGE_GLOBAL	(_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
#define _PAGE_SOFTW1	(_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1)
#define _PAGE_SOFTW2	(_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2)
#define _PAGE_PAT	(_AT(pteval_t, 1) << _PAGE_BIT_PAT)
#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
#define _PAGE_SPECIAL	(_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
#define _PAGE_CPA_TEST	(_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
#define _PAGE_PKEY_BIT0	(_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT0)
#define _PAGE_PKEY_BIT1	(_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT1)
#define _PAGE_PKEY_BIT2	(_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT2)
#define _PAGE_PKEY_BIT3	(_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT3)
#else
#define _PAGE_PKEY_BIT0	(_AT(pteval_t, 0))
#define _PAGE_PKEY_BIT1	(_AT(pteval_t, 0))
#define _PAGE_PKEY_BIT2	(_AT(pteval_t, 0))
#define _PAGE_PKEY_BIT3	(_AT(pteval_t, 0))
#endif
#define __HAVE_ARCH_PTE_SPECIAL

#define _PAGE_PKEY_MASK (_PAGE_PKEY_BIT0 | \
			 _PAGE_PKEY_BIT1 | \
			 _PAGE_PKEY_BIT2 | \
			 _PAGE_PKEY_BIT3)

#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
#define _PAGE_KNL_ERRATUM_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
#else
#define _PAGE_KNL_ERRATUM_MASK 0
#endif

#ifdef CONFIG_MEM_SOFT_DIRTY
#define _PAGE_SOFT_DIRTY	(_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY)
#else
#define _PAGE_SOFT_DIRTY	(_AT(pteval_t, 0))
#endif

/*
 * Tracking soft dirty bit when a page goes to a swap is tricky.
 * We need a bit which can be stored in pte _and_ not conflict
 * with swap entry format. On x86 bits 1-4 are *not* involved
 * into swap entry computation, but bit 7 is used for thp migration,
 * so we borrow bit 1 for soft dirty tracking.
 *
 * Please note that this bit must be treated as swap dirty page
 * mark if and only if the PTE/PMD has present bit clear!
 */
#ifdef CONFIG_MEM_SOFT_DIRTY
#define _PAGE_SWP_SOFT_DIRTY	_PAGE_RW
#else
#define _PAGE_SWP_SOFT_DIRTY	(_AT(pteval_t, 0))
#endif

#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
#define _PAGE_NX	(_AT(pteval_t, 1) << _PAGE_BIT_NX)
#define _PAGE_DEVMAP	(_AT(u64, 1) << _PAGE_BIT_DEVMAP)
#define __HAVE_ARCH_PTE_DEVMAP
#else
#define _PAGE_NX	(_AT(pteval_t, 0))
#define _PAGE_DEVMAP	(_AT(pteval_t, 0))
#endif

#define _PAGE_PROTNONE	(_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)

#define _PAGE_TABLE_NOENC	(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |\
				 _PAGE_ACCESSED | _PAGE_DIRTY)
#define _KERNPG_TABLE_NOENC	(_PAGE_PRESENT | _PAGE_RW |		\
				 _PAGE_ACCESSED | _PAGE_DIRTY)

/*
 * Set of bits not changed in pte_modify.  The pte's
 * protection key is treated like _PAGE_RW, for
 * instance, and is *not* included in this mask since
 * pte_modify() does modify it.
 */
#define _PAGE_CHG_MASK	(PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT |		\
			 _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY |	\
			 _PAGE_SOFT_DIRTY)
#define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)

/*
 * The cache modes defined here are used to translate between pure SW usage
 * and the HW defined cache mode bits and/or PAT entries.
 *
 * The resulting bits for PWT, PCD and PAT should be chosen in a way
 * to have the WB mode at index 0 (all bits clear). This is the default
 * right now and likely would break too much if changed.
 */
#ifndef __ASSEMBLY__
enum page_cache_mode {
	_PAGE_CACHE_MODE_WB = 0,
	_PAGE_CACHE_MODE_WC = 1,
	_PAGE_CACHE_MODE_UC_MINUS = 2,
	_PAGE_CACHE_MODE_UC = 3,
	_PAGE_CACHE_MODE_WT = 4,
	_PAGE_CACHE_MODE_WP = 5,
	_PAGE_CACHE_MODE_NUM = 8
};
#endif

#define _PAGE_CACHE_MASK	(_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)
#define _PAGE_NOCACHE		(cachemode2protval(_PAGE_CACHE_MODE_UC))
#define _PAGE_CACHE_WP		(cachemode2protval(_PAGE_CACHE_MODE_WP))

#define PAGE_NONE	__pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
				 _PAGE_ACCESSED | _PAGE_NX)

#define PAGE_SHARED_EXEC	__pgprot(_PAGE_PRESENT | _PAGE_RW |	\
					 _PAGE_USER | _PAGE_ACCESSED)
#define PAGE_COPY_NOEXEC	__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
					 _PAGE_ACCESSED | _PAGE_NX)
#define PAGE_COPY_EXEC		__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
					 _PAGE_ACCESSED)
#define PAGE_COPY		PAGE_COPY_NOEXEC
#define PAGE_READONLY		__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
					 _PAGE_ACCESSED | _PAGE_NX)
#define PAGE_READONLY_EXEC	__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
					 _PAGE_ACCESSED)

#define __PAGE_KERNEL_EXEC						\
	(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
#define __PAGE_KERNEL		(__PAGE_KERNEL_EXEC | _PAGE_NX)

#define __PAGE_KERNEL_RO		(__PAGE_KERNEL & ~_PAGE_RW)
#define __PAGE_KERNEL_RX		(__PAGE_KERNEL_EXEC & ~_PAGE_RW)
#define __PAGE_KERNEL_NOCACHE		(__PAGE_KERNEL | _PAGE_NOCACHE)
#define __PAGE_KERNEL_VSYSCALL		(__PAGE_KERNEL_RX | _PAGE_USER)
#define __PAGE_KERNEL_VVAR		(__PAGE_KERNEL_RO | _PAGE_USER)
#define __PAGE_KERNEL_LARGE		(__PAGE_KERNEL | _PAGE_PSE)
#define __PAGE_KERNEL_LARGE_EXEC	(__PAGE_KERNEL_EXEC | _PAGE_PSE)
#define __PAGE_KERNEL_WP		(__PAGE_KERNEL | _PAGE_CACHE_WP)

#define __PAGE_KERNEL_IO		(__PAGE_KERNEL)
#define __PAGE_KERNEL_IO_NOCACHE	(__PAGE_KERNEL_NOCACHE)

#ifndef __ASSEMBLY__

#define _PAGE_ENC	(_AT(pteval_t, sme_me_mask))

#define _KERNPG_TABLE	(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED |	\
			 _PAGE_DIRTY | _PAGE_ENC)
#define _PAGE_TABLE	(_KERNPG_TABLE | _PAGE_USER)

#define __PAGE_KERNEL_ENC	(__PAGE_KERNEL | _PAGE_ENC)
#define __PAGE_KERNEL_ENC_WP	(__PAGE_KERNEL_WP | _PAGE_ENC)

#define __PAGE_KERNEL_NOENC	(__PAGE_KERNEL)
#define __PAGE_KERNEL_NOENC_WP	(__PAGE_KERNEL_WP)

#define PAGE_KERNEL		__pgprot(__PAGE_KERNEL | _PAGE_ENC)
#define PAGE_KERNEL_NOENC	__pgprot(__PAGE_KERNEL)
#define PAGE_KERNEL_RO		__pgprot(__PAGE_KERNEL_RO | _PAGE_ENC)
#define PAGE_KERNEL_EXEC	__pgprot(__PAGE_KERNEL_EXEC | _PAGE_ENC)
#define PAGE_KERNEL_EXEC_NOENC	__pgprot(__PAGE_KERNEL_EXEC)
#define PAGE_KERNEL_RX		__pgprot(__PAGE_KERNEL_RX | _PAGE_ENC)
#define PAGE_KERNEL_NOCACHE	__pgprot(__PAGE_KERNEL_NOCACHE | _PAGE_ENC)
#define PAGE_KERNEL_LARGE	__pgprot(__PAGE_KERNEL_LARGE | _PAGE_ENC)
#define PAGE_KERNEL_LARGE_EXEC	__pgprot(__PAGE_KERNEL_LARGE_EXEC | _PAGE_ENC)
#define PAGE_KERNEL_VSYSCALL	__pgprot(__PAGE_KERNEL_VSYSCALL | _PAGE_ENC)
#define PAGE_KERNEL_VVAR	__pgprot(__PAGE_KERNEL_VVAR | _PAGE_ENC)

#define PAGE_KERNEL_IO		__pgprot(__PAGE_KERNEL_IO)
#define PAGE_KERNEL_IO_NOCACHE	__pgprot(__PAGE_KERNEL_IO_NOCACHE)

#endif	/* __ASSEMBLY__ */

/*         xwr */
#define __P000	PAGE_NONE
#define __P001	PAGE_READONLY
#define __P010	PAGE_COPY
#define __P011	PAGE_COPY
#define __P100	PAGE_READONLY_EXEC
#define __P101	PAGE_READONLY_EXEC
#define __P110	PAGE_COPY_EXEC
#define __P111	PAGE_COPY_EXEC

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED
#define __S100	PAGE_READONLY_EXEC
#define __S101	PAGE_READONLY_EXEC
#define __S110	PAGE_SHARED_EXEC
#define __S111	PAGE_SHARED_EXEC

/*
 * early identity mapping  pte attrib macros.
 */
#ifdef CONFIG_X86_64
#define __PAGE_KERNEL_IDENT_LARGE_EXEC	__PAGE_KERNEL_LARGE_EXEC
#else
#define PTE_IDENT_ATTR	 0x003		/* PRESENT+RW */
#define PDE_IDENT_ATTR	 0x063		/* PRESENT+RW+DIRTY+ACCESSED */
#define PGD_IDENT_ATTR	 0x001		/* PRESENT (no other attributes) */
#endif

#ifdef CONFIG_X86_32
# include <asm/pgtable_32_types.h>
#else
# include <asm/pgtable_64_types.h>
#endif

#ifndef __ASSEMBLY__

#include <linux/types.h>

/* Extracts the PFN from a (pte|pmd|pud|pgd)val_t of a 4KB page */
#define PTE_PFN_MASK		((pteval_t)PHYSICAL_PAGE_MASK)

/*
 *  Extracts the flags from a (pte|pmd|pud|pgd)val_t
 *  This includes the protection key value.
 */
#define PTE_FLAGS_MASK		(~PTE_PFN_MASK)

typedef struct pgprot { pgprotval_t pgprot; } pgprot_t;

typedef struct { pgdval_t pgd; } pgd_t;

static inline pgd_t native_make_pgd(pgdval_t val)
{
	return (pgd_t) { val };
}

static inline pgdval_t native_pgd_val(pgd_t pgd)
{
	return pgd.pgd;
}

static inline pgdval_t pgd_flags(pgd_t pgd)
{
	return native_pgd_val(pgd) & PTE_FLAGS_MASK;
}

#if CONFIG_PGTABLE_LEVELS > 4
typedef struct { p4dval_t p4d; } p4d_t;

static inline p4d_t native_make_p4d(pudval_t val)
{
	return (p4d_t) { val };
}

static inline p4dval_t native_p4d_val(p4d_t p4d)
{
	return p4d.p4d;
}
#else
#include <asm-generic/pgtable-nop4d.h>

static inline p4d_t native_make_p4d(pudval_t val)
{
	return (p4d_t) { .pgd = native_make_pgd((pgdval_t)val) };
}

static inline p4dval_t native_p4d_val(p4d_t p4d)
{
	return native_pgd_val(p4d.pgd);
}
#endif

#if CONFIG_PGTABLE_LEVELS > 3
typedef struct { pudval_t pud; } pud_t;

static inline pud_t native_make_pud(pmdval_t val)
{
	return (pud_t) { val };
}

static inline pudval_t native_pud_val(pud_t pud)
{
	return pud.pud;
}
#else
#include <asm-generic/pgtable-nopud.h>

static inline pud_t native_make_pud(pudval_t val)
{
	return (pud_t) { .p4d.pgd = native_make_pgd(val) };
}

static inline pudval_t native_pud_val(pud_t pud)
{
	return native_pgd_val(pud.p4d.pgd);
}
#endif

#if CONFIG_PGTABLE_LEVELS > 2
typedef struct { pmdval_t pmd; } pmd_t;

static inline pmd_t native_make_pmd(pmdval_t val)
{
	return (pmd_t) { val };
}

static inline pmdval_t native_pmd_val(pmd_t pmd)
{
	return pmd.pmd;
}
#else
#include <asm-generic/pgtable-nopmd.h>

static inline pmd_t native_make_pmd(pmdval_t val)
{
	return (pmd_t) { .pud.p4d.pgd = native_make_pgd(val) };
}

static inline pmdval_t native_pmd_val(pmd_t pmd)
{
	return native_pgd_val(pmd.pud.p4d.pgd);
}
#endif

static inline p4dval_t p4d_pfn_mask(p4d_t p4d)
{
	/* No 512 GiB huge pages yet */
	return PTE_PFN_MASK;
}

static inline p4dval_t p4d_flags_mask(p4d_t p4d)
{
	return ~p4d_pfn_mask(p4d);
}

static inline p4dval_t p4d_flags(p4d_t p4d)
{
	return native_p4d_val(p4d) & p4d_flags_mask(p4d);
}

static inline pudval_t pud_pfn_mask(pud_t pud)
{
	if (native_pud_val(pud) & _PAGE_PSE)
		return PHYSICAL_PUD_PAGE_MASK;
	else
		return PTE_PFN_MASK;
}

static inline pudval_t pud_flags_mask(pud_t pud)
{
	return ~pud_pfn_mask(pud);
}

static inline pudval_t pud_flags(pud_t pud)
{
	return native_pud_val(pud) & pud_flags_mask(pud);
}

static inline pmdval_t pmd_pfn_mask(pmd_t pmd)
{
	if (native_pmd_val(pmd) & _PAGE_PSE)
		return PHYSICAL_PMD_PAGE_MASK;
	else
		return PTE_PFN_MASK;
}

static inline pmdval_t pmd_flags_mask(pmd_t pmd)
{
	return ~pmd_pfn_mask(pmd);
}

static inline pmdval_t pmd_flags(pmd_t pmd)
{
	return native_pmd_val(pmd) & pmd_flags_mask(pmd);
}

static inline pte_t native_make_pte(pteval_t val)
{
	return (pte_t) { .pte = val };
}

static inline pteval_t native_pte_val(pte_t pte)
{
	return pte.pte;
}

static inline pteval_t pte_flags(pte_t pte)
{
	return native_pte_val(pte) & PTE_FLAGS_MASK;
}

#define pgprot_val(x)	((x).pgprot)
#define __pgprot(x)	((pgprot_t) { (x) } )

extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
extern uint8_t __pte2cachemode_tbl[8];

#define __pte2cm_idx(cb)				\
	((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) |		\
	 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) |		\
	 (((cb) >> _PAGE_BIT_PWT) & 1))
#define __cm_idx2pte(i)					\
	((((i) & 4) << (_PAGE_BIT_PAT - 2)) |		\
	 (((i) & 2) << (_PAGE_BIT_PCD - 1)) |		\
	 (((i) & 1) << _PAGE_BIT_PWT))

static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
{
	if (likely(pcm == 0))
		return 0;
	return __cachemode2pte_tbl[pcm];
}
static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
{
	return __pgprot(cachemode2protval(pcm));
}
static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
{
	unsigned long masked;

	masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
	if (likely(masked == 0))
		return 0;
	return __pte2cachemode_tbl[__pte2cm_idx(masked)];
}
static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
{
	pgprotval_t val = pgprot_val(pgprot);
	pgprot_t new;

	pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
		((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
	return new;
}
static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
{
	pgprotval_t val = pgprot_val(pgprot);
	pgprot_t new;

	pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
			  ((val & _PAGE_PAT_LARGE) >>
			   (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
	return new;
}


typedef struct page *pgtable_t;

extern pteval_t __supported_pte_mask;
extern void set_nx(void);
extern int nx_enabled;

#define pgprot_writecombine	pgprot_writecombine
extern pgprot_t pgprot_writecombine(pgprot_t prot);

#define pgprot_writethrough	pgprot_writethrough
extern pgprot_t pgprot_writethrough(pgprot_t prot);

/* Indicate that x86 has its own track and untrack pfn vma functions */
#define __HAVE_PFNMAP_TRACKING

#define __HAVE_PHYS_MEM_ACCESS_PROT
struct file;
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
                              unsigned long size, pgprot_t vma_prot);

/* Install a pte for a particular vaddr in kernel space. */
void set_pte_vaddr(unsigned long vaddr, pte_t pte);

#ifdef CONFIG_X86_32
extern void native_pagetable_init(void);
#else
#define native_pagetable_init        paging_init
#endif

struct seq_file;
extern void arch_report_meminfo(struct seq_file *m);

enum pg_level {
	PG_LEVEL_NONE,
	PG_LEVEL_4K,
	PG_LEVEL_2M,
	PG_LEVEL_1G,
	PG_LEVEL_512G,
	PG_LEVEL_NUM
};

#ifdef CONFIG_PROC_FS
extern void update_page_count(int level, unsigned long pages);
#else
static inline void update_page_count(int level, unsigned long pages) { }
#endif

/*
 * Helper function that returns the kernel pagetable entry controlling
 * the virtual address 'address'. NULL means no pagetable entry present.
 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
 * as a pte too.
 */
extern pte_t *lookup_address(unsigned long address, unsigned int *level);
extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
				    unsigned int *level);
extern pmd_t *lookup_pmd_address(unsigned long address);
extern phys_addr_t slow_virt_to_phys(void *__address);
extern int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
				   unsigned numpages, unsigned long page_flags);
#endif	/* !__ASSEMBLY__ */

#endif /* _ASM_X86_PGTABLE_DEFS_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
8d19c99f JF	2	#ifndef _ASM_X86_PGTABLE_DEFS_H
	3	#define _ASM_X86_PGTABLE_DEFS_H
	4
	5	#include <linux/const.h>
21729f81 TL	6	#include <linux/mem_encrypt.h>
21729f81 TL	7
e43623b4	8	#include <asm/page_types.h>
8d19c99f	9
d016bf7e	10	#define FIRST_USER_ADDRESS 0UL
8d19c99f JF	11
	12	#define _PAGE_BIT_PRESENT 0 /* is present */
	13	#define _PAGE_BIT_RW 1 /* writeable */
	14	#define _PAGE_BIT_USER 2 /* userspace addressable */
	15	#define _PAGE_BIT_PWT 3 /* page write through */
	16	#define _PAGE_BIT_PCD 4 /* page cache disabled */
	17	#define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */
	18	#define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */
	19	#define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
	20	#define _PAGE_BIT_PAT 7 /* on 4KB pages */
	21	#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
c46a7c81 MG	22	#define _PAGE_BIT_SOFTW1 9 /* available for programmer */
	23	#define _PAGE_BIT_SOFTW2 10 /* " */
	24	#define _PAGE_BIT_SOFTW3 11 /* " */
8d19c99f	25	#define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
5c1d90f5 DH	26	#define _PAGE_BIT_SOFTW4 58 /* available for programmer */
	27	#define _PAGE_BIT_PKEY_BIT0 59 /* Protection Keys, bit 1/4 */
	28	#define _PAGE_BIT_PKEY_BIT1 60 /* Protection Keys, bit 2/4 */
	29	#define _PAGE_BIT_PKEY_BIT2 61 /* Protection Keys, bit 3/4 */
	30	#define _PAGE_BIT_PKEY_BIT3 62 /* Protection Keys, bit 4/4 */
	31	#define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
	32
c46a7c81 MG	33	#define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1
c46a7c81 MG	34	#define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1
c46a7c81	35	#define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */
5c1d90f5	36	#define _PAGE_BIT_DEVMAP _PAGE_BIT_SOFTW4
8d19c99f JF	37
	38	/* If _PAGE_BIT_PRESENT is clear, we use these: */
	39	/* - if the user mapped it with PROT_NONE; pte_present gives true */
	40	#define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL
8d19c99f JF	41
	42	#define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
	43	#define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW)
	44	#define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER)
	45	#define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT)
	46	#define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD)
	47	#define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
	48	#define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
	49	#define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
	50	#define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
c46a7c81	51	#define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1)
f955371c	52	#define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2)
8d19c99f JF	53	#define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
	54	#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
	55	#define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
	56	#define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
5c1d90f5 DH	57	#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
	58	#define _PAGE_PKEY_BIT0 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT0)
	59	#define _PAGE_PKEY_BIT1 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT1)
	60	#define _PAGE_PKEY_BIT2 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT2)
	61	#define _PAGE_PKEY_BIT3 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT3)
	62	#else
	63	#define _PAGE_PKEY_BIT0 (_AT(pteval_t, 0))
	64	#define _PAGE_PKEY_BIT1 (_AT(pteval_t, 0))
	65	#define _PAGE_PKEY_BIT2 (_AT(pteval_t, 0))
	66	#define _PAGE_PKEY_BIT3 (_AT(pteval_t, 0))
	67	#endif
8d19c99f JF	68	#define __HAVE_ARCH_PTE_SPECIAL
8d19c99f JF	69
019132ff DH	70	#define _PAGE_PKEY_MASK (_PAGE_PKEY_BIT0 \| \
	71	_PAGE_PKEY_BIT1 \| \
	72	_PAGE_PKEY_BIT2 \| \
	73	_PAGE_PKEY_BIT3)
	74
97e3c602 DH	75	#if defined(CONFIG_X86_64) \|\| defined(CONFIG_X86_PAE)
	76	#define _PAGE_KNL_ERRATUM_MASK (_PAGE_DIRTY \| _PAGE_ACCESSED)
	77	#else
	78	#define _PAGE_KNL_ERRATUM_MASK 0
	79	#endif
	80
0f8975ec	81	#ifdef CONFIG_MEM_SOFT_DIRTY
41bb3476	82	#define _PAGE_SOFT_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY)
0f8975ec PE	83	#else
	84	#define _PAGE_SOFT_DIRTY (_AT(pteval_t, 0))
	85	#endif
	86
179ef71c CG	87	/*
	88	* Tracking soft dirty bit when a page goes to a swap is tricky.
	89	* We need a bit which can be stored in pte _and_ not conflict
eee4818b NH	90	* with swap entry format. On x86 bits 1-4 are not involved
	91	* into swap entry computation, but bit 7 is used for thp migration,
	92	* so we borrow bit 1 for soft dirty tracking.
fa0f281c CG	93	*
fa0f281c CG	94	* Please note that this bit must be treated as swap dirty page
eee4818b	95	* mark if and only if the PTE/PMD has present bit clear!
179ef71c CG	96	*/
179ef71c CG	97	#ifdef CONFIG_MEM_SOFT_DIRTY
eee4818b	98	#define _PAGE_SWP_SOFT_DIRTY _PAGE_RW
179ef71c CG	99	#else
	100	#define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0))
	101	#endif
	102
8d19c99f JF	103	#if defined(CONFIG_X86_64) \|\| defined(CONFIG_X86_PAE)
8d19c99f JF	104	#define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
69660fd7 DW	105	#define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP)
69660fd7 DW	106	#define __HAVE_ARCH_PTE_DEVMAP
8d19c99f JF	107	#else
8d19c99f JF	108	#define _PAGE_NX (_AT(pteval_t, 0))
69660fd7	109	#define _PAGE_DEVMAP (_AT(pteval_t, 0))
8d19c99f JF	110	#endif
8d19c99f JF	111
8d19c99f JF	112	#define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
8d19c99f JF	113
21729f81 TL	114	#define _PAGE_TABLE_NOENC (_PAGE_PRESENT \| _PAGE_RW \| _PAGE_USER \|\
	115	_PAGE_ACCESSED \| _PAGE_DIRTY)
	116	#define _KERNPG_TABLE_NOENC (_PAGE_PRESENT \| _PAGE_RW \| \
	117	_PAGE_ACCESSED \| _PAGE_DIRTY)
8d19c99f	118
8f62c883 DH	119	/*
	120	* Set of bits not changed in pte_modify. The pte's
	121	* protection key is treated like _PAGE_RW, for
	122	* instance, and is not included in this mask since
	123	* pte_modify() does modify it.
	124	*/
8d19c99f	125	#define _PAGE_CHG_MASK (PTE_PFN_MASK \| _PAGE_PCD \| _PAGE_PWT \| \
24f91eba	126	_PAGE_SPECIAL \| _PAGE_ACCESSED \| _PAGE_DIRTY \| \
21d9ee3e MG	127	_PAGE_SOFT_DIRTY)
21d9ee3e MG	128	#define _HPAGE_CHG_MASK (_PAGE_CHG_MASK \| _PAGE_PSE)
8d19c99f	129
281d4078 JG	130	/*
	131	* The cache modes defined here are used to translate between pure SW usage
	132	* and the HW defined cache mode bits and/or PAT entries.
	133	*
	134	* The resulting bits for PWT, PCD and PAT should be chosen in a way
	135	* to have the WB mode at index 0 (all bits clear). This is the default
	136	* right now and likely would break too much if changed.
	137	*/
	138	#ifndef __ASSEMBLY__
	139	enum page_cache_mode {
	140	_PAGE_CACHE_MODE_WB = 0,
	141	_PAGE_CACHE_MODE_WC = 1,
	142	_PAGE_CACHE_MODE_UC_MINUS = 2,
	143	_PAGE_CACHE_MODE_UC = 3,
	144	_PAGE_CACHE_MODE_WT = 4,
	145	_PAGE_CACHE_MODE_WP = 5,
	146	_PAGE_CACHE_MODE_NUM = 8
	147	};
	148	#endif
	149
	150	#define _PAGE_CACHE_MASK (_PAGE_PAT \| _PAGE_PCD \| _PAGE_PWT)
	151	#define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC))
f88a68fa	152	#define _PAGE_CACHE_WP (cachemode2protval(_PAGE_CACHE_MODE_WP))
281d4078	153
8d19c99f JF	154	#define PAGE_NONE __pgprot(_PAGE_PROTNONE \| _PAGE_ACCESSED)
	155	#define PAGE_SHARED __pgprot(_PAGE_PRESENT \| _PAGE_RW \| _PAGE_USER \| \
	156	_PAGE_ACCESSED \| _PAGE_NX)
	157
	158	#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_RW \| \
	159	_PAGE_USER \| _PAGE_ACCESSED)
	160	#define PAGE_COPY_NOEXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| \
	161	_PAGE_ACCESSED \| _PAGE_NX)
	162	#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| \
	163	_PAGE_ACCESSED)
	164	#define PAGE_COPY PAGE_COPY_NOEXEC
	165	#define PAGE_READONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER \| \
	166	_PAGE_ACCESSED \| _PAGE_NX)
	167	#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| \
	168	_PAGE_ACCESSED)
	169
	170	#define __PAGE_KERNEL_EXEC \
	171	(_PAGE_PRESENT \| _PAGE_RW \| _PAGE_DIRTY \| _PAGE_ACCESSED \| _PAGE_GLOBAL)
	172	#define __PAGE_KERNEL (__PAGE_KERNEL_EXEC \| _PAGE_NX)
	173
	174	#define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
	175	#define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
87ad0b71	176	#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL \| _PAGE_NOCACHE)
8d19c99f	177	#define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX \| _PAGE_USER)
9fd67b4e	178	#define __PAGE_KERNEL_VVAR (__PAGE_KERNEL_RO \| _PAGE_USER)
8d19c99f	179	#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL \| _PAGE_PSE)
8d19c99f	180	#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC \| _PAGE_PSE)
f88a68fa	181	#define __PAGE_KERNEL_WP (__PAGE_KERNEL \| _PAGE_CACHE_WP)
8d19c99f	182
f955371c DV	183	#define __PAGE_KERNEL_IO (__PAGE_KERNEL)
f955371c DV	184	#define __PAGE_KERNEL_IO_NOCACHE (__PAGE_KERNEL_NOCACHE)
8d19c99f	185
21729f81 TL	186	#ifndef __ASSEMBLY__
	187
	188	#define _PAGE_ENC (_AT(pteval_t, sme_me_mask))
	189
21729f81 TL	190	#define _KERNPG_TABLE (_PAGE_PRESENT \| _PAGE_RW \| _PAGE_ACCESSED \| \
21729f81 TL	191	_PAGE_DIRTY \| _PAGE_ENC)
c7da092a	192	#define _PAGE_TABLE (_KERNPG_TABLE \| _PAGE_USER)
21729f81	193
f88a68fa TL	194	#define __PAGE_KERNEL_ENC (__PAGE_KERNEL \| _PAGE_ENC)
	195	#define __PAGE_KERNEL_ENC_WP (__PAGE_KERNEL_WP \| _PAGE_ENC)
	196
	197	#define __PAGE_KERNEL_NOENC (__PAGE_KERNEL)
	198	#define __PAGE_KERNEL_NOENC_WP (__PAGE_KERNEL_WP)
	199
21729f81	200	#define PAGE_KERNEL __pgprot(__PAGE_KERNEL \| _PAGE_ENC)
57bd1905	201	#define PAGE_KERNEL_NOENC __pgprot(__PAGE_KERNEL)
21729f81 TL	202	#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO \| _PAGE_ENC)
21729f81 TL	203	#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC \| _PAGE_ENC)
bba4ed01	204	#define PAGE_KERNEL_EXEC_NOENC __pgprot(__PAGE_KERNEL_EXEC)
21729f81 TL	205	#define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX \| _PAGE_ENC)
	206	#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE \| _PAGE_ENC)
	207	#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE \| _PAGE_ENC)
	208	#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC \| _PAGE_ENC)
	209	#define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL \| _PAGE_ENC)
	210	#define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR \| _PAGE_ENC)
	211
	212	#define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO)
	213	#define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE)
	214
	215	#endif /* __ASSEMBLY__ */
8d19c99f JF	216
	217	/* xwr */
	218	#define __P000 PAGE_NONE
	219	#define __P001 PAGE_READONLY
	220	#define __P010 PAGE_COPY
	221	#define __P011 PAGE_COPY
	222	#define __P100 PAGE_READONLY_EXEC
	223	#define __P101 PAGE_READONLY_EXEC
	224	#define __P110 PAGE_COPY_EXEC
	225	#define __P111 PAGE_COPY_EXEC
	226
	227	#define __S000 PAGE_NONE
	228	#define __S001 PAGE_READONLY
	229	#define __S010 PAGE_SHARED
	230	#define __S011 PAGE_SHARED
	231	#define __S100 PAGE_READONLY_EXEC
	232	#define __S101 PAGE_READONLY_EXEC
	233	#define __S110 PAGE_SHARED_EXEC
	234	#define __S111 PAGE_SHARED_EXEC
	235
	236	/*
	237	* early identity mapping pte attrib macros.
	238	*/
	239	#ifdef CONFIG_X86_64
	240	#define __PAGE_KERNEL_IDENT_LARGE_EXEC __PAGE_KERNEL_LARGE_EXEC
	241	#else
8d19c99f	242	#define PTE_IDENT_ATTR 0x003 /* PRESENT+RW */
7dda0387	243	#define PDE_IDENT_ATTR 0x063 /* PRESENT+RW+DIRTY+ACCESSED */
8d19c99f JF	244	#define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */
	245	#endif
	246
54321d94	247	#ifdef CONFIG_X86_32
a1ce3928	248	# include <asm/pgtable_32_types.h>
54321d94	249	#else
a1ce3928	250	# include <asm/pgtable_64_types.h>
54321d94 JF	251	#endif
54321d94 JF	252
8d19c99f JF	253	#ifndef __ASSEMBLY__
8d19c99f JF	254
54321d94 JF	255	#include <linux/types.h>
54321d94 JF	256
4be4c1fb	257	/* Extracts the PFN from a (pte\|pmd\|pud\|pgd)val_t of a 4KB page */
9b3651cb JF	258	#define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK)
9b3651cb JF	259
8f62c883 DH	260	/*
	261	* Extracts the flags from a (pte\|pmd\|pud\|pgd)val_t
	262	* This includes the protection key value.
	263	*/
9b3651cb JF	264	#define PTE_FLAGS_MASK (~PTE_PFN_MASK)
9b3651cb JF	265
54321d94 JF	266	typedef struct pgprot { pgprotval_t pgprot; } pgprot_t;
	267
	268	typedef struct { pgdval_t pgd; } pgd_t;
	269
	270	static inline pgd_t native_make_pgd(pgdval_t val)
	271	{
	272	return (pgd_t) { val };
	273	}
	274
	275	static inline pgdval_t native_pgd_val(pgd_t pgd)
	276	{
	277	return pgd.pgd;
	278	}
	279
	280	static inline pgdval_t pgd_flags(pgd_t pgd)
	281	{
	282	return native_pgd_val(pgd) & PTE_FLAGS_MASK;
	283	}
	284
fe1e8c3e	285	#if CONFIG_PGTABLE_LEVELS > 4
b8504058	286	typedef struct { p4dval_t p4d; } p4d_t;
fe1e8c3e	287
b8504058 KS	288	static inline p4d_t native_make_p4d(pudval_t val)
	289	{
	290	return (p4d_t) { val };
	291	}
fe1e8c3e	292
b8504058 KS	293	static inline p4dval_t native_p4d_val(p4d_t p4d)
	294	{
	295	return p4d.p4d;
	296	}
fe1e8c3e	297	#else
f2a6a705	298	#include <asm-generic/pgtable-nop4d.h>
9849a569	299
db516997 TL	300	static inline p4d_t native_make_p4d(pudval_t val)
	301	{
	302	return (p4d_t) { .pgd = native_make_pgd((pgdval_t)val) };
	303	}
	304
fe1e8c3e KS	305	static inline p4dval_t native_p4d_val(p4d_t p4d)
fe1e8c3e KS	306	{
f2a6a705	307	return native_pgd_val(p4d.pgd);
fe1e8c3e KS	308	}
	309	#endif
	310
	311	#if CONFIG_PGTABLE_LEVELS > 3
54321d94 JF	312	typedef struct { pudval_t pud; } pud_t;
	313
	314	static inline pud_t native_make_pud(pmdval_t val)
	315	{
	316	return (pud_t) { val };
	317	}
	318
	319	static inline pudval_t native_pud_val(pud_t pud)
	320	{
	321	return pud.pud;
	322	}
	323	#else
	324	#include <asm-generic/pgtable-nopud.h>
	325
bc511804 JB	326	static inline pud_t native_make_pud(pudval_t val)
	327	{
	328	return (pud_t) { .p4d.pgd = native_make_pgd(val) };
	329	}
	330
54321d94 JF	331	static inline pudval_t native_pud_val(pud_t pud)
54321d94 JF	332	{
f2a6a705	333	return native_pgd_val(pud.p4d.pgd);
54321d94 JF	334	}
	335	#endif
	336
98233368	337	#if CONFIG_PGTABLE_LEVELS > 2
54321d94 JF	338	typedef struct { pmdval_t pmd; } pmd_t;
	339
	340	static inline pmd_t native_make_pmd(pmdval_t val)
	341	{
	342	return (pmd_t) { val };
	343	}
	344
	345	static inline pmdval_t native_pmd_val(pmd_t pmd)
	346	{
	347	return pmd.pmd;
	348	}
	349	#else
	350	#include <asm-generic/pgtable-nopmd.h>
	351
bc511804 JB	352	static inline pmd_t native_make_pmd(pmdval_t val)
	353	{
	354	return (pmd_t) { .pud.p4d.pgd = native_make_pgd(val) };
	355	}
	356
54321d94 JF	357	static inline pmdval_t native_pmd_val(pmd_t pmd)
54321d94 JF	358	{
f2a6a705	359	return native_pgd_val(pmd.pud.p4d.pgd);
54321d94 JF	360	}
	361	#endif
	362
fe1e8c3e KS	363	static inline p4dval_t p4d_pfn_mask(p4d_t p4d)
	364	{
	365	/* No 512 GiB huge pages yet */
	366	return PTE_PFN_MASK;
	367	}
	368
	369	static inline p4dval_t p4d_flags_mask(p4d_t p4d)
	370	{
	371	return ~p4d_pfn_mask(p4d);
	372	}
	373
	374	static inline p4dval_t p4d_flags(p4d_t p4d)
	375	{
	376	return native_p4d_val(p4d) & p4d_flags_mask(p4d);
	377	}
	378
4be4c1fb TK	379	static inline pudval_t pud_pfn_mask(pud_t pud)
	380	{
	381	if (native_pud_val(pud) & _PAGE_PSE)
70f15287	382	return PHYSICAL_PUD_PAGE_MASK;
4be4c1fb TK	383	else
	384	return PTE_PFN_MASK;
	385	}
	386
	387	static inline pudval_t pud_flags_mask(pud_t pud)
	388	{
70f15287	389	return ~pud_pfn_mask(pud);
4be4c1fb TK	390	}
4be4c1fb TK	391
54321d94 JF	392	static inline pudval_t pud_flags(pud_t pud)
54321d94 JF	393	{
f70abb0f	394	return native_pud_val(pud) & pud_flags_mask(pud);
54321d94 JF	395	}
54321d94 JF	396
4be4c1fb TK	397	static inline pmdval_t pmd_pfn_mask(pmd_t pmd)
	398	{
	399	if (native_pmd_val(pmd) & _PAGE_PSE)
70f15287	400	return PHYSICAL_PMD_PAGE_MASK;
4be4c1fb TK	401	else
	402	return PTE_PFN_MASK;
	403	}
	404
	405	static inline pmdval_t pmd_flags_mask(pmd_t pmd)
	406	{
70f15287	407	return ~pmd_pfn_mask(pmd);
4be4c1fb TK	408	}
4be4c1fb TK	409
54321d94 JF	410	static inline pmdval_t pmd_flags(pmd_t pmd)
54321d94 JF	411	{
f70abb0f	412	return native_pmd_val(pmd) & pmd_flags_mask(pmd);
54321d94 JF	413	}
	414
	415	static inline pte_t native_make_pte(pteval_t val)
	416	{
	417	return (pte_t) { .pte = val };
	418	}
	419
	420	static inline pteval_t native_pte_val(pte_t pte)
	421	{
	422	return pte.pte;
	423	}
	424
	425	static inline pteval_t pte_flags(pte_t pte)
	426	{
	427	return native_pte_val(pte) & PTE_FLAGS_MASK;
	428	}
	429
	430	#define pgprot_val(x) ((x).pgprot)
	431	#define __pgprot(x) ((pgprot_t) { (x) } )
	432
281d4078 JG	433	extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
	434	extern uint8_t __pte2cachemode_tbl[8];
	435
	436	#define __pte2cm_idx(cb) \
	437	((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) \| \
	438	(((cb) >> (_PAGE_BIT_PCD - 1)) & 2) \| \
	439	(((cb) >> _PAGE_BIT_PWT) & 1))
bd809af1 JG	440	#define __cm_idx2pte(i) \
	441	((((i) & 4) << (_PAGE_BIT_PAT - 2)) \| \
	442	(((i) & 2) << (_PAGE_BIT_PCD - 1)) \| \
	443	(((i) & 1) << _PAGE_BIT_PWT))
281d4078 JG	444
	445	static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
	446	{
	447	if (likely(pcm == 0))
	448	return 0;
	449	return __cachemode2pte_tbl[pcm];
	450	}
	451	static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
	452	{
	453	return __pgprot(cachemode2protval(pcm));
	454	}
	455	static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
	456	{
	457	unsigned long masked;
	458
	459	masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
	460	if (likely(masked == 0))
	461	return 0;
	462	return __pte2cachemode_tbl[__pte2cm_idx(masked)];
	463	}
	464	static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
	465	{
3625c2c2	466	pgprotval_t val = pgprot_val(pgprot);
281d4078	467	pgprot_t new;
281d4078	468
281d4078 JG	469	pgprot_val(new) = (val & ~(_PAGE_PAT \| _PAGE_PAT_LARGE)) \|
	470	((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
	471	return new;
	472	}
	473	static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
	474	{
3625c2c2	475	pgprotval_t val = pgprot_val(pgprot);
281d4078	476	pgprot_t new;
281d4078	477
281d4078 JG	478	pgprot_val(new) = (val & ~(_PAGE_PAT \| _PAGE_PAT_LARGE)) \|
	479	((val & _PAGE_PAT_LARGE) >>
	480	(_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
	481	return new;
	482	}
	483
54321d94 JF	484
	485	typedef struct page *pgtable_t;
	486
8d19c99f	487	extern pteval_t __supported_pte_mask;
c44c9ec0	488	extern void set_nx(void);
54321d94	489	extern int nx_enabled;
8d19c99f JF	490
	491	#define pgprot_writecombine pgprot_writecombine
	492	extern pgprot_t pgprot_writecombine(pgprot_t prot);
	493
d1b4bfbf TK	494	#define pgprot_writethrough pgprot_writethrough
	495	extern pgprot_t pgprot_writethrough(pgprot_t prot);
	496
8d19c99f JF	497	/* Indicate that x86 has its own track and untrack pfn vma functions */
	498	#define __HAVE_PFNMAP_TRACKING
	499
	500	#define __HAVE_PHYS_MEM_ACCESS_PROT
	501	struct file;
	502	pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
	503	unsigned long size, pgprot_t vma_prot);
8d19c99f JF	504
	505	/* Install a pte for a particular vaddr in kernel space. */
	506	void set_pte_vaddr(unsigned long vaddr, pte_t pte);
	507
	508	#ifdef CONFIG_X86_32
7737b215	509	extern void native_pagetable_init(void);
8d19c99f	510	#else
843b8ed2	511	#define native_pagetable_init paging_init
8d19c99f JF	512	#endif
	513
	514	struct seq_file;
	515	extern void arch_report_meminfo(struct seq_file *m);
	516
4cbeb51b	517	enum pg_level {
8d19c99f JF	518	PG_LEVEL_NONE,
	519	PG_LEVEL_4K,
	520	PG_LEVEL_2M,
	521	PG_LEVEL_1G,
fe1e8c3e	522	PG_LEVEL_512G,
8d19c99f JF	523	PG_LEVEL_NUM
	524	};
	525
	526	#ifdef CONFIG_PROC_FS
	527	extern void update_page_count(int level, unsigned long pages);
	528	#else
	529	static inline void update_page_count(int level, unsigned long pages) { }
	530	#endif
	531
	532	/*
	533	* Helper function that returns the kernel pagetable entry controlling
	534	* the virtual address 'address'. NULL means no pagetable entry present.
	535	* NOTE: the return type is pte_t but if the pmd is PSE then we return it
	536	* as a pte too.
	537	*/
	538	extern pte_t lookup_address(unsigned long address, unsigned int level);
426e34cc MF	539	extern pte_t lookup_address_in_pgd(pgd_t pgd, unsigned long address,
426e34cc MF	540	unsigned int *level);
792230c3	541	extern pmd_t *lookup_pmd_address(unsigned long address);
d7656534	542	extern phys_addr_t slow_virt_to_phys(void *__address);
d2f7cbe7 BP	543	extern int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
d2f7cbe7 BP	544	unsigned numpages, unsigned long page_flags);
8d19c99f JF	545	#endif /* !__ASSEMBLY__ */
	546
	547	#endif /* _ASM_X86_PGTABLE_DEFS_H */