[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / processor-flags.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_PROCESSOR_FLAGS_H
#define _ASM_X86_PROCESSOR_FLAGS_H

#include <uapi/asm/processor-flags.h>
#include <linux/mem_encrypt.h>

#ifdef CONFIG_VM86
#define X86_VM_MASK	X86_EFLAGS_VM
#else
#define X86_VM_MASK	0 /* No VM86 support */
#endif

/*
 * CR3's layout varies depending on several things.
 *
 * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID.
 * If PAE is enabled, then CR3[11:5] is part of the PDPT address
 * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored.
 * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and
 * CR3[2:0] and CR3[11:5] are ignored.
 *
 * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD.
 *
 * CR3[63] is always read as zero.  If CR4.PCIDE is set, then CR3[63] may be
 * written as 1 to prevent the write to CR3 from flushing the TLB.
 *
 * On systems with SME, one bit (in a variable position!) is stolen to indicate
 * that the top-level paging structure is encrypted.
 *
 * All of the remaining bits indicate the physical address of the top-level
 * paging structure.
 *
 * CR3_ADDR_MASK is the mask used by read_cr3_pa().
 */
#ifdef CONFIG_X86_64
/* Mask off the address space ID and SME encryption bits. */
#define CR3_ADDR_MASK	__sme_clr(0x7FFFFFFFFFFFF000ull)
#define CR3_PCID_MASK	0xFFFull
#define CR3_NOFLUSH	BIT_ULL(63)

#else
/*
 * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
 * a tiny bit of code size by setting all the bits.
 */
#define CR3_ADDR_MASK	0xFFFFFFFFull
#define CR3_PCID_MASK	0ull
#define CR3_NOFLUSH	0
#endif

#ifdef CONFIG_PAGE_TABLE_ISOLATION
# define X86_CR3_PTI_PCID_USER_BIT	11
#endif

#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_PROCESSOR_FLAGS_H
1965aae3 PA	3	#define _ASM_X86_PROCESSOR_FLAGS_H
b4531e86	4
af170c50	5	#include <uapi/asm/processor-flags.h>
eef9c4ab	6	#include <linux/mem_encrypt.h>
b4531e86	7
6330a30a VN	8	#ifdef CONFIG_VM86
	9	#define X86_VM_MASK X86_EFLAGS_VM
	10	#else
	11	#define X86_VM_MASK 0 /* No VM86 support */
	12	#endif
6c690ee1 AL	13
	14	/*
	15	* CR3's layout varies depending on several things.
	16	*
	17	* If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID.
	18	* If PAE is enabled, then CR3[11:5] is part of the PDPT address
	19	* (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored.
	20	* Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and
	21	* CR3[2:0] and CR3[11:5] are ignored.
	22	*
	23	* In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD.
	24	*
	25	* CR3[63] is always read as zero. If CR4.PCIDE is set, then CR3[63] may be
	26	* written as 1 to prevent the write to CR3 from flushing the TLB.
	27	*
	28	* On systems with SME, one bit (in a variable position!) is stolen to indicate
	29	* that the top-level paging structure is encrypted.
	30	*
	31	* All of the remaining bits indicate the physical address of the top-level
	32	* paging structure.
	33	*
	34	* CR3_ADDR_MASK is the mask used by read_cr3_pa().
	35	*/
	36	#ifdef CONFIG_X86_64
eef9c4ab	37	/* Mask off the address space ID and SME encryption bits. */
d6c8103b BP	38	#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
	39	#define CR3_PCID_MASK 0xFFFull
	40	#define CR3_NOFLUSH BIT_ULL(63)
6fd166aa	41
6c690ee1 AL	42	#else
	43	/*
	44	* CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
	45	* a tiny bit of code size by setting all the bits.
	46	*/
d6c8103b BP	47	#define CR3_ADDR_MASK 0xFFFFFFFFull
	48	#define CR3_PCID_MASK 0ull
	49	#define CR3_NOFLUSH 0
6c690ee1 AL	50	#endif
6c690ee1 AL	51
45936c77 JR	52	#ifdef CONFIG_PAGE_TABLE_ISOLATION
	53	# define X86_CR3_PTI_PCID_USER_BIT 11
	54	#endif
	55
1965aae3	56	#endif /* _ASM_X86_PROCESSOR_FLAGS_H */