]>
Commit | Line | Data |
---|---|---|
1965aae3 PA |
1 | #ifndef _ASM_X86_PROCESSOR_H |
2 | #define _ASM_X86_PROCESSOR_H | |
c758ecf6 | 3 | |
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
683e0253 GOC |
6 | /* Forward declaration, a strange C thing */ |
7 | struct task_struct; | |
8 | struct mm_struct; | |
9 | ||
2f66dcc9 GOC |
10 | #include <asm/vm86.h> |
11 | #include <asm/math_emu.h> | |
12 | #include <asm/segment.h> | |
2f66dcc9 GOC |
13 | #include <asm/types.h> |
14 | #include <asm/sigcontext.h> | |
15 | #include <asm/current.h> | |
16 | #include <asm/cpufeature.h> | |
2f66dcc9 | 17 | #include <asm/page.h> |
54321d94 | 18 | #include <asm/pgtable_types.h> |
5300db88 | 19 | #include <asm/percpu.h> |
2f66dcc9 GOC |
20 | #include <asm/msr.h> |
21 | #include <asm/desc_defs.h> | |
bd61643e | 22 | #include <asm/nops.h> |
f05e798a | 23 | #include <asm/special_insns.h> |
4d46a89e | 24 | |
2f66dcc9 | 25 | #include <linux/personality.h> |
5300db88 GOC |
26 | #include <linux/cpumask.h> |
27 | #include <linux/cache.h> | |
2f66dcc9 | 28 | #include <linux/threads.h> |
5cbc19a9 | 29 | #include <linux/math64.h> |
faa4602e | 30 | #include <linux/err.h> |
f05e798a DH |
31 | #include <linux/irqflags.h> |
32 | ||
33 | /* | |
34 | * We handle most unaligned accesses in hardware. On the other hand | |
35 | * unaligned DMA can be quite expensive on some Nehalem processors. | |
36 | * | |
37 | * Based on this we disable the IP header alignment in network drivers. | |
38 | */ | |
39 | #define NET_IP_ALIGN 0 | |
c72dcf83 | 40 | |
b332828c | 41 | #define HBP_NUM 4 |
0ccb8acc GOC |
42 | /* |
43 | * Default implementation of macro that returns current | |
44 | * instruction pointer ("program counter"). | |
45 | */ | |
46 | static inline void *current_text_addr(void) | |
47 | { | |
48 | void *pc; | |
4d46a89e IM |
49 | |
50 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
51 | ||
0ccb8acc GOC |
52 | return pc; |
53 | } | |
54 | ||
dbcb4660 | 55 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
56 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
57 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 58 | #else |
4d46a89e IM |
59 | # define ARCH_MIN_TASKALIGN 16 |
60 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 | |
dbcb4660 GOC |
61 | #endif |
62 | ||
e0ba94f1 AS |
63 | enum tlb_infos { |
64 | ENTRIES, | |
65 | NR_INFO | |
66 | }; | |
67 | ||
68 | extern u16 __read_mostly tlb_lli_4k[NR_INFO]; | |
69 | extern u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
70 | extern u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
71 | extern u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
72 | extern u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
73 | extern u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 74 | extern u16 __read_mostly tlb_lld_1g[NR_INFO]; |
c4211f42 | 75 | |
5300db88 GOC |
76 | /* |
77 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
78 | * Members of this structure are referenced in head.S, so think twice | |
79 | * before touching them. [mj] | |
80 | */ | |
81 | ||
82 | struct cpuinfo_x86 { | |
4d46a89e IM |
83 | __u8 x86; /* CPU family */ |
84 | __u8 x86_vendor; /* CPU vendor */ | |
85 | __u8 x86_model; | |
86 | __u8 x86_mask; | |
5300db88 | 87 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
88 | char wp_works_ok; /* It doesn't on 386's */ |
89 | ||
90 | /* Problems on some 486Dx4's and old 386's: */ | |
4d46a89e | 91 | char rfu; |
4d46a89e | 92 | char pad0; |
60e019eb | 93 | char pad1; |
5300db88 | 94 | #else |
4d46a89e | 95 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
b1882e68 | 96 | int x86_tlbsize; |
13c6c532 | 97 | #endif |
4d46a89e IM |
98 | __u8 x86_virt_bits; |
99 | __u8 x86_phys_bits; | |
100 | /* CPUID returned core id bits: */ | |
101 | __u8 x86_coreid_bits; | |
102 | /* Max extended CPUID function supported: */ | |
103 | __u32 extended_cpuid_level; | |
4d46a89e IM |
104 | /* Maximum supported CPUID level, -1=no CPUID: */ |
105 | int cpuid_level; | |
65fc985b | 106 | __u32 x86_capability[NCAPINTS + NBUGINTS]; |
4d46a89e IM |
107 | char x86_vendor_id[16]; |
108 | char x86_model_id[64]; | |
109 | /* in KB - valid for CPUS which support this call: */ | |
110 | int x86_cache_size; | |
111 | int x86_cache_alignment; /* In bytes */ | |
112 | int x86_power; | |
113 | unsigned long loops_per_jiffy; | |
4d46a89e IM |
114 | /* cpuid returned max cores value: */ |
115 | u16 x86_max_cores; | |
116 | u16 apicid; | |
01aaea1a | 117 | u16 initial_apicid; |
4d46a89e | 118 | u16 x86_clflush_size; |
4d46a89e IM |
119 | /* number of cores as seen by the OS: */ |
120 | u16 booted_cores; | |
121 | /* Physical processor id: */ | |
122 | u16 phys_proc_id; | |
123 | /* Core id: */ | |
124 | u16 cpu_core_id; | |
6057b4d3 AH |
125 | /* Compute unit id */ |
126 | u8 compute_unit_id; | |
4d46a89e IM |
127 | /* Index into per_cpu list: */ |
128 | u16 cpu_index; | |
506ed6b5 | 129 | u32 microcode; |
2c773dd3 | 130 | }; |
5300db88 | 131 | |
4d46a89e IM |
132 | #define X86_VENDOR_INTEL 0 |
133 | #define X86_VENDOR_CYRIX 1 | |
134 | #define X86_VENDOR_AMD 2 | |
135 | #define X86_VENDOR_UMC 3 | |
4d46a89e IM |
136 | #define X86_VENDOR_CENTAUR 5 |
137 | #define X86_VENDOR_TRANSMETA 7 | |
138 | #define X86_VENDOR_NSC 8 | |
139 | #define X86_VENDOR_NUM 9 | |
140 | ||
141 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 142 | |
1a53905a GOC |
143 | /* |
144 | * capabilities of CPUs | |
145 | */ | |
4d46a89e IM |
146 | extern struct cpuinfo_x86 boot_cpu_data; |
147 | extern struct cpuinfo_x86 new_cpu_data; | |
148 | ||
149 | extern struct tss_struct doublefault_tss; | |
3e0c3737 YL |
150 | extern __u32 cpu_caps_cleared[NCAPINTS]; |
151 | extern __u32 cpu_caps_set[NCAPINTS]; | |
5300db88 GOC |
152 | |
153 | #ifdef CONFIG_SMP | |
2c773dd3 | 154 | DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
5300db88 | 155 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) |
5300db88 | 156 | #else |
7b543a53 | 157 | #define cpu_info boot_cpu_data |
5300db88 | 158 | #define cpu_data(cpu) boot_cpu_data |
5300db88 GOC |
159 | #endif |
160 | ||
1c6c727d JS |
161 | extern const struct seq_operations cpuinfo_op; |
162 | ||
4d46a89e IM |
163 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
164 | ||
165 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
148f9bb8 | 166 | extern void fpu_detect(struct cpuinfo_x86 *c); |
1a53905a | 167 | |
f580366f | 168 | extern void early_cpu_init(void); |
1a53905a GOC |
169 | extern void identify_boot_cpu(void); |
170 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 | 171 | extern void print_cpu_info(struct cpuinfo_x86 *); |
21c3fcf3 | 172 | void print_cpu_msr(struct cpuinfo_x86 *); |
5300db88 GOC |
173 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
174 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
04a15418 | 175 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
5300db88 | 176 | |
bbb65d2d | 177 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
1a53905a | 178 | extern void detect_ht(struct cpuinfo_x86 *c); |
1a53905a | 179 | |
d288e1cf FY |
180 | #ifdef CONFIG_X86_32 |
181 | extern int have_cpuid_p(void); | |
182 | #else | |
183 | static inline int have_cpuid_p(void) | |
184 | { | |
185 | return 1; | |
186 | } | |
187 | #endif | |
c758ecf6 | 188 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 189 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
190 | { |
191 | /* ecx is often an input as well as an output. */ | |
45a94d7c | 192 | asm volatile("cpuid" |
cca2e6f8 JP |
193 | : "=a" (*eax), |
194 | "=b" (*ebx), | |
195 | "=c" (*ecx), | |
196 | "=d" (*edx) | |
506ed6b5 AK |
197 | : "0" (*eax), "2" (*ecx) |
198 | : "memory"); | |
c758ecf6 GOC |
199 | } |
200 | ||
c72dcf83 GOC |
201 | static inline void load_cr3(pgd_t *pgdir) |
202 | { | |
203 | write_cr3(__pa(pgdir)); | |
204 | } | |
c758ecf6 | 205 | |
ca241c75 GOC |
206 | #ifdef CONFIG_X86_32 |
207 | /* This is the TSS defined by the hardware. */ | |
208 | struct x86_hw_tss { | |
4d46a89e IM |
209 | unsigned short back_link, __blh; |
210 | unsigned long sp0; | |
211 | unsigned short ss0, __ss0h; | |
76e4c490 AL |
212 | |
213 | /* | |
214 | * We don't use ring 1, so sp1 and ss1 are convenient scratch | |
215 | * spaces in the same cacheline as sp0. We use them to cache | |
216 | * some MSR values to avoid unnecessary wrmsr instructions. | |
217 | * | |
218 | * We use SYSENTER_ESP to find sp0 and for the NMI emergency | |
219 | * stack, but we need to context switch it because we do | |
220 | * horrible things to the kernel stack in vm86 mode. | |
221 | * | |
222 | * We use SYSENTER_CS to disable sysenter in vm86 mode to avoid | |
223 | * corrupting the stack if we went through the sysenter path | |
224 | * from vm86 mode. | |
225 | */ | |
226 | unsigned long sp1; /* MSR_IA32_SYSENTER_ESP */ | |
227 | unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ | |
228 | ||
229 | unsigned short __ss1h; | |
4d46a89e IM |
230 | unsigned long sp2; |
231 | unsigned short ss2, __ss2h; | |
232 | unsigned long __cr3; | |
233 | unsigned long ip; | |
234 | unsigned long flags; | |
235 | unsigned long ax; | |
236 | unsigned long cx; | |
237 | unsigned long dx; | |
238 | unsigned long bx; | |
239 | unsigned long sp; | |
240 | unsigned long bp; | |
241 | unsigned long si; | |
242 | unsigned long di; | |
243 | unsigned short es, __esh; | |
244 | unsigned short cs, __csh; | |
245 | unsigned short ss, __ssh; | |
246 | unsigned short ds, __dsh; | |
247 | unsigned short fs, __fsh; | |
248 | unsigned short gs, __gsh; | |
249 | unsigned short ldt, __ldth; | |
250 | unsigned short trace; | |
251 | unsigned short io_bitmap_base; | |
252 | ||
ca241c75 GOC |
253 | } __attribute__((packed)); |
254 | #else | |
255 | struct x86_hw_tss { | |
4d46a89e IM |
256 | u32 reserved1; |
257 | u64 sp0; | |
258 | u64 sp1; | |
259 | u64 sp2; | |
260 | u64 reserved2; | |
261 | u64 ist[7]; | |
262 | u32 reserved3; | |
263 | u32 reserved4; | |
264 | u16 reserved5; | |
265 | u16 io_bitmap_base; | |
266 | ||
ca241c75 GOC |
267 | } __attribute__((packed)) ____cacheline_aligned; |
268 | #endif | |
269 | ||
270 | /* | |
4d46a89e | 271 | * IO-bitmap sizes: |
ca241c75 | 272 | */ |
4d46a89e IM |
273 | #define IO_BITMAP_BITS 65536 |
274 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
275 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
276 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) | |
277 | #define INVALID_IO_BITMAP_OFFSET 0x8000 | |
ca241c75 GOC |
278 | |
279 | struct tss_struct { | |
4d46a89e IM |
280 | /* |
281 | * The hardware state: | |
282 | */ | |
283 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
284 | |
285 | /* | |
286 | * The extra 1 is there because the CPU will access an | |
287 | * additional byte beyond the end of the IO permission | |
288 | * bitmap. The extra byte must be all 1 bits, and must | |
289 | * be within the limit. | |
290 | */ | |
4d46a89e | 291 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
4d46a89e | 292 | |
ca241c75 | 293 | /* |
4d46a89e | 294 | * .. and then another 0x100 bytes for the emergency kernel stack: |
ca241c75 | 295 | */ |
4d46a89e IM |
296 | unsigned long stack[64]; |
297 | ||
84e65b0a | 298 | } ____cacheline_aligned; |
ca241c75 | 299 | |
24933b82 | 300 | DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); |
ca241c75 | 301 | |
a7fcf28d AL |
302 | #ifdef CONFIG_X86_32 |
303 | DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); | |
304 | #endif | |
305 | ||
4d46a89e IM |
306 | /* |
307 | * Save the original ist values for checking stack pointers during debugging | |
308 | */ | |
1a53905a | 309 | struct orig_ist { |
4d46a89e | 310 | unsigned long ist[7]; |
1a53905a GOC |
311 | }; |
312 | ||
99f8ecdf | 313 | #define MXCSR_DEFAULT 0x1f80 |
46265df0 | 314 | |
99f8ecdf | 315 | struct i387_fsave_struct { |
ca9cda2f IM |
316 | u32 cwd; /* FPU Control Word */ |
317 | u32 swd; /* FPU Status Word */ | |
318 | u32 twd; /* FPU Tag Word */ | |
319 | u32 fip; /* FPU IP Offset */ | |
320 | u32 fcs; /* FPU IP Selector */ | |
321 | u32 foo; /* FPU Operand Pointer Offset */ | |
322 | u32 fos; /* FPU Operand Pointer Selector */ | |
323 | ||
324 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
4d46a89e | 325 | u32 st_space[20]; |
ca9cda2f IM |
326 | |
327 | /* Software status information [not touched by FSAVE ]: */ | |
4d46a89e | 328 | u32 status; |
46265df0 GOC |
329 | }; |
330 | ||
46265df0 | 331 | struct i387_fxsave_struct { |
ca9cda2f IM |
332 | u16 cwd; /* Control Word */ |
333 | u16 swd; /* Status Word */ | |
334 | u16 twd; /* Tag Word */ | |
335 | u16 fop; /* Last Instruction Opcode */ | |
99f8ecdf RM |
336 | union { |
337 | struct { | |
ca9cda2f IM |
338 | u64 rip; /* Instruction Pointer */ |
339 | u64 rdp; /* Data Pointer */ | |
99f8ecdf RM |
340 | }; |
341 | struct { | |
ca9cda2f IM |
342 | u32 fip; /* FPU IP Offset */ |
343 | u32 fcs; /* FPU IP Selector */ | |
344 | u32 foo; /* FPU Operand Offset */ | |
345 | u32 fos; /* FPU Operand Selector */ | |
99f8ecdf RM |
346 | }; |
347 | }; | |
ca9cda2f IM |
348 | u32 mxcsr; /* MXCSR Register State */ |
349 | u32 mxcsr_mask; /* MXCSR Mask */ | |
350 | ||
351 | /* 8*16 bytes for each FP-reg = 128 bytes: */ | |
4d46a89e | 352 | u32 st_space[32]; |
ca9cda2f IM |
353 | |
354 | /* 16*16 bytes for each XMM-reg = 256 bytes: */ | |
4d46a89e | 355 | u32 xmm_space[64]; |
ca9cda2f | 356 | |
bdd8caba SS |
357 | u32 padding[12]; |
358 | ||
359 | union { | |
360 | u32 padding1[12]; | |
361 | u32 sw_reserved[12]; | |
362 | }; | |
4d46a89e | 363 | |
46265df0 GOC |
364 | } __attribute__((aligned(16))); |
365 | ||
99f8ecdf | 366 | struct i387_soft_struct { |
4d46a89e IM |
367 | u32 cwd; |
368 | u32 swd; | |
369 | u32 twd; | |
370 | u32 fip; | |
371 | u32 fcs; | |
372 | u32 foo; | |
373 | u32 fos; | |
374 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
375 | u32 st_space[20]; | |
376 | u8 ftop; | |
377 | u8 changed; | |
378 | u8 lookahead; | |
379 | u8 no_update; | |
380 | u8 rm; | |
381 | u8 alimit; | |
ae6af41f | 382 | struct math_emu_info *info; |
4d46a89e | 383 | u32 entry_eip; |
99f8ecdf RM |
384 | }; |
385 | ||
a30469e7 SS |
386 | struct ymmh_struct { |
387 | /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ | |
388 | u32 ymmh_space[64]; | |
389 | }; | |
390 | ||
741e3902 | 391 | /* We don't support LWP yet: */ |
e7d820a5 | 392 | struct lwp_struct { |
741e3902 | 393 | u8 reserved[128]; |
e7d820a5 QR |
394 | }; |
395 | ||
c04e051c DH |
396 | struct bndreg { |
397 | u64 lower_bound; | |
398 | u64 upper_bound; | |
e7d820a5 QR |
399 | } __packed; |
400 | ||
62e7759b DH |
401 | struct bndcsr { |
402 | u64 bndcfgu; | |
403 | u64 bndstatus; | |
e7d820a5 QR |
404 | } __packed; |
405 | ||
dc1e35c6 SS |
406 | struct xsave_hdr_struct { |
407 | u64 xstate_bv; | |
0b29643a FY |
408 | u64 xcomp_bv; |
409 | u64 reserved[6]; | |
dc1e35c6 SS |
410 | } __attribute__((packed)); |
411 | ||
412 | struct xsave_struct { | |
413 | struct i387_fxsave_struct i387; | |
414 | struct xsave_hdr_struct xsave_hdr; | |
a30469e7 | 415 | struct ymmh_struct ymmh; |
e7d820a5 | 416 | struct lwp_struct lwp; |
c04e051c | 417 | struct bndreg bndreg[4]; |
62e7759b | 418 | struct bndcsr bndcsr; |
dc1e35c6 SS |
419 | /* new processor state extensions will go here */ |
420 | } __attribute__ ((packed, aligned (64))); | |
421 | ||
61c4628b | 422 | union thread_xstate { |
99f8ecdf | 423 | struct i387_fsave_struct fsave; |
46265df0 | 424 | struct i387_fxsave_struct fxsave; |
4d46a89e | 425 | struct i387_soft_struct soft; |
b359e8a4 | 426 | struct xsave_struct xsave; |
46265df0 GOC |
427 | }; |
428 | ||
86603283 | 429 | struct fpu { |
7e16838d LT |
430 | unsigned int last_cpu; |
431 | unsigned int has_fpu; | |
86603283 AK |
432 | union thread_xstate *state; |
433 | }; | |
434 | ||
fe676203 | 435 | #ifdef CONFIG_X86_64 |
2f66dcc9 | 436 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
26f80bd6 | 437 | |
947e76cd BG |
438 | union irq_stack_union { |
439 | char irq_stack[IRQ_STACK_SIZE]; | |
440 | /* | |
441 | * GCC hardcodes the stack canary as %gs:40. Since the | |
442 | * irq_stack is the object at %gs:0, we reserve the bottom | |
443 | * 48 bytes of the irq stack for the canary. | |
444 | */ | |
445 | struct { | |
446 | char gs_base[40]; | |
447 | unsigned long stack_canary; | |
448 | }; | |
449 | }; | |
450 | ||
277d5b40 | 451 | DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; |
2add8e23 BG |
452 | DECLARE_INIT_PER_CPU(irq_stack_union); |
453 | ||
26f80bd6 | 454 | DECLARE_PER_CPU(char *, irq_stack_ptr); |
9766cdbc | 455 | DECLARE_PER_CPU(unsigned int, irq_count); |
9766cdbc | 456 | extern asmlinkage void ignore_sysret(void); |
60a5317f TH |
457 | #else /* X86_64 */ |
458 | #ifdef CONFIG_CC_STACKPROTECTOR | |
1ea0d14e JF |
459 | /* |
460 | * Make sure stack canary segment base is cached-aligned: | |
461 | * "For Intel Atom processors, avoid non zero segment base address | |
462 | * that is not aligned to cache line boundary at all cost." | |
463 | * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) | |
464 | */ | |
465 | struct stack_canary { | |
466 | char __pad[20]; /* canary at %gs:20 */ | |
467 | unsigned long canary; | |
468 | }; | |
53f82452 | 469 | DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
96a388de | 470 | #endif |
198d208d SR |
471 | /* |
472 | * per-CPU IRQ handling stacks | |
473 | */ | |
474 | struct irq_stack { | |
475 | u32 stack[THREAD_SIZE/sizeof(u32)]; | |
476 | } __aligned(THREAD_SIZE); | |
477 | ||
478 | DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); | |
479 | DECLARE_PER_CPU(struct irq_stack *, softirq_stack); | |
60a5317f | 480 | #endif /* X86_64 */ |
c758ecf6 | 481 | |
61c4628b | 482 | extern unsigned int xstate_size; |
aa283f49 SS |
483 | extern void free_thread_xstate(struct task_struct *); |
484 | extern struct kmem_cache *task_xstate_cachep; | |
683e0253 | 485 | |
24f1e32c FW |
486 | struct perf_event; |
487 | ||
cb38d377 | 488 | struct thread_struct { |
4d46a89e IM |
489 | /* Cached TLS descriptors: */ |
490 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
491 | unsigned long sp0; | |
492 | unsigned long sp; | |
cb38d377 | 493 | #ifdef CONFIG_X86_32 |
4d46a89e | 494 | unsigned long sysenter_cs; |
cb38d377 | 495 | #else |
4d46a89e IM |
496 | unsigned long usersp; /* Copy from PDA */ |
497 | unsigned short es; | |
498 | unsigned short ds; | |
499 | unsigned short fsindex; | |
500 | unsigned short gsindex; | |
cb38d377 | 501 | #endif |
0c23590f | 502 | #ifdef CONFIG_X86_32 |
4d46a89e | 503 | unsigned long ip; |
0c23590f | 504 | #endif |
d756f4ad | 505 | #ifdef CONFIG_X86_64 |
4d46a89e | 506 | unsigned long fs; |
d756f4ad | 507 | #endif |
4d46a89e | 508 | unsigned long gs; |
24f1e32c FW |
509 | /* Save middle states of ptrace breakpoints */ |
510 | struct perf_event *ptrace_bps[HBP_NUM]; | |
511 | /* Debug status used for traps, single steps, etc... */ | |
512 | unsigned long debugreg6; | |
326264a0 FW |
513 | /* Keep track of the exact dr7 value set by the user */ |
514 | unsigned long ptrace_dr7; | |
4d46a89e IM |
515 | /* Fault info: */ |
516 | unsigned long cr2; | |
51e7dc70 | 517 | unsigned long trap_nr; |
4d46a89e | 518 | unsigned long error_code; |
61c4628b | 519 | /* floating point and extended processor state */ |
86603283 | 520 | struct fpu fpu; |
cb38d377 | 521 | #ifdef CONFIG_X86_32 |
4d46a89e | 522 | /* Virtual 86 mode info */ |
cb38d377 GOC |
523 | struct vm86_struct __user *vm86_info; |
524 | unsigned long screen_bitmap; | |
4d46a89e IM |
525 | unsigned long v86flags; |
526 | unsigned long v86mask; | |
527 | unsigned long saved_sp0; | |
528 | unsigned int saved_fs; | |
529 | unsigned int saved_gs; | |
cb38d377 | 530 | #endif |
4d46a89e IM |
531 | /* IO permissions: */ |
532 | unsigned long *io_bitmap_ptr; | |
533 | unsigned long iopl; | |
534 | /* Max allowed port in the bitmap, in bytes: */ | |
535 | unsigned io_bitmap_max; | |
c375f15a VG |
536 | /* |
537 | * fpu_counter contains the number of consecutive context switches | |
538 | * that the FPU is used. If this is over a threshold, the lazy fpu | |
539 | * saving becomes unlazy to save the trap. This is an unsigned char | |
540 | * so that after 256 times the counter wraps and the behavior turns | |
541 | * lazy again; this to deal with bursty apps that only use FPU for | |
542 | * a short time | |
543 | */ | |
544 | unsigned char fpu_counter; | |
cb38d377 GOC |
545 | }; |
546 | ||
62d7d7ed GOC |
547 | /* |
548 | * Set IOPL bits in EFLAGS from given mask | |
549 | */ | |
550 | static inline void native_set_iopl_mask(unsigned mask) | |
551 | { | |
552 | #ifdef CONFIG_X86_32 | |
553 | unsigned int reg; | |
4d46a89e | 554 | |
cca2e6f8 JP |
555 | asm volatile ("pushfl;" |
556 | "popl %0;" | |
557 | "andl %1, %0;" | |
558 | "orl %2, %0;" | |
559 | "pushl %0;" | |
560 | "popfl" | |
561 | : "=&r" (reg) | |
562 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
62d7d7ed GOC |
563 | #endif |
564 | } | |
565 | ||
4d46a89e IM |
566 | static inline void |
567 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
568 | { |
569 | tss->x86_tss.sp0 = thread->sp0; | |
570 | #ifdef CONFIG_X86_32 | |
4d46a89e | 571 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
7818a1e0 GOC |
572 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
573 | tss->x86_tss.ss1 = thread->sysenter_cs; | |
574 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); | |
575 | } | |
576 | #endif | |
577 | } | |
1b46cbe0 | 578 | |
e801f864 GOC |
579 | static inline void native_swapgs(void) |
580 | { | |
581 | #ifdef CONFIG_X86_64 | |
582 | asm volatile("swapgs" ::: "memory"); | |
583 | #endif | |
584 | } | |
585 | ||
a7fcf28d | 586 | static inline unsigned long current_top_of_stack(void) |
8ef46a67 | 587 | { |
a7fcf28d | 588 | #ifdef CONFIG_X86_64 |
24933b82 | 589 | return this_cpu_read_stable(cpu_tss.x86_tss.sp0); |
a7fcf28d AL |
590 | #else |
591 | /* sp0 on x86_32 is special in and around vm86 mode. */ | |
592 | return this_cpu_read_stable(cpu_current_top_of_stack); | |
593 | #endif | |
8ef46a67 AL |
594 | } |
595 | ||
7818a1e0 GOC |
596 | #ifdef CONFIG_PARAVIRT |
597 | #include <asm/paravirt.h> | |
598 | #else | |
4d46a89e IM |
599 | #define __cpuid native_cpuid |
600 | #define paravirt_enabled() 0 | |
1b46cbe0 | 601 | |
cca2e6f8 JP |
602 | static inline void load_sp0(struct tss_struct *tss, |
603 | struct thread_struct *thread) | |
7818a1e0 GOC |
604 | { |
605 | native_load_sp0(tss, thread); | |
606 | } | |
607 | ||
62d7d7ed | 608 | #define set_iopl_mask native_set_iopl_mask |
1b46cbe0 GOC |
609 | #endif /* CONFIG_PARAVIRT */ |
610 | ||
fc87e906 | 611 | typedef struct { |
4d46a89e | 612 | unsigned long seg; |
fc87e906 GOC |
613 | } mm_segment_t; |
614 | ||
615 | ||
683e0253 GOC |
616 | /* Free all resources held by a thread. */ |
617 | extern void release_thread(struct task_struct *); | |
618 | ||
683e0253 | 619 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
620 | |
621 | /* | |
622 | * Generic CPUID function | |
623 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
624 | * resulting in stale register contents being returned. | |
625 | */ | |
626 | static inline void cpuid(unsigned int op, | |
627 | unsigned int *eax, unsigned int *ebx, | |
628 | unsigned int *ecx, unsigned int *edx) | |
629 | { | |
630 | *eax = op; | |
631 | *ecx = 0; | |
632 | __cpuid(eax, ebx, ecx, edx); | |
633 | } | |
634 | ||
635 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
636 | static inline void cpuid_count(unsigned int op, int count, | |
637 | unsigned int *eax, unsigned int *ebx, | |
638 | unsigned int *ecx, unsigned int *edx) | |
639 | { | |
640 | *eax = op; | |
641 | *ecx = count; | |
642 | __cpuid(eax, ebx, ecx, edx); | |
643 | } | |
644 | ||
645 | /* | |
646 | * CPUID functions returning a single datum | |
647 | */ | |
648 | static inline unsigned int cpuid_eax(unsigned int op) | |
649 | { | |
650 | unsigned int eax, ebx, ecx, edx; | |
651 | ||
652 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 653 | |
c758ecf6 GOC |
654 | return eax; |
655 | } | |
4d46a89e | 656 | |
c758ecf6 GOC |
657 | static inline unsigned int cpuid_ebx(unsigned int op) |
658 | { | |
659 | unsigned int eax, ebx, ecx, edx; | |
660 | ||
661 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 662 | |
c758ecf6 GOC |
663 | return ebx; |
664 | } | |
4d46a89e | 665 | |
c758ecf6 GOC |
666 | static inline unsigned int cpuid_ecx(unsigned int op) |
667 | { | |
668 | unsigned int eax, ebx, ecx, edx; | |
669 | ||
670 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 671 | |
c758ecf6 GOC |
672 | return ecx; |
673 | } | |
4d46a89e | 674 | |
c758ecf6 GOC |
675 | static inline unsigned int cpuid_edx(unsigned int op) |
676 | { | |
677 | unsigned int eax, ebx, ecx, edx; | |
678 | ||
679 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 680 | |
c758ecf6 GOC |
681 | return edx; |
682 | } | |
683 | ||
683e0253 GOC |
684 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
685 | static inline void rep_nop(void) | |
686 | { | |
cca2e6f8 | 687 | asm volatile("rep; nop" ::: "memory"); |
683e0253 GOC |
688 | } |
689 | ||
4d46a89e IM |
690 | static inline void cpu_relax(void) |
691 | { | |
692 | rep_nop(); | |
693 | } | |
694 | ||
3a6bfbc9 DB |
695 | #define cpu_relax_lowlatency() cpu_relax() |
696 | ||
5367b688 | 697 | /* Stop speculative execution and prefetching of modified code. */ |
683e0253 GOC |
698 | static inline void sync_core(void) |
699 | { | |
700 | int tmp; | |
4d46a89e | 701 | |
eb068e78 | 702 | #ifdef CONFIG_M486 |
45c39fb0 PA |
703 | /* |
704 | * Do a CPUID if available, otherwise do a jump. The jump | |
705 | * can conveniently enough be the jump around CPUID. | |
706 | */ | |
707 | asm volatile("cmpl %2,%1\n\t" | |
708 | "jl 1f\n\t" | |
709 | "cpuid\n" | |
710 | "1:" | |
711 | : "=a" (tmp) | |
712 | : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) | |
713 | : "ebx", "ecx", "edx", "memory"); | |
714 | #else | |
715 | /* | |
716 | * CPUID is a barrier to speculative execution. | |
717 | * Prefetched instructions are automatically | |
718 | * invalidated when modified. | |
719 | */ | |
720 | asm volatile("cpuid" | |
721 | : "=a" (tmp) | |
722 | : "0" (1) | |
723 | : "ebx", "ecx", "edx", "memory"); | |
5367b688 | 724 | #endif |
683e0253 GOC |
725 | } |
726 | ||
683e0253 | 727 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
02c68a02 | 728 | extern void init_amd_e400_c1e_mask(void); |
683e0253 | 729 | |
4d46a89e | 730 | extern unsigned long boot_option_idle_override; |
02c68a02 | 731 | extern bool amd_e400_c1e_detected; |
683e0253 | 732 | |
d1896049 | 733 | enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, |
69fb3676 | 734 | IDLE_POLL}; |
d1896049 | 735 | |
1a53905a GOC |
736 | extern void enable_sep_cpu(void); |
737 | extern int sysenter_setup(void); | |
738 | ||
29c84391 | 739 | extern void early_trap_init(void); |
8170e6be | 740 | void early_trap_pf_init(void); |
29c84391 | 741 | |
1a53905a | 742 | /* Defined in head.S */ |
4d46a89e | 743 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
744 | |
745 | extern void cpu_set_gdt(int); | |
552be871 | 746 | extern void switch_to_new_gdt(int); |
11e3a840 | 747 | extern void load_percpu_segment(int); |
1a53905a | 748 | extern void cpu_init(void); |
1a53905a | 749 | |
c2724775 MM |
750 | static inline unsigned long get_debugctlmsr(void) |
751 | { | |
ea8e61b7 | 752 | unsigned long debugctlmsr = 0; |
c2724775 MM |
753 | |
754 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
755 | if (boot_cpu_data.x86 < 6) | |
756 | return 0; | |
757 | #endif | |
758 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
759 | ||
ea8e61b7 | 760 | return debugctlmsr; |
c2724775 MM |
761 | } |
762 | ||
5b0e5084 JB |
763 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
764 | { | |
765 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
766 | if (boot_cpu_data.x86 < 6) | |
767 | return; | |
768 | #endif | |
769 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
770 | } | |
771 | ||
9bd1190a ON |
772 | extern void set_task_blockstep(struct task_struct *task, bool on); |
773 | ||
4d46a89e IM |
774 | /* |
775 | * from system description table in BIOS. Mostly for MCA use, but | |
776 | * others may find it useful: | |
777 | */ | |
778 | extern unsigned int machine_id; | |
779 | extern unsigned int machine_submodel_id; | |
780 | extern unsigned int BIOS_revision; | |
1a53905a | 781 | |
4d46a89e IM |
782 | /* Boot loader type from the setup header: */ |
783 | extern int bootloader_type; | |
5031296c | 784 | extern int bootloader_version; |
1a53905a | 785 | |
4d46a89e | 786 | extern char ignore_fpu_irq; |
683e0253 GOC |
787 | |
788 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
789 | #define ARCH_HAS_PREFETCHW | |
790 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
791 | ||
ae2e15eb | 792 | #ifdef CONFIG_X86_32 |
a930dc45 | 793 | # define BASE_PREFETCH "" |
4d46a89e | 794 | # define ARCH_HAS_PREFETCH |
ae2e15eb | 795 | #else |
a930dc45 | 796 | # define BASE_PREFETCH "prefetcht0 %P1" |
ae2e15eb GOC |
797 | #endif |
798 | ||
4d46a89e IM |
799 | /* |
800 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
801 | * | |
802 | * It's not worth to care about 3dnow prefetches for the K6 | |
803 | * because they are microcoded there and very slow. | |
804 | */ | |
ae2e15eb GOC |
805 | static inline void prefetch(const void *x) |
806 | { | |
a930dc45 | 807 | alternative_input(BASE_PREFETCH, "prefetchnta %P1", |
ae2e15eb | 808 | X86_FEATURE_XMM, |
a930dc45 | 809 | "m" (*(const char *)x)); |
ae2e15eb GOC |
810 | } |
811 | ||
4d46a89e IM |
812 | /* |
813 | * 3dnow prefetch to get an exclusive cache line. | |
814 | * Useful for spinlocks to avoid one state transition in the | |
815 | * cache coherency protocol: | |
816 | */ | |
ae2e15eb GOC |
817 | static inline void prefetchw(const void *x) |
818 | { | |
a930dc45 BP |
819 | alternative_input(BASE_PREFETCH, "prefetchw %P1", |
820 | X86_FEATURE_3DNOWPREFETCH, | |
821 | "m" (*(const char *)x)); | |
ae2e15eb GOC |
822 | } |
823 | ||
4d46a89e IM |
824 | static inline void spin_lock_prefetch(const void *x) |
825 | { | |
826 | prefetchw(x); | |
827 | } | |
828 | ||
d9e05cc5 AL |
829 | #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ |
830 | TOP_OF_KERNEL_STACK_PADDING) | |
831 | ||
2f66dcc9 GOC |
832 | #ifdef CONFIG_X86_32 |
833 | /* | |
834 | * User space process size: 3GB (default). | |
835 | */ | |
4d46a89e | 836 | #define TASK_SIZE PAGE_OFFSET |
d9517346 | 837 | #define TASK_SIZE_MAX TASK_SIZE |
4d46a89e IM |
838 | #define STACK_TOP TASK_SIZE |
839 | #define STACK_TOP_MAX STACK_TOP | |
840 | ||
841 | #define INIT_THREAD { \ | |
d9e05cc5 | 842 | .sp0 = TOP_OF_INIT_STACK, \ |
4d46a89e IM |
843 | .vm86_info = NULL, \ |
844 | .sysenter_cs = __KERNEL_CS, \ | |
845 | .io_bitmap_ptr = NULL, \ | |
2f66dcc9 GOC |
846 | } |
847 | ||
2f66dcc9 GOC |
848 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
849 | ||
2f66dcc9 | 850 | /* |
5c39403e | 851 | * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. |
2f66dcc9 | 852 | * This is necessary to guarantee that the entire "struct pt_regs" |
b595076a | 853 | * is accessible even if the CPU haven't stored the SS/ESP registers |
2f66dcc9 GOC |
854 | * on the stack (interrupt gate does not save these registers |
855 | * when switching to the same priv ring). | |
856 | * Therefore beware: accessing the ss/esp fields of the | |
857 | * "struct pt_regs" is possible, but they may contain the | |
858 | * completely wrong values. | |
859 | */ | |
5c39403e DV |
860 | #define task_pt_regs(task) \ |
861 | ({ \ | |
862 | unsigned long __ptr = (unsigned long)task_stack_page(task); \ | |
863 | __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ | |
864 | ((struct pt_regs *)__ptr) - 1; \ | |
2f66dcc9 GOC |
865 | }) |
866 | ||
4d46a89e | 867 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
868 | |
869 | #else | |
870 | /* | |
07114f0f AL |
871 | * User space process size. 47bits minus one guard page. The guard |
872 | * page is necessary on Intel CPUs: if a SYSCALL instruction is at | |
873 | * the highest possible canonical userspace address, then that | |
874 | * syscall will enter the kernel with a non-canonical return | |
875 | * address, and SYSRET will explode dangerously. We avoid this | |
876 | * particular problem by preventing anything from being mapped | |
877 | * at the maximum canonical address. | |
2f66dcc9 | 878 | */ |
d9517346 | 879 | #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) |
2f66dcc9 GOC |
880 | |
881 | /* This decides where the kernel will search for a free chunk of vm | |
882 | * space during mmap's. | |
883 | */ | |
4d46a89e IM |
884 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
885 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 886 | |
6bd33008 | 887 | #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ |
d9517346 | 888 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
6bd33008 | 889 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ |
d9517346 | 890 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
2f66dcc9 | 891 | |
922a70d3 | 892 | #define STACK_TOP TASK_SIZE |
d9517346 | 893 | #define STACK_TOP_MAX TASK_SIZE_MAX |
922a70d3 | 894 | |
2f66dcc9 | 895 | #define INIT_THREAD { \ |
d9e05cc5 | 896 | .sp0 = TOP_OF_INIT_STACK \ |
2f66dcc9 GOC |
897 | } |
898 | ||
2f66dcc9 GOC |
899 | /* |
900 | * Return saved PC of a blocked thread. | |
901 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
902 | */ | |
4d46a89e | 903 | #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) |
2f66dcc9 | 904 | |
4d46a89e | 905 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
89240ba0 | 906 | extern unsigned long KSTK_ESP(struct task_struct *task); |
d046ff8b L |
907 | |
908 | /* | |
909 | * User space RSP while inside the SYSCALL fast path | |
910 | */ | |
911 | DECLARE_PER_CPU(unsigned long, old_rsp); | |
912 | ||
2f66dcc9 GOC |
913 | #endif /* CONFIG_X86_64 */ |
914 | ||
513ad84b IM |
915 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
916 | unsigned long new_sp); | |
917 | ||
4d46a89e IM |
918 | /* |
919 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
920 | * space during mmap's. |
921 | */ | |
922 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | |
923 | ||
4d46a89e | 924 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 925 | |
529e25f6 EB |
926 | /* Get/set a process' ability to use the timestamp counter instruction */ |
927 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) | |
928 | #define SET_TSC_CTL(val) set_tsc_mode((val)) | |
929 | ||
930 | extern int get_tsc_mode(unsigned long adr); | |
931 | extern int set_tsc_mode(unsigned int val); | |
932 | ||
fe3d197f DH |
933 | /* Register/unregister a process' MPX related resource */ |
934 | #define MPX_ENABLE_MANAGEMENT(tsk) mpx_enable_management((tsk)) | |
935 | #define MPX_DISABLE_MANAGEMENT(tsk) mpx_disable_management((tsk)) | |
936 | ||
937 | #ifdef CONFIG_X86_INTEL_MPX | |
938 | extern int mpx_enable_management(struct task_struct *tsk); | |
939 | extern int mpx_disable_management(struct task_struct *tsk); | |
940 | #else | |
941 | static inline int mpx_enable_management(struct task_struct *tsk) | |
942 | { | |
943 | return -EINVAL; | |
944 | } | |
945 | static inline int mpx_disable_management(struct task_struct *tsk) | |
946 | { | |
947 | return -EINVAL; | |
948 | } | |
949 | #endif /* CONFIG_X86_INTEL_MPX */ | |
950 | ||
8b84c8df | 951 | extern u16 amd_get_nb_id(int cpu); |
6a812691 | 952 | |
96e39ac0 JW |
953 | static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) |
954 | { | |
955 | uint32_t base, eax, signature[3]; | |
956 | ||
957 | for (base = 0x40000000; base < 0x40010000; base += 0x100) { | |
958 | cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); | |
959 | ||
960 | if (!memcmp(sig, signature, 12) && | |
961 | (leaves == 0 || ((eax - base) >= leaves))) | |
962 | return base; | |
963 | } | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
f05e798a DH |
968 | extern unsigned long arch_align_stack(unsigned long sp); |
969 | extern void free_init_pages(char *what, unsigned long begin, unsigned long end); | |
970 | ||
971 | void default_idle(void); | |
6a377ddc LB |
972 | #ifdef CONFIG_XEN |
973 | bool xen_set_default_idle(void); | |
974 | #else | |
975 | #define xen_set_default_idle 0 | |
976 | #endif | |
f05e798a DH |
977 | |
978 | void stop_this_cpu(void *dummy); | |
4d067d8e | 979 | void df_debug(struct pt_regs *regs, long error_code); |
1965aae3 | 980 | #endif /* _ASM_X86_PROCESSOR_H */ |