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1965aae3 PA |
1 | #ifndef _ASM_X86_PROCESSOR_H |
2 | #define _ASM_X86_PROCESSOR_H | |
c758ecf6 | 3 | |
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
683e0253 GOC |
6 | /* Forward declaration, a strange C thing */ |
7 | struct task_struct; | |
8 | struct mm_struct; | |
9 | ||
2f66dcc9 GOC |
10 | #include <asm/vm86.h> |
11 | #include <asm/math_emu.h> | |
12 | #include <asm/segment.h> | |
2f66dcc9 GOC |
13 | #include <asm/types.h> |
14 | #include <asm/sigcontext.h> | |
15 | #include <asm/current.h> | |
16 | #include <asm/cpufeature.h> | |
2f66dcc9 | 17 | #include <asm/page.h> |
54321d94 | 18 | #include <asm/pgtable_types.h> |
5300db88 | 19 | #include <asm/percpu.h> |
2f66dcc9 GOC |
20 | #include <asm/msr.h> |
21 | #include <asm/desc_defs.h> | |
bd61643e | 22 | #include <asm/nops.h> |
f05e798a | 23 | #include <asm/special_insns.h> |
14b9675a | 24 | #include <asm/fpu/types.h> |
4d46a89e | 25 | |
2f66dcc9 | 26 | #include <linux/personality.h> |
5300db88 GOC |
27 | #include <linux/cpumask.h> |
28 | #include <linux/cache.h> | |
2f66dcc9 | 29 | #include <linux/threads.h> |
5cbc19a9 | 30 | #include <linux/math64.h> |
faa4602e | 31 | #include <linux/err.h> |
f05e798a DH |
32 | #include <linux/irqflags.h> |
33 | ||
34 | /* | |
35 | * We handle most unaligned accesses in hardware. On the other hand | |
36 | * unaligned DMA can be quite expensive on some Nehalem processors. | |
37 | * | |
38 | * Based on this we disable the IP header alignment in network drivers. | |
39 | */ | |
40 | #define NET_IP_ALIGN 0 | |
c72dcf83 | 41 | |
b332828c | 42 | #define HBP_NUM 4 |
0ccb8acc GOC |
43 | /* |
44 | * Default implementation of macro that returns current | |
45 | * instruction pointer ("program counter"). | |
46 | */ | |
47 | static inline void *current_text_addr(void) | |
48 | { | |
49 | void *pc; | |
4d46a89e IM |
50 | |
51 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
52 | ||
0ccb8acc GOC |
53 | return pc; |
54 | } | |
55 | ||
dbcb4660 | 56 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
57 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
58 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 59 | #else |
4d46a89e IM |
60 | # define ARCH_MIN_TASKALIGN 16 |
61 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 | |
dbcb4660 GOC |
62 | #endif |
63 | ||
e0ba94f1 AS |
64 | enum tlb_infos { |
65 | ENTRIES, | |
66 | NR_INFO | |
67 | }; | |
68 | ||
69 | extern u16 __read_mostly tlb_lli_4k[NR_INFO]; | |
70 | extern u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
71 | extern u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
72 | extern u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
73 | extern u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
74 | extern u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 75 | extern u16 __read_mostly tlb_lld_1g[NR_INFO]; |
c4211f42 | 76 | |
5300db88 GOC |
77 | /* |
78 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
79 | * Members of this structure are referenced in head.S, so think twice | |
80 | * before touching them. [mj] | |
81 | */ | |
82 | ||
83 | struct cpuinfo_x86 { | |
4d46a89e IM |
84 | __u8 x86; /* CPU family */ |
85 | __u8 x86_vendor; /* CPU vendor */ | |
86 | __u8 x86_model; | |
87 | __u8 x86_mask; | |
5300db88 | 88 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
89 | char wp_works_ok; /* It doesn't on 386's */ |
90 | ||
91 | /* Problems on some 486Dx4's and old 386's: */ | |
4d46a89e | 92 | char rfu; |
4d46a89e | 93 | char pad0; |
60e019eb | 94 | char pad1; |
5300db88 | 95 | #else |
4d46a89e | 96 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
b1882e68 | 97 | int x86_tlbsize; |
13c6c532 | 98 | #endif |
4d46a89e IM |
99 | __u8 x86_virt_bits; |
100 | __u8 x86_phys_bits; | |
101 | /* CPUID returned core id bits: */ | |
102 | __u8 x86_coreid_bits; | |
103 | /* Max extended CPUID function supported: */ | |
104 | __u32 extended_cpuid_level; | |
4d46a89e IM |
105 | /* Maximum supported CPUID level, -1=no CPUID: */ |
106 | int cpuid_level; | |
65fc985b | 107 | __u32 x86_capability[NCAPINTS + NBUGINTS]; |
4d46a89e IM |
108 | char x86_vendor_id[16]; |
109 | char x86_model_id[64]; | |
110 | /* in KB - valid for CPUS which support this call: */ | |
111 | int x86_cache_size; | |
112 | int x86_cache_alignment; /* In bytes */ | |
cbc82b17 PWJ |
113 | /* Cache QoS architectural values: */ |
114 | int x86_cache_max_rmid; /* max index */ | |
115 | int x86_cache_occ_scale; /* scale to bytes */ | |
4d46a89e IM |
116 | int x86_power; |
117 | unsigned long loops_per_jiffy; | |
4d46a89e IM |
118 | /* cpuid returned max cores value: */ |
119 | u16 x86_max_cores; | |
120 | u16 apicid; | |
01aaea1a | 121 | u16 initial_apicid; |
4d46a89e | 122 | u16 x86_clflush_size; |
4d46a89e IM |
123 | /* number of cores as seen by the OS: */ |
124 | u16 booted_cores; | |
125 | /* Physical processor id: */ | |
126 | u16 phys_proc_id; | |
127 | /* Core id: */ | |
128 | u16 cpu_core_id; | |
6057b4d3 AH |
129 | /* Compute unit id */ |
130 | u8 compute_unit_id; | |
4d46a89e IM |
131 | /* Index into per_cpu list: */ |
132 | u16 cpu_index; | |
506ed6b5 | 133 | u32 microcode; |
2c773dd3 | 134 | }; |
5300db88 | 135 | |
4d46a89e IM |
136 | #define X86_VENDOR_INTEL 0 |
137 | #define X86_VENDOR_CYRIX 1 | |
138 | #define X86_VENDOR_AMD 2 | |
139 | #define X86_VENDOR_UMC 3 | |
4d46a89e IM |
140 | #define X86_VENDOR_CENTAUR 5 |
141 | #define X86_VENDOR_TRANSMETA 7 | |
142 | #define X86_VENDOR_NSC 8 | |
143 | #define X86_VENDOR_NUM 9 | |
144 | ||
145 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 146 | |
1a53905a GOC |
147 | /* |
148 | * capabilities of CPUs | |
149 | */ | |
4d46a89e IM |
150 | extern struct cpuinfo_x86 boot_cpu_data; |
151 | extern struct cpuinfo_x86 new_cpu_data; | |
152 | ||
153 | extern struct tss_struct doublefault_tss; | |
3e0c3737 YL |
154 | extern __u32 cpu_caps_cleared[NCAPINTS]; |
155 | extern __u32 cpu_caps_set[NCAPINTS]; | |
5300db88 GOC |
156 | |
157 | #ifdef CONFIG_SMP | |
2c773dd3 | 158 | DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
5300db88 | 159 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) |
5300db88 | 160 | #else |
7b543a53 | 161 | #define cpu_info boot_cpu_data |
5300db88 | 162 | #define cpu_data(cpu) boot_cpu_data |
5300db88 GOC |
163 | #endif |
164 | ||
1c6c727d JS |
165 | extern const struct seq_operations cpuinfo_op; |
166 | ||
4d46a89e IM |
167 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
168 | ||
169 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
1a7dc0db | 170 | extern void fpu__detect(struct cpuinfo_x86 *c); |
1a53905a | 171 | |
f580366f | 172 | extern void early_cpu_init(void); |
1a53905a GOC |
173 | extern void identify_boot_cpu(void); |
174 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 | 175 | extern void print_cpu_info(struct cpuinfo_x86 *); |
21c3fcf3 | 176 | void print_cpu_msr(struct cpuinfo_x86 *); |
5300db88 GOC |
177 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
178 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
04a15418 | 179 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
5300db88 | 180 | |
bbb65d2d | 181 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
1a53905a | 182 | extern void detect_ht(struct cpuinfo_x86 *c); |
1a53905a | 183 | |
d288e1cf FY |
184 | #ifdef CONFIG_X86_32 |
185 | extern int have_cpuid_p(void); | |
186 | #else | |
187 | static inline int have_cpuid_p(void) | |
188 | { | |
189 | return 1; | |
190 | } | |
191 | #endif | |
c758ecf6 | 192 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 193 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
194 | { |
195 | /* ecx is often an input as well as an output. */ | |
45a94d7c | 196 | asm volatile("cpuid" |
cca2e6f8 JP |
197 | : "=a" (*eax), |
198 | "=b" (*ebx), | |
199 | "=c" (*ecx), | |
200 | "=d" (*edx) | |
506ed6b5 AK |
201 | : "0" (*eax), "2" (*ecx) |
202 | : "memory"); | |
c758ecf6 GOC |
203 | } |
204 | ||
c72dcf83 GOC |
205 | static inline void load_cr3(pgd_t *pgdir) |
206 | { | |
207 | write_cr3(__pa(pgdir)); | |
208 | } | |
c758ecf6 | 209 | |
ca241c75 GOC |
210 | #ifdef CONFIG_X86_32 |
211 | /* This is the TSS defined by the hardware. */ | |
212 | struct x86_hw_tss { | |
4d46a89e IM |
213 | unsigned short back_link, __blh; |
214 | unsigned long sp0; | |
215 | unsigned short ss0, __ss0h; | |
cf9328cc | 216 | unsigned long sp1; |
76e4c490 AL |
217 | |
218 | /* | |
cf9328cc AL |
219 | * We don't use ring 1, so ss1 is a convenient scratch space in |
220 | * the same cacheline as sp0. We use ss1 to cache the value in | |
221 | * MSR_IA32_SYSENTER_CS. When we context switch | |
222 | * MSR_IA32_SYSENTER_CS, we first check if the new value being | |
223 | * written matches ss1, and, if it's not, then we wrmsr the new | |
224 | * value and update ss1. | |
76e4c490 | 225 | * |
cf9328cc AL |
226 | * The only reason we context switch MSR_IA32_SYSENTER_CS is |
227 | * that we set it to zero in vm86 tasks to avoid corrupting the | |
228 | * stack if we were to go through the sysenter path from vm86 | |
229 | * mode. | |
76e4c490 | 230 | */ |
76e4c490 AL |
231 | unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ |
232 | ||
233 | unsigned short __ss1h; | |
4d46a89e IM |
234 | unsigned long sp2; |
235 | unsigned short ss2, __ss2h; | |
236 | unsigned long __cr3; | |
237 | unsigned long ip; | |
238 | unsigned long flags; | |
239 | unsigned long ax; | |
240 | unsigned long cx; | |
241 | unsigned long dx; | |
242 | unsigned long bx; | |
243 | unsigned long sp; | |
244 | unsigned long bp; | |
245 | unsigned long si; | |
246 | unsigned long di; | |
247 | unsigned short es, __esh; | |
248 | unsigned short cs, __csh; | |
249 | unsigned short ss, __ssh; | |
250 | unsigned short ds, __dsh; | |
251 | unsigned short fs, __fsh; | |
252 | unsigned short gs, __gsh; | |
253 | unsigned short ldt, __ldth; | |
254 | unsigned short trace; | |
255 | unsigned short io_bitmap_base; | |
256 | ||
ca241c75 GOC |
257 | } __attribute__((packed)); |
258 | #else | |
259 | struct x86_hw_tss { | |
4d46a89e IM |
260 | u32 reserved1; |
261 | u64 sp0; | |
262 | u64 sp1; | |
263 | u64 sp2; | |
264 | u64 reserved2; | |
265 | u64 ist[7]; | |
266 | u32 reserved3; | |
267 | u32 reserved4; | |
268 | u16 reserved5; | |
269 | u16 io_bitmap_base; | |
270 | ||
ca241c75 GOC |
271 | } __attribute__((packed)) ____cacheline_aligned; |
272 | #endif | |
273 | ||
274 | /* | |
4d46a89e | 275 | * IO-bitmap sizes: |
ca241c75 | 276 | */ |
4d46a89e IM |
277 | #define IO_BITMAP_BITS 65536 |
278 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
279 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
280 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) | |
281 | #define INVALID_IO_BITMAP_OFFSET 0x8000 | |
ca241c75 GOC |
282 | |
283 | struct tss_struct { | |
4d46a89e IM |
284 | /* |
285 | * The hardware state: | |
286 | */ | |
287 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
288 | |
289 | /* | |
290 | * The extra 1 is there because the CPU will access an | |
291 | * additional byte beyond the end of the IO permission | |
292 | * bitmap. The extra byte must be all 1 bits, and must | |
293 | * be within the limit. | |
294 | */ | |
4d46a89e | 295 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
4d46a89e | 296 | |
ca241c75 | 297 | /* |
d828c71f | 298 | * Space for the temporary SYSENTER stack: |
ca241c75 | 299 | */ |
d828c71f | 300 | unsigned long SYSENTER_stack[64]; |
4d46a89e | 301 | |
84e65b0a | 302 | } ____cacheline_aligned; |
ca241c75 | 303 | |
24933b82 | 304 | DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); |
ca241c75 | 305 | |
a7fcf28d AL |
306 | #ifdef CONFIG_X86_32 |
307 | DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); | |
308 | #endif | |
309 | ||
4d46a89e IM |
310 | /* |
311 | * Save the original ist values for checking stack pointers during debugging | |
312 | */ | |
1a53905a | 313 | struct orig_ist { |
4d46a89e | 314 | unsigned long ist[7]; |
1a53905a GOC |
315 | }; |
316 | ||
fe676203 | 317 | #ifdef CONFIG_X86_64 |
2f66dcc9 | 318 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
26f80bd6 | 319 | |
947e76cd BG |
320 | union irq_stack_union { |
321 | char irq_stack[IRQ_STACK_SIZE]; | |
322 | /* | |
323 | * GCC hardcodes the stack canary as %gs:40. Since the | |
324 | * irq_stack is the object at %gs:0, we reserve the bottom | |
325 | * 48 bytes of the irq stack for the canary. | |
326 | */ | |
327 | struct { | |
328 | char gs_base[40]; | |
329 | unsigned long stack_canary; | |
330 | }; | |
331 | }; | |
332 | ||
277d5b40 | 333 | DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; |
2add8e23 BG |
334 | DECLARE_INIT_PER_CPU(irq_stack_union); |
335 | ||
26f80bd6 | 336 | DECLARE_PER_CPU(char *, irq_stack_ptr); |
9766cdbc | 337 | DECLARE_PER_CPU(unsigned int, irq_count); |
9766cdbc | 338 | extern asmlinkage void ignore_sysret(void); |
60a5317f TH |
339 | #else /* X86_64 */ |
340 | #ifdef CONFIG_CC_STACKPROTECTOR | |
1ea0d14e JF |
341 | /* |
342 | * Make sure stack canary segment base is cached-aligned: | |
343 | * "For Intel Atom processors, avoid non zero segment base address | |
344 | * that is not aligned to cache line boundary at all cost." | |
345 | * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) | |
346 | */ | |
347 | struct stack_canary { | |
348 | char __pad[20]; /* canary at %gs:20 */ | |
349 | unsigned long canary; | |
350 | }; | |
53f82452 | 351 | DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
96a388de | 352 | #endif |
198d208d SR |
353 | /* |
354 | * per-CPU IRQ handling stacks | |
355 | */ | |
356 | struct irq_stack { | |
357 | u32 stack[THREAD_SIZE/sizeof(u32)]; | |
358 | } __aligned(THREAD_SIZE); | |
359 | ||
360 | DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); | |
361 | DECLARE_PER_CPU(struct irq_stack *, softirq_stack); | |
60a5317f | 362 | #endif /* X86_64 */ |
c758ecf6 | 363 | |
61c4628b | 364 | extern unsigned int xstate_size; |
683e0253 | 365 | |
24f1e32c FW |
366 | struct perf_event; |
367 | ||
cb38d377 | 368 | struct thread_struct { |
4d46a89e IM |
369 | /* Cached TLS descriptors: */ |
370 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
371 | unsigned long sp0; | |
372 | unsigned long sp; | |
cb38d377 | 373 | #ifdef CONFIG_X86_32 |
4d46a89e | 374 | unsigned long sysenter_cs; |
cb38d377 | 375 | #else |
4d46a89e IM |
376 | unsigned short es; |
377 | unsigned short ds; | |
378 | unsigned short fsindex; | |
379 | unsigned short gsindex; | |
cb38d377 | 380 | #endif |
0c23590f | 381 | #ifdef CONFIG_X86_32 |
4d46a89e | 382 | unsigned long ip; |
0c23590f | 383 | #endif |
d756f4ad | 384 | #ifdef CONFIG_X86_64 |
4d46a89e | 385 | unsigned long fs; |
d756f4ad | 386 | #endif |
4d46a89e | 387 | unsigned long gs; |
24f1e32c FW |
388 | /* Save middle states of ptrace breakpoints */ |
389 | struct perf_event *ptrace_bps[HBP_NUM]; | |
390 | /* Debug status used for traps, single steps, etc... */ | |
391 | unsigned long debugreg6; | |
326264a0 FW |
392 | /* Keep track of the exact dr7 value set by the user */ |
393 | unsigned long ptrace_dr7; | |
4d46a89e IM |
394 | /* Fault info: */ |
395 | unsigned long cr2; | |
51e7dc70 | 396 | unsigned long trap_nr; |
4d46a89e | 397 | unsigned long error_code; |
61c4628b | 398 | /* floating point and extended processor state */ |
86603283 | 399 | struct fpu fpu; |
cb38d377 | 400 | #ifdef CONFIG_X86_32 |
4d46a89e | 401 | /* Virtual 86 mode info */ |
cb38d377 GOC |
402 | struct vm86_struct __user *vm86_info; |
403 | unsigned long screen_bitmap; | |
4d46a89e IM |
404 | unsigned long v86flags; |
405 | unsigned long v86mask; | |
406 | unsigned long saved_sp0; | |
407 | unsigned int saved_fs; | |
408 | unsigned int saved_gs; | |
cb38d377 | 409 | #endif |
4d46a89e IM |
410 | /* IO permissions: */ |
411 | unsigned long *io_bitmap_ptr; | |
412 | unsigned long iopl; | |
413 | /* Max allowed port in the bitmap, in bytes: */ | |
414 | unsigned io_bitmap_max; | |
cb38d377 GOC |
415 | }; |
416 | ||
62d7d7ed GOC |
417 | /* |
418 | * Set IOPL bits in EFLAGS from given mask | |
419 | */ | |
420 | static inline void native_set_iopl_mask(unsigned mask) | |
421 | { | |
422 | #ifdef CONFIG_X86_32 | |
423 | unsigned int reg; | |
4d46a89e | 424 | |
cca2e6f8 JP |
425 | asm volatile ("pushfl;" |
426 | "popl %0;" | |
427 | "andl %1, %0;" | |
428 | "orl %2, %0;" | |
429 | "pushl %0;" | |
430 | "popfl" | |
431 | : "=&r" (reg) | |
432 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
62d7d7ed GOC |
433 | #endif |
434 | } | |
435 | ||
4d46a89e IM |
436 | static inline void |
437 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
438 | { |
439 | tss->x86_tss.sp0 = thread->sp0; | |
440 | #ifdef CONFIG_X86_32 | |
4d46a89e | 441 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
7818a1e0 GOC |
442 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
443 | tss->x86_tss.ss1 = thread->sysenter_cs; | |
444 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); | |
445 | } | |
446 | #endif | |
447 | } | |
1b46cbe0 | 448 | |
e801f864 GOC |
449 | static inline void native_swapgs(void) |
450 | { | |
451 | #ifdef CONFIG_X86_64 | |
452 | asm volatile("swapgs" ::: "memory"); | |
453 | #endif | |
454 | } | |
455 | ||
a7fcf28d | 456 | static inline unsigned long current_top_of_stack(void) |
8ef46a67 | 457 | { |
a7fcf28d | 458 | #ifdef CONFIG_X86_64 |
24933b82 | 459 | return this_cpu_read_stable(cpu_tss.x86_tss.sp0); |
a7fcf28d AL |
460 | #else |
461 | /* sp0 on x86_32 is special in and around vm86 mode. */ | |
462 | return this_cpu_read_stable(cpu_current_top_of_stack); | |
463 | #endif | |
8ef46a67 AL |
464 | } |
465 | ||
7818a1e0 GOC |
466 | #ifdef CONFIG_PARAVIRT |
467 | #include <asm/paravirt.h> | |
468 | #else | |
4d46a89e IM |
469 | #define __cpuid native_cpuid |
470 | #define paravirt_enabled() 0 | |
1b46cbe0 | 471 | |
cca2e6f8 JP |
472 | static inline void load_sp0(struct tss_struct *tss, |
473 | struct thread_struct *thread) | |
7818a1e0 GOC |
474 | { |
475 | native_load_sp0(tss, thread); | |
476 | } | |
477 | ||
62d7d7ed | 478 | #define set_iopl_mask native_set_iopl_mask |
1b46cbe0 GOC |
479 | #endif /* CONFIG_PARAVIRT */ |
480 | ||
fc87e906 | 481 | typedef struct { |
4d46a89e | 482 | unsigned long seg; |
fc87e906 GOC |
483 | } mm_segment_t; |
484 | ||
485 | ||
683e0253 GOC |
486 | /* Free all resources held by a thread. */ |
487 | extern void release_thread(struct task_struct *); | |
488 | ||
683e0253 | 489 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
490 | |
491 | /* | |
492 | * Generic CPUID function | |
493 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
494 | * resulting in stale register contents being returned. | |
495 | */ | |
496 | static inline void cpuid(unsigned int op, | |
497 | unsigned int *eax, unsigned int *ebx, | |
498 | unsigned int *ecx, unsigned int *edx) | |
499 | { | |
500 | *eax = op; | |
501 | *ecx = 0; | |
502 | __cpuid(eax, ebx, ecx, edx); | |
503 | } | |
504 | ||
505 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
506 | static inline void cpuid_count(unsigned int op, int count, | |
507 | unsigned int *eax, unsigned int *ebx, | |
508 | unsigned int *ecx, unsigned int *edx) | |
509 | { | |
510 | *eax = op; | |
511 | *ecx = count; | |
512 | __cpuid(eax, ebx, ecx, edx); | |
513 | } | |
514 | ||
515 | /* | |
516 | * CPUID functions returning a single datum | |
517 | */ | |
518 | static inline unsigned int cpuid_eax(unsigned int op) | |
519 | { | |
520 | unsigned int eax, ebx, ecx, edx; | |
521 | ||
522 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 523 | |
c758ecf6 GOC |
524 | return eax; |
525 | } | |
4d46a89e | 526 | |
c758ecf6 GOC |
527 | static inline unsigned int cpuid_ebx(unsigned int op) |
528 | { | |
529 | unsigned int eax, ebx, ecx, edx; | |
530 | ||
531 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 532 | |
c758ecf6 GOC |
533 | return ebx; |
534 | } | |
4d46a89e | 535 | |
c758ecf6 GOC |
536 | static inline unsigned int cpuid_ecx(unsigned int op) |
537 | { | |
538 | unsigned int eax, ebx, ecx, edx; | |
539 | ||
540 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 541 | |
c758ecf6 GOC |
542 | return ecx; |
543 | } | |
4d46a89e | 544 | |
c758ecf6 GOC |
545 | static inline unsigned int cpuid_edx(unsigned int op) |
546 | { | |
547 | unsigned int eax, ebx, ecx, edx; | |
548 | ||
549 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 550 | |
c758ecf6 GOC |
551 | return edx; |
552 | } | |
553 | ||
683e0253 GOC |
554 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
555 | static inline void rep_nop(void) | |
556 | { | |
cca2e6f8 | 557 | asm volatile("rep; nop" ::: "memory"); |
683e0253 GOC |
558 | } |
559 | ||
4d46a89e IM |
560 | static inline void cpu_relax(void) |
561 | { | |
562 | rep_nop(); | |
563 | } | |
564 | ||
3a6bfbc9 DB |
565 | #define cpu_relax_lowlatency() cpu_relax() |
566 | ||
5367b688 | 567 | /* Stop speculative execution and prefetching of modified code. */ |
683e0253 GOC |
568 | static inline void sync_core(void) |
569 | { | |
570 | int tmp; | |
4d46a89e | 571 | |
eb068e78 | 572 | #ifdef CONFIG_M486 |
45c39fb0 PA |
573 | /* |
574 | * Do a CPUID if available, otherwise do a jump. The jump | |
575 | * can conveniently enough be the jump around CPUID. | |
576 | */ | |
577 | asm volatile("cmpl %2,%1\n\t" | |
578 | "jl 1f\n\t" | |
579 | "cpuid\n" | |
580 | "1:" | |
581 | : "=a" (tmp) | |
582 | : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) | |
583 | : "ebx", "ecx", "edx", "memory"); | |
584 | #else | |
585 | /* | |
586 | * CPUID is a barrier to speculative execution. | |
587 | * Prefetched instructions are automatically | |
588 | * invalidated when modified. | |
589 | */ | |
590 | asm volatile("cpuid" | |
591 | : "=a" (tmp) | |
592 | : "0" (1) | |
593 | : "ebx", "ecx", "edx", "memory"); | |
5367b688 | 594 | #endif |
683e0253 GOC |
595 | } |
596 | ||
683e0253 | 597 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
02c68a02 | 598 | extern void init_amd_e400_c1e_mask(void); |
683e0253 | 599 | |
4d46a89e | 600 | extern unsigned long boot_option_idle_override; |
02c68a02 | 601 | extern bool amd_e400_c1e_detected; |
683e0253 | 602 | |
d1896049 | 603 | enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, |
69fb3676 | 604 | IDLE_POLL}; |
d1896049 | 605 | |
1a53905a GOC |
606 | extern void enable_sep_cpu(void); |
607 | extern int sysenter_setup(void); | |
608 | ||
29c84391 | 609 | extern void early_trap_init(void); |
8170e6be | 610 | void early_trap_pf_init(void); |
29c84391 | 611 | |
1a53905a | 612 | /* Defined in head.S */ |
4d46a89e | 613 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
614 | |
615 | extern void cpu_set_gdt(int); | |
552be871 | 616 | extern void switch_to_new_gdt(int); |
11e3a840 | 617 | extern void load_percpu_segment(int); |
1a53905a | 618 | extern void cpu_init(void); |
1a53905a | 619 | |
c2724775 MM |
620 | static inline unsigned long get_debugctlmsr(void) |
621 | { | |
ea8e61b7 | 622 | unsigned long debugctlmsr = 0; |
c2724775 MM |
623 | |
624 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
625 | if (boot_cpu_data.x86 < 6) | |
626 | return 0; | |
627 | #endif | |
628 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
629 | ||
ea8e61b7 | 630 | return debugctlmsr; |
c2724775 MM |
631 | } |
632 | ||
5b0e5084 JB |
633 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
634 | { | |
635 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
636 | if (boot_cpu_data.x86 < 6) | |
637 | return; | |
638 | #endif | |
639 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
640 | } | |
641 | ||
9bd1190a ON |
642 | extern void set_task_blockstep(struct task_struct *task, bool on); |
643 | ||
4d46a89e IM |
644 | /* |
645 | * from system description table in BIOS. Mostly for MCA use, but | |
646 | * others may find it useful: | |
647 | */ | |
648 | extern unsigned int machine_id; | |
649 | extern unsigned int machine_submodel_id; | |
650 | extern unsigned int BIOS_revision; | |
1a53905a | 651 | |
4d46a89e IM |
652 | /* Boot loader type from the setup header: */ |
653 | extern int bootloader_type; | |
5031296c | 654 | extern int bootloader_version; |
1a53905a | 655 | |
4d46a89e | 656 | extern char ignore_fpu_irq; |
683e0253 GOC |
657 | |
658 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
659 | #define ARCH_HAS_PREFETCHW | |
660 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
661 | ||
ae2e15eb | 662 | #ifdef CONFIG_X86_32 |
a930dc45 | 663 | # define BASE_PREFETCH "" |
4d46a89e | 664 | # define ARCH_HAS_PREFETCH |
ae2e15eb | 665 | #else |
a930dc45 | 666 | # define BASE_PREFETCH "prefetcht0 %P1" |
ae2e15eb GOC |
667 | #endif |
668 | ||
4d46a89e IM |
669 | /* |
670 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
671 | * | |
672 | * It's not worth to care about 3dnow prefetches for the K6 | |
673 | * because they are microcoded there and very slow. | |
674 | */ | |
ae2e15eb GOC |
675 | static inline void prefetch(const void *x) |
676 | { | |
a930dc45 | 677 | alternative_input(BASE_PREFETCH, "prefetchnta %P1", |
ae2e15eb | 678 | X86_FEATURE_XMM, |
a930dc45 | 679 | "m" (*(const char *)x)); |
ae2e15eb GOC |
680 | } |
681 | ||
4d46a89e IM |
682 | /* |
683 | * 3dnow prefetch to get an exclusive cache line. | |
684 | * Useful for spinlocks to avoid one state transition in the | |
685 | * cache coherency protocol: | |
686 | */ | |
ae2e15eb GOC |
687 | static inline void prefetchw(const void *x) |
688 | { | |
a930dc45 BP |
689 | alternative_input(BASE_PREFETCH, "prefetchw %P1", |
690 | X86_FEATURE_3DNOWPREFETCH, | |
691 | "m" (*(const char *)x)); | |
ae2e15eb GOC |
692 | } |
693 | ||
4d46a89e IM |
694 | static inline void spin_lock_prefetch(const void *x) |
695 | { | |
696 | prefetchw(x); | |
697 | } | |
698 | ||
d9e05cc5 AL |
699 | #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ |
700 | TOP_OF_KERNEL_STACK_PADDING) | |
701 | ||
2f66dcc9 GOC |
702 | #ifdef CONFIG_X86_32 |
703 | /* | |
704 | * User space process size: 3GB (default). | |
705 | */ | |
4d46a89e | 706 | #define TASK_SIZE PAGE_OFFSET |
d9517346 | 707 | #define TASK_SIZE_MAX TASK_SIZE |
4d46a89e IM |
708 | #define STACK_TOP TASK_SIZE |
709 | #define STACK_TOP_MAX STACK_TOP | |
710 | ||
711 | #define INIT_THREAD { \ | |
d9e05cc5 | 712 | .sp0 = TOP_OF_INIT_STACK, \ |
4d46a89e IM |
713 | .vm86_info = NULL, \ |
714 | .sysenter_cs = __KERNEL_CS, \ | |
715 | .io_bitmap_ptr = NULL, \ | |
2f66dcc9 GOC |
716 | } |
717 | ||
2f66dcc9 GOC |
718 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
719 | ||
2f66dcc9 | 720 | /* |
5c39403e | 721 | * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. |
2f66dcc9 | 722 | * This is necessary to guarantee that the entire "struct pt_regs" |
b595076a | 723 | * is accessible even if the CPU haven't stored the SS/ESP registers |
2f66dcc9 GOC |
724 | * on the stack (interrupt gate does not save these registers |
725 | * when switching to the same priv ring). | |
726 | * Therefore beware: accessing the ss/esp fields of the | |
727 | * "struct pt_regs" is possible, but they may contain the | |
728 | * completely wrong values. | |
729 | */ | |
5c39403e DV |
730 | #define task_pt_regs(task) \ |
731 | ({ \ | |
732 | unsigned long __ptr = (unsigned long)task_stack_page(task); \ | |
733 | __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ | |
734 | ((struct pt_regs *)__ptr) - 1; \ | |
2f66dcc9 GOC |
735 | }) |
736 | ||
4d46a89e | 737 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
738 | |
739 | #else | |
740 | /* | |
07114f0f AL |
741 | * User space process size. 47bits minus one guard page. The guard |
742 | * page is necessary on Intel CPUs: if a SYSCALL instruction is at | |
743 | * the highest possible canonical userspace address, then that | |
744 | * syscall will enter the kernel with a non-canonical return | |
745 | * address, and SYSRET will explode dangerously. We avoid this | |
746 | * particular problem by preventing anything from being mapped | |
747 | * at the maximum canonical address. | |
2f66dcc9 | 748 | */ |
d9517346 | 749 | #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) |
2f66dcc9 GOC |
750 | |
751 | /* This decides where the kernel will search for a free chunk of vm | |
752 | * space during mmap's. | |
753 | */ | |
4d46a89e IM |
754 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
755 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 756 | |
6bd33008 | 757 | #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ |
d9517346 | 758 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
6bd33008 | 759 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ |
d9517346 | 760 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
2f66dcc9 | 761 | |
922a70d3 | 762 | #define STACK_TOP TASK_SIZE |
d9517346 | 763 | #define STACK_TOP_MAX TASK_SIZE_MAX |
922a70d3 | 764 | |
2f66dcc9 | 765 | #define INIT_THREAD { \ |
d9e05cc5 | 766 | .sp0 = TOP_OF_INIT_STACK \ |
2f66dcc9 GOC |
767 | } |
768 | ||
2f66dcc9 GOC |
769 | /* |
770 | * Return saved PC of a blocked thread. | |
771 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
772 | */ | |
4d46a89e | 773 | #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) |
2f66dcc9 | 774 | |
4d46a89e | 775 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
89240ba0 | 776 | extern unsigned long KSTK_ESP(struct task_struct *task); |
d046ff8b | 777 | |
2f66dcc9 GOC |
778 | #endif /* CONFIG_X86_64 */ |
779 | ||
513ad84b IM |
780 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
781 | unsigned long new_sp); | |
782 | ||
4d46a89e IM |
783 | /* |
784 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
785 | * space during mmap's. |
786 | */ | |
787 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | |
788 | ||
4d46a89e | 789 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 790 | |
529e25f6 EB |
791 | /* Get/set a process' ability to use the timestamp counter instruction */ |
792 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) | |
793 | #define SET_TSC_CTL(val) set_tsc_mode((val)) | |
794 | ||
795 | extern int get_tsc_mode(unsigned long adr); | |
796 | extern int set_tsc_mode(unsigned int val); | |
797 | ||
fe3d197f DH |
798 | /* Register/unregister a process' MPX related resource */ |
799 | #define MPX_ENABLE_MANAGEMENT(tsk) mpx_enable_management((tsk)) | |
800 | #define MPX_DISABLE_MANAGEMENT(tsk) mpx_disable_management((tsk)) | |
801 | ||
802 | #ifdef CONFIG_X86_INTEL_MPX | |
803 | extern int mpx_enable_management(struct task_struct *tsk); | |
804 | extern int mpx_disable_management(struct task_struct *tsk); | |
805 | #else | |
806 | static inline int mpx_enable_management(struct task_struct *tsk) | |
807 | { | |
808 | return -EINVAL; | |
809 | } | |
810 | static inline int mpx_disable_management(struct task_struct *tsk) | |
811 | { | |
812 | return -EINVAL; | |
813 | } | |
814 | #endif /* CONFIG_X86_INTEL_MPX */ | |
815 | ||
8b84c8df | 816 | extern u16 amd_get_nb_id(int cpu); |
6a812691 | 817 | |
96e39ac0 JW |
818 | static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) |
819 | { | |
820 | uint32_t base, eax, signature[3]; | |
821 | ||
822 | for (base = 0x40000000; base < 0x40010000; base += 0x100) { | |
823 | cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); | |
824 | ||
825 | if (!memcmp(sig, signature, 12) && | |
826 | (leaves == 0 || ((eax - base) >= leaves))) | |
827 | return base; | |
828 | } | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
f05e798a DH |
833 | extern unsigned long arch_align_stack(unsigned long sp); |
834 | extern void free_init_pages(char *what, unsigned long begin, unsigned long end); | |
835 | ||
836 | void default_idle(void); | |
6a377ddc LB |
837 | #ifdef CONFIG_XEN |
838 | bool xen_set_default_idle(void); | |
839 | #else | |
840 | #define xen_set_default_idle 0 | |
841 | #endif | |
f05e798a DH |
842 | |
843 | void stop_this_cpu(void *dummy); | |
4d067d8e | 844 | void df_debug(struct pt_regs *regs, long error_code); |
1965aae3 | 845 | #endif /* _ASM_X86_PROCESSOR_H */ |