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1965aae3 PA |
1 | #ifndef _ASM_X86_PROCESSOR_H |
2 | #define _ASM_X86_PROCESSOR_H | |
c758ecf6 | 3 | |
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
683e0253 GOC |
6 | /* Forward declaration, a strange C thing */ |
7 | struct task_struct; | |
8 | struct mm_struct; | |
9fda6a06 | 9 | struct vm86; |
683e0253 | 10 | |
2f66dcc9 GOC |
11 | #include <asm/math_emu.h> |
12 | #include <asm/segment.h> | |
2f66dcc9 | 13 | #include <asm/types.h> |
decb4c41 | 14 | #include <uapi/asm/sigcontext.h> |
2f66dcc9 | 15 | #include <asm/current.h> |
cd4d09ec | 16 | #include <asm/cpufeatures.h> |
2f66dcc9 | 17 | #include <asm/page.h> |
54321d94 | 18 | #include <asm/pgtable_types.h> |
5300db88 | 19 | #include <asm/percpu.h> |
2f66dcc9 GOC |
20 | #include <asm/msr.h> |
21 | #include <asm/desc_defs.h> | |
bd61643e | 22 | #include <asm/nops.h> |
f05e798a | 23 | #include <asm/special_insns.h> |
14b9675a | 24 | #include <asm/fpu/types.h> |
4d46a89e | 25 | |
2f66dcc9 | 26 | #include <linux/personality.h> |
5300db88 | 27 | #include <linux/cache.h> |
2f66dcc9 | 28 | #include <linux/threads.h> |
5cbc19a9 | 29 | #include <linux/math64.h> |
faa4602e | 30 | #include <linux/err.h> |
f05e798a DH |
31 | #include <linux/irqflags.h> |
32 | ||
33 | /* | |
34 | * We handle most unaligned accesses in hardware. On the other hand | |
35 | * unaligned DMA can be quite expensive on some Nehalem processors. | |
36 | * | |
37 | * Based on this we disable the IP header alignment in network drivers. | |
38 | */ | |
39 | #define NET_IP_ALIGN 0 | |
c72dcf83 | 40 | |
b332828c | 41 | #define HBP_NUM 4 |
0ccb8acc GOC |
42 | /* |
43 | * Default implementation of macro that returns current | |
44 | * instruction pointer ("program counter"). | |
45 | */ | |
46 | static inline void *current_text_addr(void) | |
47 | { | |
48 | void *pc; | |
4d46a89e IM |
49 | |
50 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
51 | ||
0ccb8acc GOC |
52 | return pc; |
53 | } | |
54 | ||
b8c1b8ea IM |
55 | /* |
56 | * These alignment constraints are for performance in the vSMP case, | |
57 | * but in the task_struct case we must also meet hardware imposed | |
58 | * alignment requirements of the FPU state: | |
59 | */ | |
dbcb4660 | 60 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
61 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
62 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 63 | #else |
b8c1b8ea | 64 | # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) |
4d46a89e | 65 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 |
dbcb4660 GOC |
66 | #endif |
67 | ||
e0ba94f1 AS |
68 | enum tlb_infos { |
69 | ENTRIES, | |
70 | NR_INFO | |
71 | }; | |
72 | ||
73 | extern u16 __read_mostly tlb_lli_4k[NR_INFO]; | |
74 | extern u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
75 | extern u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
76 | extern u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
77 | extern u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
78 | extern u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 79 | extern u16 __read_mostly tlb_lld_1g[NR_INFO]; |
c4211f42 | 80 | |
5300db88 GOC |
81 | /* |
82 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
04402116 | 83 | * Members of this structure are referenced in head_32.S, so think twice |
5300db88 GOC |
84 | * before touching them. [mj] |
85 | */ | |
86 | ||
87 | struct cpuinfo_x86 { | |
4d46a89e IM |
88 | __u8 x86; /* CPU family */ |
89 | __u8 x86_vendor; /* CPU vendor */ | |
90 | __u8 x86_model; | |
91 | __u8 x86_mask; | |
6415813b | 92 | #ifdef CONFIG_X86_64 |
4d46a89e | 93 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
b1882e68 | 94 | int x86_tlbsize; |
13c6c532 | 95 | #endif |
4d46a89e IM |
96 | __u8 x86_virt_bits; |
97 | __u8 x86_phys_bits; | |
98 | /* CPUID returned core id bits: */ | |
99 | __u8 x86_coreid_bits; | |
79a8b9aa | 100 | __u8 cu_id; |
4d46a89e IM |
101 | /* Max extended CPUID function supported: */ |
102 | __u32 extended_cpuid_level; | |
4d46a89e IM |
103 | /* Maximum supported CPUID level, -1=no CPUID: */ |
104 | int cpuid_level; | |
65fc985b | 105 | __u32 x86_capability[NCAPINTS + NBUGINTS]; |
4d46a89e IM |
106 | char x86_vendor_id[16]; |
107 | char x86_model_id[64]; | |
108 | /* in KB - valid for CPUS which support this call: */ | |
109 | int x86_cache_size; | |
110 | int x86_cache_alignment; /* In bytes */ | |
cbc82b17 PWJ |
111 | /* Cache QoS architectural values: */ |
112 | int x86_cache_max_rmid; /* max index */ | |
113 | int x86_cache_occ_scale; /* scale to bytes */ | |
4d46a89e IM |
114 | int x86_power; |
115 | unsigned long loops_per_jiffy; | |
4d46a89e IM |
116 | /* cpuid returned max cores value: */ |
117 | u16 x86_max_cores; | |
118 | u16 apicid; | |
01aaea1a | 119 | u16 initial_apicid; |
4d46a89e | 120 | u16 x86_clflush_size; |
4d46a89e IM |
121 | /* number of cores as seen by the OS: */ |
122 | u16 booted_cores; | |
123 | /* Physical processor id: */ | |
124 | u16 phys_proc_id; | |
1f12e32f TG |
125 | /* Logical processor id: */ |
126 | u16 logical_proc_id; | |
4d46a89e IM |
127 | /* Core id: */ |
128 | u16 cpu_core_id; | |
129 | /* Index into per_cpu list: */ | |
130 | u16 cpu_index; | |
506ed6b5 | 131 | u32 microcode; |
3859a271 | 132 | } __randomize_layout; |
5300db88 | 133 | |
47f10a36 HC |
134 | struct cpuid_regs { |
135 | u32 eax, ebx, ecx, edx; | |
136 | }; | |
137 | ||
138 | enum cpuid_regs_idx { | |
139 | CPUID_EAX = 0, | |
140 | CPUID_EBX, | |
141 | CPUID_ECX, | |
142 | CPUID_EDX, | |
143 | }; | |
144 | ||
4d46a89e IM |
145 | #define X86_VENDOR_INTEL 0 |
146 | #define X86_VENDOR_CYRIX 1 | |
147 | #define X86_VENDOR_AMD 2 | |
148 | #define X86_VENDOR_UMC 3 | |
4d46a89e IM |
149 | #define X86_VENDOR_CENTAUR 5 |
150 | #define X86_VENDOR_TRANSMETA 7 | |
151 | #define X86_VENDOR_NSC 8 | |
152 | #define X86_VENDOR_NUM 9 | |
153 | ||
154 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 155 | |
1a53905a GOC |
156 | /* |
157 | * capabilities of CPUs | |
158 | */ | |
4d46a89e IM |
159 | extern struct cpuinfo_x86 boot_cpu_data; |
160 | extern struct cpuinfo_x86 new_cpu_data; | |
161 | ||
243de7bd AL |
162 | #include <linux/thread_info.h> |
163 | ||
7123a5de | 164 | extern struct x86_hw_tss doublefault_tss; |
aab40a66 TG |
165 | extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
166 | extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
5300db88 GOC |
167 | |
168 | #ifdef CONFIG_SMP | |
2c773dd3 | 169 | DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
5300db88 | 170 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) |
5300db88 | 171 | #else |
7b543a53 | 172 | #define cpu_info boot_cpu_data |
5300db88 | 173 | #define cpu_data(cpu) boot_cpu_data |
5300db88 GOC |
174 | #endif |
175 | ||
1c6c727d JS |
176 | extern const struct seq_operations cpuinfo_op; |
177 | ||
4d46a89e IM |
178 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
179 | ||
180 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
1a53905a | 181 | |
f580366f | 182 | extern void early_cpu_init(void); |
1a53905a GOC |
183 | extern void identify_boot_cpu(void); |
184 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 | 185 | extern void print_cpu_info(struct cpuinfo_x86 *); |
21c3fcf3 | 186 | void print_cpu_msr(struct cpuinfo_x86 *); |
5300db88 | 187 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
47bdf337 HC |
188 | extern u32 get_scattered_cpuid_leaf(unsigned int level, |
189 | unsigned int sub_leaf, | |
190 | enum cpuid_regs_idx reg); | |
5300db88 | 191 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); |
04a15418 | 192 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
5300db88 | 193 | |
bbb65d2d | 194 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
1a53905a | 195 | extern void detect_ht(struct cpuinfo_x86 *c); |
1a53905a | 196 | |
d288e1cf FY |
197 | #ifdef CONFIG_X86_32 |
198 | extern int have_cpuid_p(void); | |
199 | #else | |
200 | static inline int have_cpuid_p(void) | |
201 | { | |
202 | return 1; | |
203 | } | |
204 | #endif | |
c758ecf6 | 205 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 206 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
207 | { |
208 | /* ecx is often an input as well as an output. */ | |
45a94d7c | 209 | asm volatile("cpuid" |
cca2e6f8 JP |
210 | : "=a" (*eax), |
211 | "=b" (*ebx), | |
212 | "=c" (*ecx), | |
213 | "=d" (*edx) | |
506ed6b5 AK |
214 | : "0" (*eax), "2" (*ecx) |
215 | : "memory"); | |
c758ecf6 GOC |
216 | } |
217 | ||
5dedade6 BP |
218 | #define native_cpuid_reg(reg) \ |
219 | static inline unsigned int native_cpuid_##reg(unsigned int op) \ | |
220 | { \ | |
221 | unsigned int eax = op, ebx, ecx = 0, edx; \ | |
222 | \ | |
223 | native_cpuid(&eax, &ebx, &ecx, &edx); \ | |
224 | \ | |
225 | return reg; \ | |
226 | } | |
227 | ||
228 | /* | |
229 | * Native CPUID functions returning a single datum. | |
230 | */ | |
231 | native_cpuid_reg(eax) | |
232 | native_cpuid_reg(ebx) | |
233 | native_cpuid_reg(ecx) | |
234 | native_cpuid_reg(edx) | |
235 | ||
6c690ee1 AL |
236 | /* |
237 | * Friendlier CR3 helpers. | |
238 | */ | |
239 | static inline unsigned long read_cr3_pa(void) | |
240 | { | |
241 | return __read_cr3() & CR3_ADDR_MASK; | |
242 | } | |
243 | ||
c72dcf83 GOC |
244 | static inline void load_cr3(pgd_t *pgdir) |
245 | { | |
246 | write_cr3(__pa(pgdir)); | |
247 | } | |
c758ecf6 | 248 | |
7123a5de AL |
249 | /* |
250 | * Note that while the legacy 'TSS' name comes from 'Task State Segment', | |
251 | * on modern x86 CPUs the TSS also holds information important to 64-bit mode, | |
252 | * unrelated to the task-switch mechanism: | |
253 | */ | |
ca241c75 GOC |
254 | #ifdef CONFIG_X86_32 |
255 | /* This is the TSS defined by the hardware. */ | |
256 | struct x86_hw_tss { | |
4d46a89e IM |
257 | unsigned short back_link, __blh; |
258 | unsigned long sp0; | |
259 | unsigned short ss0, __ss0h; | |
cf9328cc | 260 | unsigned long sp1; |
76e4c490 AL |
261 | |
262 | /* | |
cf9328cc AL |
263 | * We don't use ring 1, so ss1 is a convenient scratch space in |
264 | * the same cacheline as sp0. We use ss1 to cache the value in | |
265 | * MSR_IA32_SYSENTER_CS. When we context switch | |
266 | * MSR_IA32_SYSENTER_CS, we first check if the new value being | |
267 | * written matches ss1, and, if it's not, then we wrmsr the new | |
268 | * value and update ss1. | |
76e4c490 | 269 | * |
cf9328cc AL |
270 | * The only reason we context switch MSR_IA32_SYSENTER_CS is |
271 | * that we set it to zero in vm86 tasks to avoid corrupting the | |
272 | * stack if we were to go through the sysenter path from vm86 | |
273 | * mode. | |
76e4c490 | 274 | */ |
76e4c490 AL |
275 | unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ |
276 | ||
277 | unsigned short __ss1h; | |
4d46a89e IM |
278 | unsigned long sp2; |
279 | unsigned short ss2, __ss2h; | |
280 | unsigned long __cr3; | |
281 | unsigned long ip; | |
282 | unsigned long flags; | |
283 | unsigned long ax; | |
284 | unsigned long cx; | |
285 | unsigned long dx; | |
286 | unsigned long bx; | |
287 | unsigned long sp; | |
288 | unsigned long bp; | |
289 | unsigned long si; | |
290 | unsigned long di; | |
291 | unsigned short es, __esh; | |
292 | unsigned short cs, __csh; | |
293 | unsigned short ss, __ssh; | |
294 | unsigned short ds, __dsh; | |
295 | unsigned short fs, __fsh; | |
296 | unsigned short gs, __gsh; | |
297 | unsigned short ldt, __ldth; | |
298 | unsigned short trace; | |
299 | unsigned short io_bitmap_base; | |
300 | ||
ca241c75 GOC |
301 | } __attribute__((packed)); |
302 | #else | |
303 | struct x86_hw_tss { | |
4d46a89e IM |
304 | u32 reserved1; |
305 | u64 sp0; | |
281be4ff AL |
306 | |
307 | /* | |
308 | * We store cpu_current_top_of_stack in sp1 so it's always accessible. | |
309 | * Linux does not use ring 1, so sp1 is not otherwise needed. | |
310 | */ | |
4d46a89e | 311 | u64 sp1; |
281be4ff | 312 | |
4d46a89e IM |
313 | u64 sp2; |
314 | u64 reserved2; | |
315 | u64 ist[7]; | |
316 | u32 reserved3; | |
317 | u32 reserved4; | |
318 | u16 reserved5; | |
319 | u16 io_bitmap_base; | |
320 | ||
d3273dea | 321 | } __attribute__((packed)); |
ca241c75 GOC |
322 | #endif |
323 | ||
324 | /* | |
4d46a89e | 325 | * IO-bitmap sizes: |
ca241c75 | 326 | */ |
4d46a89e IM |
327 | #define IO_BITMAP_BITS 65536 |
328 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
329 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
7123a5de | 330 | #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss)) |
4d46a89e | 331 | #define INVALID_IO_BITMAP_OFFSET 0x8000 |
ca241c75 | 332 | |
e0437c47 | 333 | struct entry_stack { |
a308af33 AL |
334 | unsigned long words[64]; |
335 | }; | |
336 | ||
e0437c47 DH |
337 | struct entry_stack_page { |
338 | struct entry_stack stack; | |
785be108 | 339 | } __aligned(PAGE_SIZE); |
57d6cfd9 | 340 | |
785be108 | 341 | struct tss_struct { |
57d6cfd9 AL |
342 | /* |
343 | * The fixed hardware portion. This must not cross a page boundary | |
344 | * at risk of violating the SDM's advice and potentially triggering | |
345 | * errata. | |
4d46a89e IM |
346 | */ |
347 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
348 | |
349 | /* | |
350 | * The extra 1 is there because the CPU will access an | |
351 | * additional byte beyond the end of the IO permission | |
352 | * bitmap. The extra byte must be all 1 bits, and must | |
353 | * be within the limit. | |
354 | */ | |
4d46a89e | 355 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
57d6cfd9 | 356 | } __aligned(PAGE_SIZE); |
4d46a89e | 357 | |
785be108 | 358 | DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); |
ca241c75 | 359 | |
4f53ab14 AL |
360 | /* |
361 | * sizeof(unsigned long) coming from an extra "long" at the end | |
362 | * of the iobitmap. | |
363 | * | |
364 | * -1? seg base+limit should be pointing to the address of the | |
365 | * last valid byte | |
366 | */ | |
367 | #define __KERNEL_TSS_LIMIT \ | |
368 | (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) | |
369 | ||
a7fcf28d AL |
370 | #ifdef CONFIG_X86_32 |
371 | DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); | |
281be4ff | 372 | #else |
785be108 AL |
373 | /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */ |
374 | #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1 | |
a7fcf28d AL |
375 | #endif |
376 | ||
4d46a89e IM |
377 | /* |
378 | * Save the original ist values for checking stack pointers during debugging | |
379 | */ | |
1a53905a | 380 | struct orig_ist { |
4d46a89e | 381 | unsigned long ist[7]; |
1a53905a GOC |
382 | }; |
383 | ||
fe676203 | 384 | #ifdef CONFIG_X86_64 |
2f66dcc9 | 385 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
26f80bd6 | 386 | |
947e76cd BG |
387 | union irq_stack_union { |
388 | char irq_stack[IRQ_STACK_SIZE]; | |
389 | /* | |
390 | * GCC hardcodes the stack canary as %gs:40. Since the | |
391 | * irq_stack is the object at %gs:0, we reserve the bottom | |
392 | * 48 bytes of the irq stack for the canary. | |
393 | */ | |
394 | struct { | |
395 | char gs_base[40]; | |
396 | unsigned long stack_canary; | |
397 | }; | |
398 | }; | |
399 | ||
277d5b40 | 400 | DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; |
2add8e23 BG |
401 | DECLARE_INIT_PER_CPU(irq_stack_union); |
402 | ||
26f80bd6 | 403 | DECLARE_PER_CPU(char *, irq_stack_ptr); |
9766cdbc | 404 | DECLARE_PER_CPU(unsigned int, irq_count); |
9766cdbc | 405 | extern asmlinkage void ignore_sysret(void); |
60a5317f TH |
406 | #else /* X86_64 */ |
407 | #ifdef CONFIG_CC_STACKPROTECTOR | |
1ea0d14e JF |
408 | /* |
409 | * Make sure stack canary segment base is cached-aligned: | |
410 | * "For Intel Atom processors, avoid non zero segment base address | |
411 | * that is not aligned to cache line boundary at all cost." | |
412 | * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) | |
413 | */ | |
414 | struct stack_canary { | |
415 | char __pad[20]; /* canary at %gs:20 */ | |
416 | unsigned long canary; | |
417 | }; | |
53f82452 | 418 | DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
96a388de | 419 | #endif |
198d208d SR |
420 | /* |
421 | * per-CPU IRQ handling stacks | |
422 | */ | |
423 | struct irq_stack { | |
424 | u32 stack[THREAD_SIZE/sizeof(u32)]; | |
425 | } __aligned(THREAD_SIZE); | |
426 | ||
427 | DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); | |
428 | DECLARE_PER_CPU(struct irq_stack *, softirq_stack); | |
60a5317f | 429 | #endif /* X86_64 */ |
c758ecf6 | 430 | |
bf15a8cf | 431 | extern unsigned int fpu_kernel_xstate_size; |
a1141e0b | 432 | extern unsigned int fpu_user_xstate_size; |
683e0253 | 433 | |
24f1e32c FW |
434 | struct perf_event; |
435 | ||
13d4ea09 AL |
436 | typedef struct { |
437 | unsigned long seg; | |
438 | } mm_segment_t; | |
439 | ||
cb38d377 | 440 | struct thread_struct { |
4d46a89e IM |
441 | /* Cached TLS descriptors: */ |
442 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
4910af19 | 443 | #ifdef CONFIG_X86_32 |
4d46a89e | 444 | unsigned long sp0; |
4910af19 | 445 | #endif |
4d46a89e | 446 | unsigned long sp; |
cb38d377 | 447 | #ifdef CONFIG_X86_32 |
4d46a89e | 448 | unsigned long sysenter_cs; |
cb38d377 | 449 | #else |
4d46a89e IM |
450 | unsigned short es; |
451 | unsigned short ds; | |
452 | unsigned short fsindex; | |
453 | unsigned short gsindex; | |
cb38d377 | 454 | #endif |
b9d989c7 AL |
455 | |
456 | u32 status; /* thread synchronous flags */ | |
457 | ||
d756f4ad | 458 | #ifdef CONFIG_X86_64 |
296f781a AL |
459 | unsigned long fsbase; |
460 | unsigned long gsbase; | |
461 | #else | |
462 | /* | |
463 | * XXX: this could presumably be unsigned short. Alternatively, | |
464 | * 32-bit kernels could be taught to use fsindex instead. | |
465 | */ | |
466 | unsigned long fs; | |
467 | unsigned long gs; | |
d756f4ad | 468 | #endif |
c5bedc68 | 469 | |
24f1e32c FW |
470 | /* Save middle states of ptrace breakpoints */ |
471 | struct perf_event *ptrace_bps[HBP_NUM]; | |
472 | /* Debug status used for traps, single steps, etc... */ | |
473 | unsigned long debugreg6; | |
326264a0 FW |
474 | /* Keep track of the exact dr7 value set by the user */ |
475 | unsigned long ptrace_dr7; | |
4d46a89e IM |
476 | /* Fault info: */ |
477 | unsigned long cr2; | |
51e7dc70 | 478 | unsigned long trap_nr; |
4d46a89e | 479 | unsigned long error_code; |
9fda6a06 | 480 | #ifdef CONFIG_VM86 |
4d46a89e | 481 | /* Virtual 86 mode info */ |
9fda6a06 | 482 | struct vm86 *vm86; |
cb38d377 | 483 | #endif |
4d46a89e IM |
484 | /* IO permissions: */ |
485 | unsigned long *io_bitmap_ptr; | |
486 | unsigned long iopl; | |
487 | /* Max allowed port in the bitmap, in bytes: */ | |
488 | unsigned io_bitmap_max; | |
0c8c0f03 | 489 | |
13d4ea09 AL |
490 | mm_segment_t addr_limit; |
491 | ||
2a53ccbc | 492 | unsigned int sig_on_uaccess_err:1; |
dfa9a942 AL |
493 | unsigned int uaccess_err:1; /* uaccess failed */ |
494 | ||
0c8c0f03 DH |
495 | /* Floating point and extended processor state */ |
496 | struct fpu fpu; | |
497 | /* | |
498 | * WARNING: 'fpu' is dynamically-sized. It *MUST* be at | |
499 | * the end. | |
500 | */ | |
cb38d377 GOC |
501 | }; |
502 | ||
b9d989c7 AL |
503 | /* |
504 | * Thread-synchronous status. | |
505 | * | |
506 | * This is different from the flags in that nobody else | |
507 | * ever touches our thread-synchronous status, so we don't | |
508 | * have to worry about atomic accesses. | |
509 | */ | |
510 | #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ | |
511 | ||
62d7d7ed GOC |
512 | /* |
513 | * Set IOPL bits in EFLAGS from given mask | |
514 | */ | |
515 | static inline void native_set_iopl_mask(unsigned mask) | |
516 | { | |
517 | #ifdef CONFIG_X86_32 | |
518 | unsigned int reg; | |
4d46a89e | 519 | |
cca2e6f8 JP |
520 | asm volatile ("pushfl;" |
521 | "popl %0;" | |
522 | "andl %1, %0;" | |
523 | "orl %2, %0;" | |
524 | "pushl %0;" | |
525 | "popfl" | |
526 | : "=&r" (reg) | |
527 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
62d7d7ed GOC |
528 | #endif |
529 | } | |
530 | ||
4d46a89e | 531 | static inline void |
41f6a89b | 532 | native_load_sp0(unsigned long sp0) |
7818a1e0 | 533 | { |
785be108 | 534 | this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); |
7818a1e0 | 535 | } |
1b46cbe0 | 536 | |
e801f864 GOC |
537 | static inline void native_swapgs(void) |
538 | { | |
539 | #ifdef CONFIG_X86_64 | |
540 | asm volatile("swapgs" ::: "memory"); | |
541 | #endif | |
542 | } | |
543 | ||
a7fcf28d | 544 | static inline unsigned long current_top_of_stack(void) |
8ef46a67 | 545 | { |
281be4ff AL |
546 | /* |
547 | * We can't read directly from tss.sp0: sp0 on x86_32 is special in | |
548 | * and around vm86 mode and sp0 on x86_64 is special because of the | |
549 | * entry trampoline. | |
550 | */ | |
a7fcf28d | 551 | return this_cpu_read_stable(cpu_current_top_of_stack); |
8ef46a67 AL |
552 | } |
553 | ||
243de7bd AL |
554 | static inline bool on_thread_stack(void) |
555 | { | |
556 | return (unsigned long)(current_top_of_stack() - | |
557 | current_stack_pointer()) < THREAD_SIZE; | |
558 | } | |
559 | ||
7818a1e0 GOC |
560 | #ifdef CONFIG_PARAVIRT |
561 | #include <asm/paravirt.h> | |
562 | #else | |
4d46a89e | 563 | #define __cpuid native_cpuid |
1b46cbe0 | 564 | |
41f6a89b | 565 | static inline void load_sp0(unsigned long sp0) |
7818a1e0 | 566 | { |
41f6a89b | 567 | native_load_sp0(sp0); |
7818a1e0 GOC |
568 | } |
569 | ||
62d7d7ed | 570 | #define set_iopl_mask native_set_iopl_mask |
1b46cbe0 GOC |
571 | #endif /* CONFIG_PARAVIRT */ |
572 | ||
683e0253 GOC |
573 | /* Free all resources held by a thread. */ |
574 | extern void release_thread(struct task_struct *); | |
575 | ||
683e0253 | 576 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
577 | |
578 | /* | |
579 | * Generic CPUID function | |
580 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
581 | * resulting in stale register contents being returned. | |
582 | */ | |
583 | static inline void cpuid(unsigned int op, | |
584 | unsigned int *eax, unsigned int *ebx, | |
585 | unsigned int *ecx, unsigned int *edx) | |
586 | { | |
587 | *eax = op; | |
588 | *ecx = 0; | |
589 | __cpuid(eax, ebx, ecx, edx); | |
590 | } | |
591 | ||
592 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
593 | static inline void cpuid_count(unsigned int op, int count, | |
594 | unsigned int *eax, unsigned int *ebx, | |
595 | unsigned int *ecx, unsigned int *edx) | |
596 | { | |
597 | *eax = op; | |
598 | *ecx = count; | |
599 | __cpuid(eax, ebx, ecx, edx); | |
600 | } | |
601 | ||
602 | /* | |
603 | * CPUID functions returning a single datum | |
604 | */ | |
605 | static inline unsigned int cpuid_eax(unsigned int op) | |
606 | { | |
607 | unsigned int eax, ebx, ecx, edx; | |
608 | ||
609 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 610 | |
c758ecf6 GOC |
611 | return eax; |
612 | } | |
4d46a89e | 613 | |
c758ecf6 GOC |
614 | static inline unsigned int cpuid_ebx(unsigned int op) |
615 | { | |
616 | unsigned int eax, ebx, ecx, edx; | |
617 | ||
618 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 619 | |
c758ecf6 GOC |
620 | return ebx; |
621 | } | |
4d46a89e | 622 | |
c758ecf6 GOC |
623 | static inline unsigned int cpuid_ecx(unsigned int op) |
624 | { | |
625 | unsigned int eax, ebx, ecx, edx; | |
626 | ||
627 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 628 | |
c758ecf6 GOC |
629 | return ecx; |
630 | } | |
4d46a89e | 631 | |
c758ecf6 GOC |
632 | static inline unsigned int cpuid_edx(unsigned int op) |
633 | { | |
634 | unsigned int eax, ebx, ecx, edx; | |
635 | ||
636 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 637 | |
c758ecf6 GOC |
638 | return edx; |
639 | } | |
640 | ||
683e0253 | 641 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
0b101e62 | 642 | static __always_inline void rep_nop(void) |
683e0253 | 643 | { |
cca2e6f8 | 644 | asm volatile("rep; nop" ::: "memory"); |
683e0253 GOC |
645 | } |
646 | ||
0b101e62 | 647 | static __always_inline void cpu_relax(void) |
4d46a89e IM |
648 | { |
649 | rep_nop(); | |
650 | } | |
651 | ||
c198b121 AL |
652 | /* |
653 | * This function forces the icache and prefetched instruction stream to | |
654 | * catch up with reality in two very specific cases: | |
655 | * | |
656 | * a) Text was modified using one virtual address and is about to be executed | |
657 | * from the same physical page at a different virtual address. | |
658 | * | |
659 | * b) Text was modified on a different CPU, may subsequently be | |
660 | * executed on this CPU, and you want to make sure the new version | |
661 | * gets executed. This generally means you're calling this in a IPI. | |
662 | * | |
663 | * If you're calling this for a different reason, you're probably doing | |
664 | * it wrong. | |
665 | */ | |
683e0253 GOC |
666 | static inline void sync_core(void) |
667 | { | |
45c39fb0 | 668 | /* |
c198b121 AL |
669 | * There are quite a few ways to do this. IRET-to-self is nice |
670 | * because it works on every CPU, at any CPL (so it's compatible | |
671 | * with paravirtualization), and it never exits to a hypervisor. | |
672 | * The only down sides are that it's a bit slow (it seems to be | |
673 | * a bit more than 2x slower than the fastest options) and that | |
674 | * it unmasks NMIs. The "push %cs" is needed because, in | |
675 | * paravirtual environments, __KERNEL_CS may not be a valid CS | |
676 | * value when we do IRET directly. | |
677 | * | |
678 | * In case NMI unmasking or performance ever becomes a problem, | |
679 | * the next best option appears to be MOV-to-CR2 and an | |
680 | * unconditional jump. That sequence also works on all CPUs, | |
681 | * but it will fault at CPL3 (i.e. Xen PV and lguest). | |
682 | * | |
683 | * CPUID is the conventional way, but it's nasty: it doesn't | |
684 | * exist on some 486-like CPUs, and it usually exits to a | |
685 | * hypervisor. | |
686 | * | |
687 | * Like all of Linux's memory ordering operations, this is a | |
688 | * compiler barrier as well. | |
45c39fb0 | 689 | */ |
c198b121 AL |
690 | #ifdef CONFIG_X86_32 |
691 | asm volatile ( | |
692 | "pushfl\n\t" | |
693 | "pushl %%cs\n\t" | |
694 | "pushl $1f\n\t" | |
695 | "iret\n\t" | |
696 | "1:" | |
0d3109a1 | 697 | : ASM_CALL_CONSTRAINT : : "memory"); |
45c39fb0 | 698 | #else |
c198b121 AL |
699 | unsigned int tmp; |
700 | ||
701 | asm volatile ( | |
702 | "mov %%ss, %0\n\t" | |
703 | "pushq %q0\n\t" | |
704 | "pushq %%rsp\n\t" | |
705 | "addq $8, (%%rsp)\n\t" | |
706 | "pushfq\n\t" | |
707 | "mov %%cs, %0\n\t" | |
708 | "pushq %q0\n\t" | |
709 | "pushq $1f\n\t" | |
710 | "iretq\n\t" | |
711 | "1:" | |
0d3109a1 | 712 | : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory"); |
5367b688 | 713 | #endif |
683e0253 GOC |
714 | } |
715 | ||
683e0253 | 716 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
07c94a38 | 717 | extern void amd_e400_c1e_apic_setup(void); |
683e0253 | 718 | |
4d46a89e | 719 | extern unsigned long boot_option_idle_override; |
683e0253 | 720 | |
d1896049 | 721 | enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, |
69fb3676 | 722 | IDLE_POLL}; |
d1896049 | 723 | |
1a53905a GOC |
724 | extern void enable_sep_cpu(void); |
725 | extern int sysenter_setup(void); | |
726 | ||
29c84391 | 727 | extern void early_trap_init(void); |
8170e6be | 728 | void early_trap_pf_init(void); |
29c84391 | 729 | |
1a53905a | 730 | /* Defined in head.S */ |
4d46a89e | 731 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
732 | |
733 | extern void cpu_set_gdt(int); | |
552be871 | 734 | extern void switch_to_new_gdt(int); |
45fc8757 | 735 | extern void load_direct_gdt(int); |
69218e47 | 736 | extern void load_fixmap_gdt(int); |
11e3a840 | 737 | extern void load_percpu_segment(int); |
1a53905a | 738 | extern void cpu_init(void); |
1a53905a | 739 | |
c2724775 MM |
740 | static inline unsigned long get_debugctlmsr(void) |
741 | { | |
ea8e61b7 | 742 | unsigned long debugctlmsr = 0; |
c2724775 MM |
743 | |
744 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
745 | if (boot_cpu_data.x86 < 6) | |
746 | return 0; | |
747 | #endif | |
748 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
749 | ||
ea8e61b7 | 750 | return debugctlmsr; |
c2724775 MM |
751 | } |
752 | ||
5b0e5084 JB |
753 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
754 | { | |
755 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
756 | if (boot_cpu_data.x86 < 6) | |
757 | return; | |
758 | #endif | |
759 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
760 | } | |
761 | ||
9bd1190a ON |
762 | extern void set_task_blockstep(struct task_struct *task, bool on); |
763 | ||
4d46a89e IM |
764 | /* Boot loader type from the setup header: */ |
765 | extern int bootloader_type; | |
5031296c | 766 | extern int bootloader_version; |
1a53905a | 767 | |
4d46a89e | 768 | extern char ignore_fpu_irq; |
683e0253 GOC |
769 | |
770 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
771 | #define ARCH_HAS_PREFETCHW | |
772 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
773 | ||
ae2e15eb | 774 | #ifdef CONFIG_X86_32 |
a930dc45 | 775 | # define BASE_PREFETCH "" |
4d46a89e | 776 | # define ARCH_HAS_PREFETCH |
ae2e15eb | 777 | #else |
a930dc45 | 778 | # define BASE_PREFETCH "prefetcht0 %P1" |
ae2e15eb GOC |
779 | #endif |
780 | ||
4d46a89e IM |
781 | /* |
782 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
783 | * | |
784 | * It's not worth to care about 3dnow prefetches for the K6 | |
785 | * because they are microcoded there and very slow. | |
786 | */ | |
ae2e15eb GOC |
787 | static inline void prefetch(const void *x) |
788 | { | |
a930dc45 | 789 | alternative_input(BASE_PREFETCH, "prefetchnta %P1", |
ae2e15eb | 790 | X86_FEATURE_XMM, |
a930dc45 | 791 | "m" (*(const char *)x)); |
ae2e15eb GOC |
792 | } |
793 | ||
4d46a89e IM |
794 | /* |
795 | * 3dnow prefetch to get an exclusive cache line. | |
796 | * Useful for spinlocks to avoid one state transition in the | |
797 | * cache coherency protocol: | |
798 | */ | |
ae2e15eb GOC |
799 | static inline void prefetchw(const void *x) |
800 | { | |
a930dc45 BP |
801 | alternative_input(BASE_PREFETCH, "prefetchw %P1", |
802 | X86_FEATURE_3DNOWPREFETCH, | |
803 | "m" (*(const char *)x)); | |
ae2e15eb GOC |
804 | } |
805 | ||
4d46a89e IM |
806 | static inline void spin_lock_prefetch(const void *x) |
807 | { | |
808 | prefetchw(x); | |
809 | } | |
810 | ||
d9e05cc5 AL |
811 | #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ |
812 | TOP_OF_KERNEL_STACK_PADDING) | |
813 | ||
f1078e10 AL |
814 | #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) |
815 | ||
4910af19 AL |
816 | #define task_pt_regs(task) \ |
817 | ({ \ | |
818 | unsigned long __ptr = (unsigned long)task_stack_page(task); \ | |
819 | __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ | |
820 | ((struct pt_regs *)__ptr) - 1; \ | |
821 | }) | |
822 | ||
2f66dcc9 GOC |
823 | #ifdef CONFIG_X86_32 |
824 | /* | |
825 | * User space process size: 3GB (default). | |
826 | */ | |
8f3e474f | 827 | #define IA32_PAGE_OFFSET PAGE_OFFSET |
4d46a89e | 828 | #define TASK_SIZE PAGE_OFFSET |
d9517346 | 829 | #define TASK_SIZE_MAX TASK_SIZE |
4d46a89e IM |
830 | #define STACK_TOP TASK_SIZE |
831 | #define STACK_TOP_MAX STACK_TOP | |
832 | ||
833 | #define INIT_THREAD { \ | |
d9e05cc5 | 834 | .sp0 = TOP_OF_INIT_STACK, \ |
4d46a89e IM |
835 | .sysenter_cs = __KERNEL_CS, \ |
836 | .io_bitmap_ptr = NULL, \ | |
13d4ea09 | 837 | .addr_limit = KERNEL_DS, \ |
2f66dcc9 GOC |
838 | } |
839 | ||
4d46a89e | 840 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
841 | |
842 | #else | |
843 | /* | |
c2506438 AL |
844 | * User space process size. This is the first address outside the user range. |
845 | * There are a few constraints that determine this: | |
846 | * | |
847 | * On Intel CPUs, if a SYSCALL instruction is at the highest canonical | |
848 | * address, then that syscall will enter the kernel with a | |
849 | * non-canonical return address, and SYSRET will explode dangerously. | |
850 | * We avoid this particular problem by preventing anything executable | |
851 | * from being mapped at the maximum canonical address. | |
852 | * | |
853 | * On AMD CPUs in the Ryzen family, there's a nasty bug in which the | |
854 | * CPUs malfunction if they execute code from the highest canonical page. | |
855 | * They'll speculate right off the end of the canonical space, and | |
856 | * bad things happen. This is worked around in the same way as the | |
857 | * Intel problem. | |
858 | * | |
859 | * With page table isolation enabled, we map the LDT in ... [stay tuned] | |
2f66dcc9 | 860 | */ |
d9517346 | 861 | #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) |
2f66dcc9 GOC |
862 | |
863 | /* This decides where the kernel will search for a free chunk of vm | |
864 | * space during mmap's. | |
865 | */ | |
4d46a89e IM |
866 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
867 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 868 | |
6bd33008 | 869 | #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ |
d9517346 | 870 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
6bd33008 | 871 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ |
d9517346 | 872 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
2f66dcc9 | 873 | |
922a70d3 | 874 | #define STACK_TOP TASK_SIZE |
d9517346 | 875 | #define STACK_TOP_MAX TASK_SIZE_MAX |
922a70d3 | 876 | |
13d4ea09 | 877 | #define INIT_THREAD { \ |
13d4ea09 | 878 | .addr_limit = KERNEL_DS, \ |
2f66dcc9 GOC |
879 | } |
880 | ||
89240ba0 | 881 | extern unsigned long KSTK_ESP(struct task_struct *task); |
d046ff8b | 882 | |
2f66dcc9 GOC |
883 | #endif /* CONFIG_X86_64 */ |
884 | ||
513ad84b IM |
885 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
886 | unsigned long new_sp); | |
887 | ||
4d46a89e IM |
888 | /* |
889 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
890 | * space during mmap's. |
891 | */ | |
8f3e474f DS |
892 | #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) |
893 | #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE) | |
683e0253 | 894 | |
4d46a89e | 895 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 896 | |
529e25f6 EB |
897 | /* Get/set a process' ability to use the timestamp counter instruction */ |
898 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) | |
899 | #define SET_TSC_CTL(val) set_tsc_mode((val)) | |
900 | ||
901 | extern int get_tsc_mode(unsigned long adr); | |
902 | extern int set_tsc_mode(unsigned int val); | |
903 | ||
e9ea1e7f KH |
904 | DECLARE_PER_CPU(u64, msr_misc_features_shadow); |
905 | ||
fe3d197f | 906 | /* Register/unregister a process' MPX related resource */ |
46a6e0cf DH |
907 | #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() |
908 | #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() | |
fe3d197f DH |
909 | |
910 | #ifdef CONFIG_X86_INTEL_MPX | |
46a6e0cf DH |
911 | extern int mpx_enable_management(void); |
912 | extern int mpx_disable_management(void); | |
fe3d197f | 913 | #else |
46a6e0cf | 914 | static inline int mpx_enable_management(void) |
fe3d197f DH |
915 | { |
916 | return -EINVAL; | |
917 | } | |
46a6e0cf | 918 | static inline int mpx_disable_management(void) |
fe3d197f DH |
919 | { |
920 | return -EINVAL; | |
921 | } | |
922 | #endif /* CONFIG_X86_INTEL_MPX */ | |
923 | ||
bc8e80d5 | 924 | #ifdef CONFIG_CPU_SUP_AMD |
8b84c8df | 925 | extern u16 amd_get_nb_id(int cpu); |
cc2749e4 | 926 | extern u32 amd_get_nodes_per_socket(void); |
bc8e80d5 BP |
927 | #else |
928 | static inline u16 amd_get_nb_id(int cpu) { return 0; } | |
929 | static inline u32 amd_get_nodes_per_socket(void) { return 0; } | |
930 | #endif | |
6a812691 | 931 | |
96e39ac0 JW |
932 | static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) |
933 | { | |
934 | uint32_t base, eax, signature[3]; | |
935 | ||
936 | for (base = 0x40000000; base < 0x40010000; base += 0x100) { | |
937 | cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); | |
938 | ||
939 | if (!memcmp(sig, signature, 12) && | |
940 | (leaves == 0 || ((eax - base) >= leaves))) | |
941 | return base; | |
942 | } | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
f05e798a DH |
947 | extern unsigned long arch_align_stack(unsigned long sp); |
948 | extern void free_init_pages(char *what, unsigned long begin, unsigned long end); | |
949 | ||
950 | void default_idle(void); | |
6a377ddc LB |
951 | #ifdef CONFIG_XEN |
952 | bool xen_set_default_idle(void); | |
953 | #else | |
954 | #define xen_set_default_idle 0 | |
955 | #endif | |
f05e798a DH |
956 | |
957 | void stop_this_cpu(void *dummy); | |
4d067d8e | 958 | void df_debug(struct pt_regs *regs, long error_code); |
1965aae3 | 959 | #endif /* _ASM_X86_PROCESSOR_H */ |