[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / svm.h

#ifndef __SVM_H
#define __SVM_H

#include <uapi/asm/svm.h>


enum {
	INTERCEPT_INTR,
	INTERCEPT_NMI,
	INTERCEPT_SMI,
	INTERCEPT_INIT,
	INTERCEPT_VINTR,
	INTERCEPT_SELECTIVE_CR0,
	INTERCEPT_STORE_IDTR,
	INTERCEPT_STORE_GDTR,
	INTERCEPT_STORE_LDTR,
	INTERCEPT_STORE_TR,
	INTERCEPT_LOAD_IDTR,
	INTERCEPT_LOAD_GDTR,
	INTERCEPT_LOAD_LDTR,
	INTERCEPT_LOAD_TR,
	INTERCEPT_RDTSC,
	INTERCEPT_RDPMC,
	INTERCEPT_PUSHF,
	INTERCEPT_POPF,
	INTERCEPT_CPUID,
	INTERCEPT_RSM,
	INTERCEPT_IRET,
	INTERCEPT_INTn,
	INTERCEPT_INVD,
	INTERCEPT_PAUSE,
	INTERCEPT_HLT,
	INTERCEPT_INVLPG,
	INTERCEPT_INVLPGA,
	INTERCEPT_IOIO_PROT,
	INTERCEPT_MSR_PROT,
	INTERCEPT_TASK_SWITCH,
	INTERCEPT_FERR_FREEZE,
	INTERCEPT_SHUTDOWN,
	INTERCEPT_VMRUN,
	INTERCEPT_VMMCALL,
	INTERCEPT_VMLOAD,
	INTERCEPT_VMSAVE,
	INTERCEPT_STGI,
	INTERCEPT_CLGI,
	INTERCEPT_SKINIT,
	INTERCEPT_RDTSCP,
	INTERCEPT_ICEBP,
	INTERCEPT_WBINVD,
	INTERCEPT_MONITOR,
	INTERCEPT_MWAIT,
	INTERCEPT_MWAIT_COND,
	INTERCEPT_XSETBV,
};


struct __attribute__ ((__packed__)) vmcb_control_area {
	u32 intercept_cr;
	u32 intercept_dr;
	u32 intercept_exceptions;
	u64 intercept;
	u8 reserved_1[42];
	u16 pause_filter_count;
	u64 iopm_base_pa;
	u64 msrpm_base_pa;
	u64 tsc_offset;
	u32 asid;
	u8 tlb_ctl;
	u8 reserved_2[3];
	u32 int_ctl;
	u32 int_vector;
	u32 int_state;
	u8 reserved_3[4];
	u32 exit_code;
	u32 exit_code_hi;
	u64 exit_info_1;
	u64 exit_info_2;
	u32 exit_int_info;
	u32 exit_int_info_err;
	u64 nested_ctl;
	u64 avic_vapic_bar;
	u8 reserved_4[8];
	u32 event_inj;
	u32 event_inj_err;
	u64 nested_cr3;
	u64 lbr_ctl;
	u32 clean;
	u32 reserved_5;
	u64 next_rip;
	u8 insn_len;
	u8 insn_bytes[15];
	u64 avic_backing_page;	/* Offset 0xe0 */
	u8 reserved_6[8];	/* Offset 0xe8 */
	u64 avic_logical_id;	/* Offset 0xf0 */
	u64 avic_physical_id;	/* Offset 0xf8 */
	u8 reserved_7[768];
};


#define TLB_CONTROL_DO_NOTHING 0
#define TLB_CONTROL_FLUSH_ALL_ASID 1
#define TLB_CONTROL_FLUSH_ASID 3
#define TLB_CONTROL_FLUSH_ASID_LOCAL 7

#define V_TPR_MASK 0x0f

#define V_IRQ_SHIFT 8
#define V_IRQ_MASK (1 << V_IRQ_SHIFT)

#define V_INTR_PRIO_SHIFT 16
#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)

#define V_IGN_TPR_SHIFT 20
#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)

#define V_INTR_MASKING_SHIFT 24
#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)

#define AVIC_ENABLE_SHIFT 31
#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)

#define SVM_INTERRUPT_SHADOW_MASK 1

#define SVM_IOIO_STR_SHIFT 2
#define SVM_IOIO_REP_SHIFT 3
#define SVM_IOIO_SIZE_SHIFT 4
#define SVM_IOIO_ASIZE_SHIFT 7

#define SVM_IOIO_TYPE_MASK 1
#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)

#define SVM_VM_CR_VALID_MASK	0x001fULL
#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
#define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL

struct __attribute__ ((__packed__)) vmcb_seg {
	u16 selector;
	u16 attrib;
	u32 limit;
	u64 base;
};

struct __attribute__ ((__packed__)) vmcb_save_area {
	struct vmcb_seg es;
	struct vmcb_seg cs;
	struct vmcb_seg ss;
	struct vmcb_seg ds;
	struct vmcb_seg fs;
	struct vmcb_seg gs;
	struct vmcb_seg gdtr;
	struct vmcb_seg ldtr;
	struct vmcb_seg idtr;
	struct vmcb_seg tr;
	u8 reserved_1[43];
	u8 cpl;
	u8 reserved_2[4];
	u64 efer;
	u8 reserved_3[112];
	u64 cr4;
	u64 cr3;
	u64 cr0;
	u64 dr7;
	u64 dr6;
	u64 rflags;
	u64 rip;
	u8 reserved_4[88];
	u64 rsp;
	u8 reserved_5[24];
	u64 rax;
	u64 star;
	u64 lstar;
	u64 cstar;
	u64 sfmask;
	u64 kernel_gs_base;
	u64 sysenter_cs;
	u64 sysenter_esp;
	u64 sysenter_eip;
	u64 cr2;
	u8 reserved_6[32];
	u64 g_pat;
	u64 dbgctl;
	u64 br_from;
	u64 br_to;
	u64 last_excp_from;
	u64 last_excp_to;
};

struct __attribute__ ((__packed__)) vmcb {
	struct vmcb_control_area control;
	struct vmcb_save_area save;
};

#define SVM_CPUID_FEATURE_SHIFT 2
#define SVM_CPUID_FUNC 0x8000000a

#define SVM_VM_CR_SVM_DISABLE 4

#define SVM_SELECTOR_S_SHIFT 4
#define SVM_SELECTOR_DPL_SHIFT 5
#define SVM_SELECTOR_P_SHIFT 7
#define SVM_SELECTOR_AVL_SHIFT 8
#define SVM_SELECTOR_L_SHIFT 9
#define SVM_SELECTOR_DB_SHIFT 10
#define SVM_SELECTOR_G_SHIFT 11

#define SVM_SELECTOR_TYPE_MASK (0xf)
#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)

#define SVM_SELECTOR_WRITE_MASK (1 << 1)
#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
#define SVM_SELECTOR_CODE_MASK (1 << 3)

#define INTERCEPT_CR0_READ	0
#define INTERCEPT_CR3_READ	3
#define INTERCEPT_CR4_READ	4
#define INTERCEPT_CR8_READ	8
#define INTERCEPT_CR0_WRITE	(16 + 0)
#define INTERCEPT_CR3_WRITE	(16 + 3)
#define INTERCEPT_CR4_WRITE	(16 + 4)
#define INTERCEPT_CR8_WRITE	(16 + 8)

#define INTERCEPT_DR0_READ	0
#define INTERCEPT_DR1_READ	1
#define INTERCEPT_DR2_READ	2
#define INTERCEPT_DR3_READ	3
#define INTERCEPT_DR4_READ	4
#define INTERCEPT_DR5_READ	5
#define INTERCEPT_DR6_READ	6
#define INTERCEPT_DR7_READ	7
#define INTERCEPT_DR0_WRITE	(16 + 0)
#define INTERCEPT_DR1_WRITE	(16 + 1)
#define INTERCEPT_DR2_WRITE	(16 + 2)
#define INTERCEPT_DR3_WRITE	(16 + 3)
#define INTERCEPT_DR4_WRITE	(16 + 4)
#define INTERCEPT_DR5_WRITE	(16 + 5)
#define INTERCEPT_DR6_WRITE	(16 + 6)
#define INTERCEPT_DR7_WRITE	(16 + 7)

#define SVM_EVTINJ_VEC_MASK 0xff

#define SVM_EVTINJ_TYPE_SHIFT 8
#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_VALID (1 << 31)
#define SVM_EVTINJ_VALID_ERR (1 << 11)

#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK

#define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
#define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
#define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
#define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT

#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR

#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44

#define SVM_EXITINFO_REG_MASK 0x0F

#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)

#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
#define SVM_VMRUN  ".byte 0x0f, 0x01, 0xd8"
#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
#define SVM_CLGI   ".byte 0x0f, 0x01, 0xdd"
#define SVM_STGI   ".byte 0x0f, 0x01, 0xdc"
#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"

#endif
Commit	Line	Data
6aa8b732 AK	1	#ifndef __SVM_H
	2	#define __SVM_H
	3
af170c50 DH	4	#include <uapi/asm/svm.h>
af170c50 DH	5
26bf264e	6
6aa8b732 AK	7	enum {
	8	INTERCEPT_INTR,
	9	INTERCEPT_NMI,
	10	INTERCEPT_SMI,
	11	INTERCEPT_INIT,
	12	INTERCEPT_VINTR,
	13	INTERCEPT_SELECTIVE_CR0,
	14	INTERCEPT_STORE_IDTR,
	15	INTERCEPT_STORE_GDTR,
	16	INTERCEPT_STORE_LDTR,
	17	INTERCEPT_STORE_TR,
	18	INTERCEPT_LOAD_IDTR,
	19	INTERCEPT_LOAD_GDTR,
	20	INTERCEPT_LOAD_LDTR,
	21	INTERCEPT_LOAD_TR,
	22	INTERCEPT_RDTSC,
	23	INTERCEPT_RDPMC,
	24	INTERCEPT_PUSHF,
	25	INTERCEPT_POPF,
	26	INTERCEPT_CPUID,
	27	INTERCEPT_RSM,
	28	INTERCEPT_IRET,
	29	INTERCEPT_INTn,
	30	INTERCEPT_INVD,
	31	INTERCEPT_PAUSE,
	32	INTERCEPT_HLT,
	33	INTERCEPT_INVLPG,
	34	INTERCEPT_INVLPGA,
	35	INTERCEPT_IOIO_PROT,
	36	INTERCEPT_MSR_PROT,
	37	INTERCEPT_TASK_SWITCH,
	38	INTERCEPT_FERR_FREEZE,
	39	INTERCEPT_SHUTDOWN,
	40	INTERCEPT_VMRUN,
	41	INTERCEPT_VMMCALL,
	42	INTERCEPT_VMLOAD,
	43	INTERCEPT_VMSAVE,
	44	INTERCEPT_STGI,
	45	INTERCEPT_CLGI,
	46	INTERCEPT_SKINIT,
	47	INTERCEPT_RDTSCP,
	48	INTERCEPT_ICEBP,
	49	INTERCEPT_WBINVD,
916ce236 JR	50	INTERCEPT_MONITOR,
	51	INTERCEPT_MWAIT,
	52	INTERCEPT_MWAIT_COND,
81dd35d4	53	INTERCEPT_XSETBV,
6aa8b732 AK	54	};
	55
	56
	57	struct __attribute__ ((__packed__)) vmcb_control_area {
4ee546b4	58	u32 intercept_cr;
3aed041a	59	u32 intercept_dr;
6aa8b732 AK	60	u32 intercept_exceptions;
6aa8b732 AK	61	u64 intercept;
565d0998 ML	62	u8 reserved_1[42];
565d0998 ML	63	u16 pause_filter_count;
6aa8b732 AK	64	u64 iopm_base_pa;
	65	u64 msrpm_base_pa;
	66	u64 tsc_offset;
	67	u32 asid;
	68	u8 tlb_ctl;
	69	u8 reserved_2[3];
	70	u32 int_ctl;
	71	u32 int_vector;
	72	u32 int_state;
	73	u8 reserved_3[4];
	74	u32 exit_code;
	75	u32 exit_code_hi;
	76	u64 exit_info_1;
	77	u64 exit_info_2;
	78	u32 exit_int_info;
	79	u32 exit_int_info_err;
	80	u64 nested_ctl;
3d5615e5 SS	81	u64 avic_vapic_bar;
3d5615e5 SS	82	u8 reserved_4[8];
6aa8b732 AK	83	u32 event_inj;
	84	u32 event_inj_err;
	85	u64 nested_cr3;
	86	u64 lbr_ctl;
8d28fec4 RJ	87	u32 clean;
8d28fec4 RJ	88	u32 reserved_5;
6bc31bdc	89	u64 next_rip;
dc25e89e AP	90	u8 insn_len;
dc25e89e AP	91	u8 insn_bytes[15];
3d5615e5 SS	92	u64 avic_backing_page; /* Offset 0xe0 */
	93	u8 reserved_6[8]; /* Offset 0xe8 */
	94	u64 avic_logical_id; /* Offset 0xf0 */
	95	u64 avic_physical_id; /* Offset 0xf8 */
	96	u8 reserved_7[768];
6aa8b732 AK	97	};
	98
	99
	100	#define TLB_CONTROL_DO_NOTHING 0
	101	#define TLB_CONTROL_FLUSH_ALL_ASID 1
38e5e92f JR	102	#define TLB_CONTROL_FLUSH_ASID 3
38e5e92f JR	103	#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
6aa8b732 AK	104
	105	#define V_TPR_MASK 0x0f
	106
	107	#define V_IRQ_SHIFT 8
	108	#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
	109
	110	#define V_INTR_PRIO_SHIFT 16
	111	#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
	112
	113	#define V_IGN_TPR_SHIFT 20
	114	#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
	115
	116	#define V_INTR_MASKING_SHIFT 24
	117	#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
	118
44a95dae SS	119	#define AVIC_ENABLE_SHIFT 31
	120	#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
	121
6aa8b732 AK	122	#define SVM_INTERRUPT_SHADOW_MASK 1
	123
	124	#define SVM_IOIO_STR_SHIFT 2
	125	#define SVM_IOIO_REP_SHIFT 3
	126	#define SVM_IOIO_SIZE_SHIFT 4
	127	#define SVM_IOIO_ASIZE_SHIFT 7
	128
	129	#define SVM_IOIO_TYPE_MASK 1
	130	#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
	131	#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
	132	#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
	133	#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
	134
4a810181 JR	135	#define SVM_VM_CR_VALID_MASK 0x001fULL
	136	#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
	137	#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
	138
6aa8b732 AK	139	struct __attribute__ ((__packed__)) vmcb_seg {
	140	u16 selector;
	141	u16 attrib;
	142	u32 limit;
	143	u64 base;
	144	};
	145
	146	struct __attribute__ ((__packed__)) vmcb_save_area {
	147	struct vmcb_seg es;
	148	struct vmcb_seg cs;
	149	struct vmcb_seg ss;
	150	struct vmcb_seg ds;
	151	struct vmcb_seg fs;
	152	struct vmcb_seg gs;
	153	struct vmcb_seg gdtr;
	154	struct vmcb_seg ldtr;
	155	struct vmcb_seg idtr;
	156	struct vmcb_seg tr;
	157	u8 reserved_1[43];
	158	u8 cpl;
	159	u8 reserved_2[4];
	160	u64 efer;
	161	u8 reserved_3[112];
	162	u64 cr4;
	163	u64 cr3;
	164	u64 cr0;
	165	u64 dr7;
	166	u64 dr6;
	167	u64 rflags;
	168	u64 rip;
	169	u8 reserved_4[88];
	170	u64 rsp;
	171	u8 reserved_5[24];
	172	u64 rax;
	173	u64 star;
	174	u64 lstar;
	175	u64 cstar;
	176	u64 sfmask;
	177	u64 kernel_gs_base;
	178	u64 sysenter_cs;
	179	u64 sysenter_esp;
	180	u64 sysenter_eip;
	181	u64 cr2;
	182	u8 reserved_6[32];
	183	u64 g_pat;
	184	u64 dbgctl;
	185	u64 br_from;
	186	u64 br_to;
	187	u64 last_excp_from;
	188	u64 last_excp_to;
	189	};
	190
	191	struct __attribute__ ((__packed__)) vmcb {
	192	struct vmcb_control_area control;
	193	struct vmcb_save_area save;
	194	};
	195
	196	#define SVM_CPUID_FEATURE_SHIFT 2
	197	#define SVM_CPUID_FUNC 0x8000000a
	198
6031a61c JR	199	#define SVM_VM_CR_SVM_DISABLE 4
6031a61c JR	200
6aa8b732 AK	201	#define SVM_SELECTOR_S_SHIFT 4
	202	#define SVM_SELECTOR_DPL_SHIFT 5
	203	#define SVM_SELECTOR_P_SHIFT 7
	204	#define SVM_SELECTOR_AVL_SHIFT 8
	205	#define SVM_SELECTOR_L_SHIFT 9
	206	#define SVM_SELECTOR_DB_SHIFT 10
	207	#define SVM_SELECTOR_G_SHIFT 11
	208
	209	#define SVM_SELECTOR_TYPE_MASK (0xf)
	210	#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
	211	#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
	212	#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
	213	#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
	214	#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
	215	#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
	216	#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
	217
	218	#define SVM_SELECTOR_WRITE_MASK (1 << 1)
	219	#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
	220	#define SVM_SELECTOR_CODE_MASK (1 << 3)
	221
4ee546b4 RJ	222	#define INTERCEPT_CR0_READ 0
	223	#define INTERCEPT_CR3_READ 3
	224	#define INTERCEPT_CR4_READ 4
	225	#define INTERCEPT_CR8_READ 8
	226	#define INTERCEPT_CR0_WRITE (16 + 0)
	227	#define INTERCEPT_CR3_WRITE (16 + 3)
	228	#define INTERCEPT_CR4_WRITE (16 + 4)
	229	#define INTERCEPT_CR8_WRITE (16 + 8)
6aa8b732	230
3aed041a JR	231	#define INTERCEPT_DR0_READ 0
	232	#define INTERCEPT_DR1_READ 1
	233	#define INTERCEPT_DR2_READ 2
	234	#define INTERCEPT_DR3_READ 3
	235	#define INTERCEPT_DR4_READ 4
	236	#define INTERCEPT_DR5_READ 5
	237	#define INTERCEPT_DR6_READ 6
	238	#define INTERCEPT_DR7_READ 7
	239	#define INTERCEPT_DR0_WRITE (16 + 0)
	240	#define INTERCEPT_DR1_WRITE (16 + 1)
	241	#define INTERCEPT_DR2_WRITE (16 + 2)
	242	#define INTERCEPT_DR3_WRITE (16 + 3)
	243	#define INTERCEPT_DR4_WRITE (16 + 4)
	244	#define INTERCEPT_DR5_WRITE (16 + 5)
	245	#define INTERCEPT_DR6_WRITE (16 + 6)
	246	#define INTERCEPT_DR7_WRITE (16 + 7)
6aa8b732 AK	247
	248	#define SVM_EVTINJ_VEC_MASK 0xff
	249
	250	#define SVM_EVTINJ_TYPE_SHIFT 8
	251	#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
	252
	253	#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
	254	#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
	255	#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
	256	#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
	257
	258	#define SVM_EVTINJ_VALID (1 << 31)
	259	#define SVM_EVTINJ_VALID_ERR (1 << 11)
	260
	261	#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
64a7ec06	262	#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
6aa8b732 AK	263
	264	#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
	265	#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
	266	#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
	267	#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
	268
	269	#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
	270	#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
	271
37817f29 IE	272	#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
37817f29 IE	273	#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
e269fb21	274	#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
37817f29	275
7ff76d58 AP	276	#define SVM_EXITINFO_REG_MASK 0x0F
7ff76d58 AP	277
dc77270f	278	#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS \| X86_CR0_MP)
6aa8b732 AK	279
	280	#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
	281	#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
	282	#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
	283	#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
	284	#define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
	285	#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
	286
	287	#endif