[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / tlbflush.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_TLBFLUSH_H
#define _ASM_X86_TLBFLUSH_H

#include <linux/mm.h>
#include <linux/sched.h>

#include <asm/processor.h>
#include <asm/cpufeature.h>
#include <asm/special_insns.h>
#include <asm/smp.h>

static inline void __invpcid(unsigned long pcid, unsigned long addr,
			     unsigned long type)
{
	struct { u64 d[2]; } desc = { { pcid, addr } };

	/*
	 * The memory clobber is because the whole point is to invalidate
	 * stale TLB entries and, especially if we're flushing global
	 * mappings, we don't want the compiler to reorder any subsequent
	 * memory accesses before the TLB flush.
	 *
	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
	 * invpcid (%rcx), %rax in long mode.
	 */
	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
		      : : "m" (desc), "a" (type), "c" (&desc) : "memory");
}

#define INVPCID_TYPE_INDIV_ADDR		0
#define INVPCID_TYPE_SINGLE_CTXT	1
#define INVPCID_TYPE_ALL_INCL_GLOBAL	2
#define INVPCID_TYPE_ALL_NON_GLOBAL	3

/* Flush all mappings for a given pcid and addr, not including globals. */
static inline void invpcid_flush_one(unsigned long pcid,
				     unsigned long addr)
{
	__invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
}

/* Flush all mappings for a given PCID, not including globals. */
static inline void invpcid_flush_single_context(unsigned long pcid)
{
	__invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
}

/* Flush all mappings, including globals, for all PCIDs. */
static inline void invpcid_flush_all(void)
{
	__invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
}

/* Flush all mappings for all PCIDs except globals. */
static inline void invpcid_flush_all_nonglobals(void)
{
	__invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
}

static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
{
	u64 new_tlb_gen;

	/*
	 * Bump the generation count.  This also serves as a full barrier
	 * that synchronizes with switch_mm(): callers are required to order
	 * their read of mm_cpumask after their writes to the paging
	 * structures.
	 */
	smp_mb__before_atomic();
	new_tlb_gen = atomic64_inc_return(&mm->context.tlb_gen);
	smp_mb__after_atomic();

	return new_tlb_gen;
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define __flush_tlb() __native_flush_tlb()
#define __flush_tlb_global() __native_flush_tlb_global()
#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
#endif

static inline bool tlb_defer_switch_to_init_mm(void)
{
	/*
	 * If we have PCID, then switching to init_mm is reasonably
	 * fast.  If we don't have PCID, then switching to init_mm is
	 * quite slow, so we try to defer it in the hopes that we can
	 * avoid it entirely.  The latter approach runs the risk of
	 * receiving otherwise unnecessary IPIs.
	 *
	 * This choice is just a heuristic.  The tlb code can handle this
	 * function returning true or false regardless of whether we have
	 * PCID.
	 */
	return !static_cpu_has(X86_FEATURE_PCID);
}

/*
 * 6 because 6 should be plenty and struct tlb_state will fit in
 * two cache lines.
 */
#define TLB_NR_DYN_ASIDS 6

struct tlb_context {
	u64 ctx_id;
	u64 tlb_gen;
};

struct tlb_state {
	/*
	 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
	 * are on.  This means that it may not match current->active_mm,
	 * which will contain the previous user mm when we're in lazy TLB
	 * mode even if we've already switched back to swapper_pg_dir.
	 */
	struct mm_struct *loaded_mm;
	u16 loaded_mm_asid;
	u16 next_asid;

	/*
	 * We can be in one of several states:
	 *
	 *  - Actively using an mm.  Our CPU's bit will be set in
	 *    mm_cpumask(loaded_mm) and is_lazy == false;
	 *
	 *  - Not using a real mm.  loaded_mm == &init_mm.  Our CPU's bit
	 *    will not be set in mm_cpumask(&init_mm) and is_lazy == false.
	 *
	 *  - Lazily using a real mm.  loaded_mm != &init_mm, our bit
	 *    is set in mm_cpumask(loaded_mm), but is_lazy == true.
	 *    We're heuristically guessing that the CR3 load we
	 *    skipped more than makes up for the overhead added by
	 *    lazy mode.
	 */
	bool is_lazy;

	/*
	 * Access to this CR4 shadow and to H/W CR4 is protected by
	 * disabling interrupts when modifying either one.
	 */
	unsigned long cr4;

	/*
	 * This is a list of all contexts that might exist in the TLB.
	 * There is one per ASID that we use, and the ASID (what the
	 * CPU calls PCID) is the index into ctxts.
	 *
	 * For each context, ctx_id indicates which mm the TLB's user
	 * entries came from.  As an invariant, the TLB will never
	 * contain entries that are out-of-date as when that mm reached
	 * the tlb_gen in the list.
	 *
	 * To be clear, this means that it's legal for the TLB code to
	 * flush the TLB without updating tlb_gen.  This can happen
	 * (for now, at least) due to paravirt remote flushes.
	 *
	 * NB: context 0 is a bit special, since it's also used by
	 * various bits of init code.  This is fine -- code that
	 * isn't aware of PCID will end up harmlessly flushing
	 * context 0.
	 */
	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
};
DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);

/* Initialize cr4 shadow for this CPU. */
static inline void cr4_init_shadow(void)
{
	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
}

/* Set in this cpu's CR4. */
static inline void cr4_set_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	if ((cr4 | mask) != cr4) {
		cr4 |= mask;
		this_cpu_write(cpu_tlbstate.cr4, cr4);
		__write_cr4(cr4);
	}
}

/* Clear in this cpu's CR4. */
static inline void cr4_clear_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	if ((cr4 & ~mask) != cr4) {
		cr4 &= ~mask;
		this_cpu_write(cpu_tlbstate.cr4, cr4);
		__write_cr4(cr4);
	}
}

static inline void cr4_toggle_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	cr4 ^= mask;
	this_cpu_write(cpu_tlbstate.cr4, cr4);
	__write_cr4(cr4);
}

/* Read the CR4 shadow. */
static inline unsigned long cr4_read_shadow(void)
{
	return this_cpu_read(cpu_tlbstate.cr4);
}

/*
 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB
 * enable and PPro Global page enable), so that any CPU's that boot
 * up after us can get the correct flags.  This should only be used
 * during boot on the boot cpu.
 */
extern unsigned long mmu_cr4_features;
extern u32 *trampoline_cr4_features;

static inline void cr4_set_bits_and_update_boot(unsigned long mask)
{
	mmu_cr4_features |= mask;
	if (trampoline_cr4_features)
		*trampoline_cr4_features = mmu_cr4_features;
	cr4_set_bits(mask);
}

extern void initialize_tlbstate_and_flush(void);

static inline void __native_flush_tlb(void)
{
	/*
	 * If current->mm == NULL then we borrow a mm which may change during a
	 * task switch and therefore we must not be preempted while we write CR3
	 * back:
	 */
	preempt_disable();
	native_write_cr3(__native_read_cr3());
	preempt_enable();
}

static inline void __native_flush_tlb_global(void)
{
	unsigned long cr4, flags;

	if (static_cpu_has(X86_FEATURE_INVPCID)) {
		/*
		 * Using INVPCID is considerably faster than a pair of writes
		 * to CR4 sandwiched inside an IRQ flag save/restore.
		 */
		invpcid_flush_all();
		return;
	}

	/*
	 * Read-modify-write to CR4 - protect it from preemption and
	 * from interrupts. (Use the raw variant because this code can
	 * be called from deep inside debugging code.)
	 */
	raw_local_irq_save(flags);

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	/* toggle PGE */
	native_write_cr4(cr4 ^ X86_CR4_PGE);
	/* write old PGE again and flush TLBs */
	native_write_cr4(cr4);

	raw_local_irq_restore(flags);
}

static inline void __native_flush_tlb_single(unsigned long addr)
{
	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
}

static inline void __flush_tlb_all(void)
{
	if (boot_cpu_has(X86_FEATURE_PGE))
		__flush_tlb_global();
	else
		__flush_tlb();

	/*
	 * Note: if we somehow had PCID but not PGE, then this wouldn't work --
	 * we'd end up flushing kernel translations for the current ASID but
	 * we might fail to flush kernel translations for other cached ASIDs.
	 *
	 * To avoid this issue, we force PCID off if PGE is off.
	 */
}

static inline void __flush_tlb_one(unsigned long addr)
{
	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
	__flush_tlb_single(addr);
}

#define TLB_FLUSH_ALL	-1UL

/*
 * TLB flushing:
 *
 *  - flush_tlb_all() flushes all processes TLBs
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
 *  - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
 *
 * ..but the i386 has somewhat limited tlb flushing capabilities,
 * and page-granular flushes are available only on i486 and up.
 */
struct flush_tlb_info {
	/*
	 * We support several kinds of flushes.
	 *
	 * - Fully flush a single mm.  .mm will be set, .end will be
	 *   TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
	 *   which the IPI sender is trying to catch us up.
	 *
	 * - Partially flush a single mm.  .mm will be set, .start and
	 *   .end will indicate the range, and .new_tlb_gen will be set
	 *   such that the changes between generation .new_tlb_gen-1 and
	 *   .new_tlb_gen are entirely contained in the indicated range.
	 *
	 * - Fully flush all mms whose tlb_gens have been updated.  .mm
	 *   will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
	 *   will be zero.
	 */
	struct mm_struct	*mm;
	unsigned long		start;
	unsigned long		end;
	u64			new_tlb_gen;
};

#define local_flush_tlb() __flush_tlb()

#define flush_tlb_mm(mm)	flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)

#define flush_tlb_range(vma, start, end)	\
		flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)

extern void flush_tlb_all(void);
extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
				unsigned long end, unsigned long vmflag);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);

static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
{
	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
}

void native_flush_tlb_others(const struct cpumask *cpumask,
			     const struct flush_tlb_info *info);

static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
					struct mm_struct *mm)
{
	inc_mm_tlb_gen(mm);
	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
}

extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);

#ifndef CONFIG_PARAVIRT
#define flush_tlb_others(mask, info)	\
	native_flush_tlb_others(mask, info)
#endif

#endif /* _ASM_X86_TLBFLUSH_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_TLBFLUSH_H
1965aae3 PA	3	#define _ASM_X86_TLBFLUSH_H
d291cf83 TG	4
	5	#include <linux/mm.h>
	6	#include <linux/sched.h>
	7
	8	#include <asm/processor.h>
cd4d09ec	9	#include <asm/cpufeature.h>
f05e798a	10	#include <asm/special_insns.h>
ce4a4e56	11	#include <asm/smp.h>
d291cf83	12
060a402a AL	13	static inline void __invpcid(unsigned long pcid, unsigned long addr,
	14	unsigned long type)
	15	{
e2c7698c	16	struct { u64 d[2]; } desc = { { pcid, addr } };
060a402a AL	17
	18	/*
	19	* The memory clobber is because the whole point is to invalidate
	20	* stale TLB entries and, especially if we're flushing global
	21	* mappings, we don't want the compiler to reorder any subsequent
	22	* memory accesses before the TLB flush.
	23	*
	24	* The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
	25	* invpcid (%rcx), %rax in long mode.
	26	*/
	27	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
e2c7698c	28	: : "m" (desc), "a" (type), "c" (&desc) : "memory");
060a402a AL	29	}
	30
	31	#define INVPCID_TYPE_INDIV_ADDR 0
	32	#define INVPCID_TYPE_SINGLE_CTXT 1
	33	#define INVPCID_TYPE_ALL_INCL_GLOBAL 2
	34	#define INVPCID_TYPE_ALL_NON_GLOBAL 3
	35
	36	/* Flush all mappings for a given pcid and addr, not including globals. */
	37	static inline void invpcid_flush_one(unsigned long pcid,
	38	unsigned long addr)
	39	{
	40	__invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
	41	}
	42
	43	/* Flush all mappings for a given PCID, not including globals. */
	44	static inline void invpcid_flush_single_context(unsigned long pcid)
	45	{
	46	__invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
	47	}
	48
	49	/* Flush all mappings, including globals, for all PCIDs. */
	50	static inline void invpcid_flush_all(void)
	51	{
	52	__invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
	53	}
	54
	55	/* Flush all mappings for all PCIDs except globals. */
	56	static inline void invpcid_flush_all_nonglobals(void)
	57	{
	58	__invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
	59	}
	60
f39681ed AL	61	static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
	62	{
	63	u64 new_tlb_gen;
	64
	65	/*
	66	* Bump the generation count. This also serves as a full barrier
	67	* that synchronizes with switch_mm(): callers are required to order
	68	* their read of mm_cpumask after their writes to the paging
	69	* structures.
	70	*/
	71	smp_mb__before_atomic();
	72	new_tlb_gen = atomic64_inc_return(&mm->context.tlb_gen);
	73	smp_mb__after_atomic();
	74
	75	return new_tlb_gen;
	76	}
	77
d291cf83 TG	78	#ifdef CONFIG_PARAVIRT
	79	#include <asm/paravirt.h>
	80	#else
	81	#define __flush_tlb() __native_flush_tlb()
	82	#define __flush_tlb_global() __native_flush_tlb_global()
	83	#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
	84	#endif
	85
4e57b946 AL	86	static inline bool tlb_defer_switch_to_init_mm(void)
4e57b946 AL	87	{
7ac7f2c3 AL	88	/*
	89	* If we have PCID, then switching to init_mm is reasonably
	90	* fast. If we don't have PCID, then switching to init_mm is
	91	* quite slow, so we try to defer it in the hopes that we can
	92	* avoid it entirely. The latter approach runs the risk of
	93	* receiving otherwise unnecessary IPIs.
	94	*
	95	* This choice is just a heuristic. The tlb code can handle this
	96	* function returning true or false regardless of whether we have
	97	* PCID.
	98	*/
	99	return !static_cpu_has(X86_FEATURE_PCID);
4e57b946	100	}
b956575b	101
10af6235 AL	102	/*
	103	* 6 because 6 should be plenty and struct tlb_state will fit in
	104	* two cache lines.
	105	*/
	106	#define TLB_NR_DYN_ASIDS 6
	107
b0579ade AL	108	struct tlb_context {
	109	u64 ctx_id;
	110	u64 tlb_gen;
	111	};
	112
1e02ce4c	113	struct tlb_state {
3d28ebce AL	114	/*
	115	* cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
	116	* are on. This means that it may not match current->active_mm,
	117	* which will contain the previous user mm when we're in lazy TLB
	118	* mode even if we've already switched back to swapper_pg_dir.
	119	*/
	120	struct mm_struct *loaded_mm;
10af6235 AL	121	u16 loaded_mm_asid;
10af6235 AL	122	u16 next_asid;
1e02ce4c	123
b956575b AL	124	/*
	125	* We can be in one of several states:
	126	*
	127	* - Actively using an mm. Our CPU's bit will be set in
	128	* mm_cpumask(loaded_mm) and is_lazy == false;
	129	*
	130	* - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
	131	* will not be set in mm_cpumask(&init_mm) and is_lazy == false.
	132	*
	133	* - Lazily using a real mm. loaded_mm != &init_mm, our bit
	134	* is set in mm_cpumask(loaded_mm), but is_lazy == true.
	135	* We're heuristically guessing that the CR3 load we
	136	* skipped more than makes up for the overhead added by
	137	* lazy mode.
	138	*/
	139	bool is_lazy;
	140
1e02ce4c AL	141	/*
	142	* Access to this CR4 shadow and to H/W CR4 is protected by
	143	* disabling interrupts when modifying either one.
	144	*/
	145	unsigned long cr4;
b0579ade AL	146
	147	/*
	148	* This is a list of all contexts that might exist in the TLB.
10af6235 AL	149	* There is one per ASID that we use, and the ASID (what the
10af6235 AL	150	* CPU calls PCID) is the index into ctxts.
b0579ade AL	151	*
	152	* For each context, ctx_id indicates which mm the TLB's user
	153	* entries came from. As an invariant, the TLB will never
	154	* contain entries that are out-of-date as when that mm reached
	155	* the tlb_gen in the list.
	156	*
	157	* To be clear, this means that it's legal for the TLB code to
	158	* flush the TLB without updating tlb_gen. This can happen
	159	* (for now, at least) due to paravirt remote flushes.
10af6235 AL	160	*
	161	* NB: context 0 is a bit special, since it's also used by
	162	* various bits of init code. This is fine -- code that
	163	* isn't aware of PCID will end up harmlessly flushing
	164	* context 0.
b0579ade	165	*/
10af6235	166	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
1e02ce4c AL	167	};
	168	DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
	169
	170	/* Initialize cr4 shadow for this CPU. */
	171	static inline void cr4_init_shadow(void)
	172	{
1ef55be1	173	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
1e02ce4c AL	174	}
1e02ce4c AL	175
375074cc AL	176	/* Set in this cpu's CR4. */
	177	static inline void cr4_set_bits(unsigned long mask)
	178	{
	179	unsigned long cr4;
	180
1e02ce4c AL	181	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	182	if ((cr4 \| mask) != cr4) {
	183	cr4 \|= mask;
	184	this_cpu_write(cpu_tlbstate.cr4, cr4);
	185	__write_cr4(cr4);
	186	}
375074cc AL	187	}
	188
	189	/* Clear in this cpu's CR4. */
	190	static inline void cr4_clear_bits(unsigned long mask)
	191	{
	192	unsigned long cr4;
	193
1e02ce4c AL	194	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	195	if ((cr4 & ~mask) != cr4) {
	196	cr4 &= ~mask;
	197	this_cpu_write(cpu_tlbstate.cr4, cr4);
	198	__write_cr4(cr4);
	199	}
	200	}
	201
5a920155 TG	202	static inline void cr4_toggle_bits(unsigned long mask)
	203	{
	204	unsigned long cr4;
	205
	206	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	207	cr4 ^= mask;
	208	this_cpu_write(cpu_tlbstate.cr4, cr4);
	209	__write_cr4(cr4);
	210	}
	211
1e02ce4c AL	212	/* Read the CR4 shadow. */
	213	static inline unsigned long cr4_read_shadow(void)
	214	{
	215	return this_cpu_read(cpu_tlbstate.cr4);
375074cc AL	216	}
	217
	218	/*
	219	* Save some of cr4 feature set we're using (e.g. Pentium 4MB
	220	* enable and PPro Global page enable), so that any CPU's that boot
	221	* up after us can get the correct flags. This should only be used
	222	* during boot on the boot cpu.
	223	*/
	224	extern unsigned long mmu_cr4_features;
	225	extern u32 *trampoline_cr4_features;
	226
	227	static inline void cr4_set_bits_and_update_boot(unsigned long mask)
	228	{
	229	mmu_cr4_features \|= mask;
	230	if (trampoline_cr4_features)
	231	*trampoline_cr4_features = mmu_cr4_features;
	232	cr4_set_bits(mask);
	233	}
	234
72c0098d AL	235	extern void initialize_tlbstate_and_flush(void);
72c0098d AL	236
d291cf83 TG	237	static inline void __native_flush_tlb(void)
d291cf83 TG	238	{
5cf0791d SAS	239	/*
	240	* If current->mm == NULL then we borrow a mm which may change during a
	241	* task switch and therefore we must not be preempted while we write CR3
	242	* back:
	243	*/
	244	preempt_disable();
6c690ee1	245	native_write_cr3(__native_read_cr3());
5cf0791d	246	preempt_enable();
d291cf83 TG	247	}
	248
	249	static inline void __native_flush_tlb_global(void)
	250	{
23cb7d46	251	unsigned long cr4, flags;
d291cf83	252
d8bced79 AL	253	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	254	/*
	255	* Using INVPCID is considerably faster than a pair of writes
	256	* to CR4 sandwiched inside an IRQ flag save/restore.
	257	*/
	258	invpcid_flush_all();
	259	return;
	260	}
	261
b1979a5f IM	262	/*
	263	* Read-modify-write to CR4 - protect it from preemption and
	264	* from interrupts. (Use the raw variant because this code can
	265	* be called from deep inside debugging code.)
	266	*/
	267	raw_local_irq_save(flags);
	268
23cb7d46 PZ	269	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	270	/* toggle PGE */
	271	native_write_cr4(cr4 ^ X86_CR4_PGE);
	272	/* write old PGE again and flush TLBs */
	273	native_write_cr4(cr4);
b1979a5f IM	274
b1979a5f IM	275	raw_local_irq_restore(flags);
d291cf83 TG	276	}
	277
	278	static inline void __native_flush_tlb_single(unsigned long addr)
	279	{
94cf8de0	280	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
d291cf83 TG	281	}
	282
	283	static inline void __flush_tlb_all(void)
	284	{
2c4ea6e2	285	if (boot_cpu_has(X86_FEATURE_PGE))
d291cf83 TG	286	__flush_tlb_global();
	287	else
	288	__flush_tlb();
660da7c9 AL	289
	290	/*
	291	* Note: if we somehow had PCID but not PGE, then this wouldn't work --
	292	* we'd end up flushing kernel translations for the current ASID but
	293	* we might fail to flush kernel translations for other cached ASIDs.
	294	*
	295	* To avoid this issue, we force PCID off if PGE is off.
	296	*/
d291cf83 TG	297	}
	298
	299	static inline void __flush_tlb_one(unsigned long addr)
	300	{
ec659934	301	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
e8747f10	302	__flush_tlb_single(addr);
d291cf83 TG	303	}
d291cf83 TG	304
3e7f3db0	305	#define TLB_FLUSH_ALL -1UL
d291cf83 TG	306
	307	/*
	308	* TLB flushing:
	309	*
d291cf83 TG	310	* - flush_tlb_all() flushes all processes TLBs
	311	* - flush_tlb_mm(mm) flushes the specified mm context TLB's
	312	* - flush_tlb_page(vma, vmaddr) flushes one page
	313	* - flush_tlb_range(vma, start, end) flushes a range of pages
	314	* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
a2055abe	315	* - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
d291cf83 TG	316	*
	317	* ..but the i386 has somewhat limited tlb flushing capabilities,
	318	* and page-granular flushes are available only on i486 and up.
d291cf83	319	*/
a2055abe	320	struct flush_tlb_info {
b0579ade AL	321	/*
	322	* We support several kinds of flushes.
	323	*
	324	* - Fully flush a single mm. .mm will be set, .end will be
	325	* TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
	326	* which the IPI sender is trying to catch us up.
	327	*
	328	* - Partially flush a single mm. .mm will be set, .start and
	329	* .end will indicate the range, and .new_tlb_gen will be set
	330	* such that the changes between generation .new_tlb_gen-1 and
	331	* .new_tlb_gen are entirely contained in the indicated range.
	332	*
	333	* - Fully flush all mms whose tlb_gens have been updated. .mm
	334	* will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
	335	* will be zero.
	336	*/
	337	struct mm_struct *mm;
	338	unsigned long start;
	339	unsigned long end;
	340	u64 new_tlb_gen;
a2055abe AL	341	};
a2055abe AL	342
d291cf83 TG	343	#define local_flush_tlb() __flush_tlb()
d291cf83 TG	344
611ae8e3 AS	345	#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
	346
	347	#define flush_tlb_range(vma, start, end) \
	348	flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
	349
d291cf83	350	extern void flush_tlb_all(void);
611ae8e3 AS	351	extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
611ae8e3 AS	352	unsigned long end, unsigned long vmflag);
effee4b9	353	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
d291cf83	354
ca6c99c0 AL	355	static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
	356	{
	357	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
	358	}
	359
4595f962	360	void native_flush_tlb_others(const struct cpumask *cpumask,
a2055abe	361	const struct flush_tlb_info *info);
d291cf83	362
e73ad5ff AL	363	static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
	364	struct mm_struct *mm)
	365	{
f39681ed	366	inc_mm_tlb_gen(mm);
e73ad5ff AL	367	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
	368	}
	369
	370	extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
	371
d291cf83	372	#ifndef CONFIG_PARAVIRT
a2055abe AL	373	#define flush_tlb_others(mask, info) \
a2055abe AL	374	native_flush_tlb_others(mask, info)
96a388de	375	#endif
d291cf83	376
1965aae3	377	#endif /* _ASM_X86_TLBFLUSH_H */