[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / tlbflush.h

#ifndef _ASM_X86_TLBFLUSH_H
#define _ASM_X86_TLBFLUSH_H

#include <linux/mm.h>
#include <linux/sched.h>

#include <asm/processor.h>
#include <asm/cpufeature.h>
#include <asm/special_insns.h>

static inline void __invpcid(unsigned long pcid, unsigned long addr,
			     unsigned long type)
{
	struct { u64 d[2]; } desc = { { pcid, addr } };

	/*
	 * The memory clobber is because the whole point is to invalidate
	 * stale TLB entries and, especially if we're flushing global
	 * mappings, we don't want the compiler to reorder any subsequent
	 * memory accesses before the TLB flush.
	 *
	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
	 * invpcid (%rcx), %rax in long mode.
	 */
	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
		      : : "m" (desc), "a" (type), "c" (&desc) : "memory");
}

#define INVPCID_TYPE_INDIV_ADDR		0
#define INVPCID_TYPE_SINGLE_CTXT	1
#define INVPCID_TYPE_ALL_INCL_GLOBAL	2
#define INVPCID_TYPE_ALL_NON_GLOBAL	3

/* Flush all mappings for a given pcid and addr, not including globals. */
static inline void invpcid_flush_one(unsigned long pcid,
				     unsigned long addr)
{
	__invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
}

/* Flush all mappings for a given PCID, not including globals. */
static inline void invpcid_flush_single_context(unsigned long pcid)
{
	__invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
}

/* Flush all mappings, including globals, for all PCIDs. */
static inline void invpcid_flush_all(void)
{
	__invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
}

/* Flush all mappings for all PCIDs except globals. */
static inline void invpcid_flush_all_nonglobals(void)
{
	__invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define __flush_tlb() __native_flush_tlb()
#define __flush_tlb_global() __native_flush_tlb_global()
#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
#endif

struct tlb_state {
#ifdef CONFIG_SMP
	struct mm_struct *active_mm;
	int state;
#endif

	/*
	 * Access to this CR4 shadow and to H/W CR4 is protected by
	 * disabling interrupts when modifying either one.
	 */
	unsigned long cr4;
};
DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);

/* Initialize cr4 shadow for this CPU. */
static inline void cr4_init_shadow(void)
{
	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
}

/* Set in this cpu's CR4. */
static inline void cr4_set_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	if ((cr4 | mask) != cr4) {
		cr4 |= mask;
		this_cpu_write(cpu_tlbstate.cr4, cr4);
		__write_cr4(cr4);
	}
}

/* Clear in this cpu's CR4. */
static inline void cr4_clear_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	if ((cr4 & ~mask) != cr4) {
		cr4 &= ~mask;
		this_cpu_write(cpu_tlbstate.cr4, cr4);
		__write_cr4(cr4);
	}
}

static inline void cr4_toggle_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	cr4 ^= mask;
	this_cpu_write(cpu_tlbstate.cr4, cr4);
	__write_cr4(cr4);
}

/* Read the CR4 shadow. */
static inline unsigned long cr4_read_shadow(void)
{
	return this_cpu_read(cpu_tlbstate.cr4);
}

/*
 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB
 * enable and PPro Global page enable), so that any CPU's that boot
 * up after us can get the correct flags.  This should only be used
 * during boot on the boot cpu.
 */
extern unsigned long mmu_cr4_features;
extern u32 *trampoline_cr4_features;

static inline void cr4_set_bits_and_update_boot(unsigned long mask)
{
	mmu_cr4_features |= mask;
	if (trampoline_cr4_features)
		*trampoline_cr4_features = mmu_cr4_features;
	cr4_set_bits(mask);
}

static inline void __native_flush_tlb(void)
{
	/*
	 * If current->mm == NULL then we borrow a mm which may change during a
	 * task switch and therefore we must not be preempted while we write CR3
	 * back:
	 */
	preempt_disable();
	native_write_cr3(native_read_cr3());
	preempt_enable();
}

static inline void __native_flush_tlb_global_irq_disabled(void)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	/* clear PGE */
	native_write_cr4(cr4 & ~X86_CR4_PGE);
	/* write old PGE again and flush TLBs */
	native_write_cr4(cr4);
}

static inline void __native_flush_tlb_global(void)
{
	unsigned long flags;

	if (static_cpu_has(X86_FEATURE_INVPCID)) {
		/*
		 * Using INVPCID is considerably faster than a pair of writes
		 * to CR4 sandwiched inside an IRQ flag save/restore.
		 */
		invpcid_flush_all();
		return;
	}

	/*
	 * Read-modify-write to CR4 - protect it from preemption and
	 * from interrupts. (Use the raw variant because this code can
	 * be called from deep inside debugging code.)
	 */
	raw_local_irq_save(flags);

	__native_flush_tlb_global_irq_disabled();

	raw_local_irq_restore(flags);
}

static inline void __native_flush_tlb_single(unsigned long addr)
{
	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
}

static inline void __flush_tlb_all(void)
{
	if (boot_cpu_has(X86_FEATURE_PGE))
		__flush_tlb_global();
	else
		__flush_tlb();
}

static inline void __flush_tlb_one(unsigned long addr)
{
	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
	__flush_tlb_single(addr);
}

#define TLB_FLUSH_ALL	-1UL

/*
 * TLB flushing:
 *
 *  - flush_tlb_all() flushes all processes TLBs
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
 *  - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
 *
 * ..but the i386 has somewhat limited tlb flushing capabilities,
 * and page-granular flushes are available only on i486 and up.
 */

#ifndef CONFIG_SMP

/* "_up" is for UniProcessor.
 *
 * This is a helper for other header functions.  *Not* intended to be called
 * directly.  All global TLB flushes need to either call this, or to bump the
 * vm statistics themselves.
 */
static inline void __flush_tlb_up(void)
{
	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
	__flush_tlb();
}

static inline void flush_tlb_all(void)
{
	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
	__flush_tlb_all();
}

static inline void local_flush_tlb(void)
{
	__flush_tlb_up();
}

static inline void flush_tlb_mm(struct mm_struct *mm)
{
	if (mm == current->active_mm)
		__flush_tlb_up();
}

static inline void flush_tlb_page(struct vm_area_struct *vma,
				  unsigned long addr)
{
	if (vma->vm_mm == current->active_mm)
		__flush_tlb_one(addr);
}

static inline void flush_tlb_range(struct vm_area_struct *vma,
				   unsigned long start, unsigned long end)
{
	if (vma->vm_mm == current->active_mm)
		__flush_tlb_up();
}

static inline void flush_tlb_mm_range(struct mm_struct *mm,
	   unsigned long start, unsigned long end, unsigned long vmflag)
{
	if (mm == current->active_mm)
		__flush_tlb_up();
}

static inline void native_flush_tlb_others(const struct cpumask *cpumask,
					   struct mm_struct *mm,
					   unsigned long start,
					   unsigned long end)
{
}

static inline void reset_lazy_tlbstate(void)
{
}

static inline void flush_tlb_kernel_range(unsigned long start,
					  unsigned long end)
{
	flush_tlb_all();
}

#else  /* SMP */

#include <asm/smp.h>

#define local_flush_tlb() __flush_tlb()

#define flush_tlb_mm(mm)	flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)

#define flush_tlb_range(vma, start, end)	\
		flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)

extern void flush_tlb_all(void);
extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
				unsigned long end, unsigned long vmflag);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);

static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
{
	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
}

void native_flush_tlb_others(const struct cpumask *cpumask,
				struct mm_struct *mm,
				unsigned long start, unsigned long end);

#define TLBSTATE_OK	1
#define TLBSTATE_LAZY	2

static inline void reset_lazy_tlbstate(void)
{
	this_cpu_write(cpu_tlbstate.state, 0);
	this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
}

static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
					struct mm_struct *mm)
{
	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
}

extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);

#endif	/* SMP */

#ifndef CONFIG_PARAVIRT
#define flush_tlb_others(mask, mm, start, end)	\
	native_flush_tlb_others(mask, mm, start, end)
#endif

#endif /* _ASM_X86_TLBFLUSH_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_TLBFLUSH_H
1965aae3 PA	2	#define _ASM_X86_TLBFLUSH_H
d291cf83 TG	3
	4	#include <linux/mm.h>
	5	#include <linux/sched.h>
	6
	7	#include <asm/processor.h>
cd4d09ec	8	#include <asm/cpufeature.h>
f05e798a	9	#include <asm/special_insns.h>
d291cf83	10
060a402a AL	11	static inline void __invpcid(unsigned long pcid, unsigned long addr,
	12	unsigned long type)
	13	{
e2c7698c	14	struct { u64 d[2]; } desc = { { pcid, addr } };
060a402a AL	15
	16	/*
	17	* The memory clobber is because the whole point is to invalidate
	18	* stale TLB entries and, especially if we're flushing global
	19	* mappings, we don't want the compiler to reorder any subsequent
	20	* memory accesses before the TLB flush.
	21	*
	22	* The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
	23	* invpcid (%rcx), %rax in long mode.
	24	*/
	25	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
e2c7698c	26	: : "m" (desc), "a" (type), "c" (&desc) : "memory");
060a402a AL	27	}
	28
	29	#define INVPCID_TYPE_INDIV_ADDR 0
	30	#define INVPCID_TYPE_SINGLE_CTXT 1
	31	#define INVPCID_TYPE_ALL_INCL_GLOBAL 2
	32	#define INVPCID_TYPE_ALL_NON_GLOBAL 3
	33
	34	/* Flush all mappings for a given pcid and addr, not including globals. */
	35	static inline void invpcid_flush_one(unsigned long pcid,
	36	unsigned long addr)
	37	{
	38	__invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
	39	}
	40
	41	/* Flush all mappings for a given PCID, not including globals. */
	42	static inline void invpcid_flush_single_context(unsigned long pcid)
	43	{
	44	__invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
	45	}
	46
	47	/* Flush all mappings, including globals, for all PCIDs. */
	48	static inline void invpcid_flush_all(void)
	49	{
	50	__invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
	51	}
	52
	53	/* Flush all mappings for all PCIDs except globals. */
	54	static inline void invpcid_flush_all_nonglobals(void)
	55	{
	56	__invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
	57	}
	58
d291cf83 TG	59	#ifdef CONFIG_PARAVIRT
	60	#include <asm/paravirt.h>
	61	#else
	62	#define __flush_tlb() __native_flush_tlb()
	63	#define __flush_tlb_global() __native_flush_tlb_global()
	64	#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
	65	#endif
	66
1e02ce4c AL	67	struct tlb_state {
	68	#ifdef CONFIG_SMP
	69	struct mm_struct *active_mm;
	70	int state;
	71	#endif
	72
	73	/*
	74	* Access to this CR4 shadow and to H/W CR4 is protected by
	75	* disabling interrupts when modifying either one.
	76	*/
	77	unsigned long cr4;
	78	};
	79	DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
	80
	81	/* Initialize cr4 shadow for this CPU. */
	82	static inline void cr4_init_shadow(void)
	83	{
1ef55be1	84	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
1e02ce4c AL	85	}
1e02ce4c AL	86
375074cc AL	87	/* Set in this cpu's CR4. */
	88	static inline void cr4_set_bits(unsigned long mask)
	89	{
	90	unsigned long cr4;
	91
1e02ce4c AL	92	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	93	if ((cr4 \| mask) != cr4) {
	94	cr4 \|= mask;
	95	this_cpu_write(cpu_tlbstate.cr4, cr4);
	96	__write_cr4(cr4);
	97	}
375074cc AL	98	}
	99
	100	/* Clear in this cpu's CR4. */
	101	static inline void cr4_clear_bits(unsigned long mask)
	102	{
	103	unsigned long cr4;
	104
1e02ce4c AL	105	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	106	if ((cr4 & ~mask) != cr4) {
	107	cr4 &= ~mask;
	108	this_cpu_write(cpu_tlbstate.cr4, cr4);
	109	__write_cr4(cr4);
	110	}
	111	}
	112
5a920155 TG	113	static inline void cr4_toggle_bits(unsigned long mask)
	114	{
	115	unsigned long cr4;
	116
	117	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	118	cr4 ^= mask;
	119	this_cpu_write(cpu_tlbstate.cr4, cr4);
	120	__write_cr4(cr4);
	121	}
	122
1e02ce4c AL	123	/* Read the CR4 shadow. */
	124	static inline unsigned long cr4_read_shadow(void)
	125	{
	126	return this_cpu_read(cpu_tlbstate.cr4);
375074cc AL	127	}
	128
	129	/*
	130	* Save some of cr4 feature set we're using (e.g. Pentium 4MB
	131	* enable and PPro Global page enable), so that any CPU's that boot
	132	* up after us can get the correct flags. This should only be used
	133	* during boot on the boot cpu.
	134	*/
	135	extern unsigned long mmu_cr4_features;
	136	extern u32 *trampoline_cr4_features;
	137
	138	static inline void cr4_set_bits_and_update_boot(unsigned long mask)
	139	{
	140	mmu_cr4_features \|= mask;
	141	if (trampoline_cr4_features)
	142	*trampoline_cr4_features = mmu_cr4_features;
	143	cr4_set_bits(mask);
	144	}
	145
d291cf83 TG	146	static inline void __native_flush_tlb(void)
d291cf83 TG	147	{
5cf0791d SAS	148	/*
	149	* If current->mm == NULL then we borrow a mm which may change during a
	150	* task switch and therefore we must not be preempted while we write CR3
	151	* back:
	152	*/
	153	preempt_disable();
d7285c6b	154	native_write_cr3(native_read_cr3());
5cf0791d	155	preempt_enable();
d291cf83 TG	156	}
d291cf83 TG	157
086fc8f8 FY	158	static inline void __native_flush_tlb_global_irq_disabled(void)
	159	{
	160	unsigned long cr4;
	161
1e02ce4c	162	cr4 = this_cpu_read(cpu_tlbstate.cr4);
086fc8f8 FY	163	/* clear PGE */
	164	native_write_cr4(cr4 & ~X86_CR4_PGE);
	165	/* write old PGE again and flush TLBs */
	166	native_write_cr4(cr4);
	167	}
	168
d291cf83 TG	169	static inline void __native_flush_tlb_global(void)
d291cf83 TG	170	{
b1979a5f	171	unsigned long flags;
d291cf83	172
d8bced79 AL	173	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	174	/*
	175	* Using INVPCID is considerably faster than a pair of writes
	176	* to CR4 sandwiched inside an IRQ flag save/restore.
	177	*/
	178	invpcid_flush_all();
	179	return;
	180	}
	181
b1979a5f IM	182	/*
	183	* Read-modify-write to CR4 - protect it from preemption and
	184	* from interrupts. (Use the raw variant because this code can
	185	* be called from deep inside debugging code.)
	186	*/
	187	raw_local_irq_save(flags);
	188
086fc8f8	189	__native_flush_tlb_global_irq_disabled();
b1979a5f IM	190
b1979a5f IM	191	raw_local_irq_restore(flags);
d291cf83 TG	192	}
	193
	194	static inline void __native_flush_tlb_single(unsigned long addr)
	195	{
94cf8de0	196	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
d291cf83 TG	197	}
	198
	199	static inline void __flush_tlb_all(void)
	200	{
2c4ea6e2	201	if (boot_cpu_has(X86_FEATURE_PGE))
d291cf83 TG	202	__flush_tlb_global();
	203	else
	204	__flush_tlb();
	205	}
	206
	207	static inline void __flush_tlb_one(unsigned long addr)
	208	{
ec659934	209	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
e8747f10	210	__flush_tlb_single(addr);
d291cf83 TG	211	}
d291cf83 TG	212
3e7f3db0	213	#define TLB_FLUSH_ALL -1UL
d291cf83 TG	214
	215	/*
	216	* TLB flushing:
	217	*
d291cf83 TG	218	* - flush_tlb_all() flushes all processes TLBs
	219	* - flush_tlb_mm(mm) flushes the specified mm context TLB's
	220	* - flush_tlb_page(vma, vmaddr) flushes one page
	221	* - flush_tlb_range(vma, start, end) flushes a range of pages
	222	* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
e7b52ffd	223	* - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
d291cf83 TG	224	*
	225	* ..but the i386 has somewhat limited tlb flushing capabilities,
	226	* and page-granular flushes are available only on i486 and up.
d291cf83 TG	227	*/
	228
	229	#ifndef CONFIG_SMP
	230
6df46865 DH	231	/* "_up" is for UniProcessor.
	232	*
	233	* This is a helper for other header functions. Not intended to be called
	234	* directly. All global TLB flushes need to either call this, or to bump the
	235	* vm statistics themselves.
	236	*/
	237	static inline void __flush_tlb_up(void)
	238	{
ec659934	239	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
6df46865 DH	240	__flush_tlb();
	241	}
	242
	243	static inline void flush_tlb_all(void)
	244	{
ec659934	245	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
6df46865 DH	246	__flush_tlb_all();
	247	}
	248
6df46865 DH	249	static inline void local_flush_tlb(void)
	250	{
	251	__flush_tlb_up();
	252	}
d291cf83 TG	253
	254	static inline void flush_tlb_mm(struct mm_struct *mm)
	255	{
	256	if (mm == current->active_mm)
6df46865	257	__flush_tlb_up();
d291cf83 TG	258	}
	259
	260	static inline void flush_tlb_page(struct vm_area_struct *vma,
	261	unsigned long addr)
	262	{
	263	if (vma->vm_mm == current->active_mm)
	264	__flush_tlb_one(addr);
	265	}
	266
	267	static inline void flush_tlb_range(struct vm_area_struct *vma,
	268	unsigned long start, unsigned long end)
	269	{
	270	if (vma->vm_mm == current->active_mm)
6df46865	271	__flush_tlb_up();
d291cf83 TG	272	}
d291cf83 TG	273
7efa1c87	274	static inline void flush_tlb_mm_range(struct mm_struct *mm,
611ae8e3 AS	275	unsigned long start, unsigned long end, unsigned long vmflag)
611ae8e3 AS	276	{
7efa1c87	277	if (mm == current->active_mm)
6df46865	278	__flush_tlb_up();
611ae8e3 AS	279	}
611ae8e3 AS	280
4595f962	281	static inline void native_flush_tlb_others(const struct cpumask *cpumask,
d291cf83	282	struct mm_struct *mm,
e7b52ffd AS	283	unsigned long start,
e7b52ffd AS	284	unsigned long end)
d291cf83 TG	285	{
	286	}
	287
913da64b AN	288	static inline void reset_lazy_tlbstate(void)
	289	{
	290	}
	291
effee4b9 AS	292	static inline void flush_tlb_kernel_range(unsigned long start,
	293	unsigned long end)
	294	{
	295	flush_tlb_all();
	296	}
	297
d291cf83 TG	298	#else /* SMP */
	299
	300	#include <asm/smp.h>
	301
	302	#define local_flush_tlb() __flush_tlb()
	303
611ae8e3 AS	304	#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
	305
	306	#define flush_tlb_range(vma, start, end) \
	307	flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
	308
d291cf83	309	extern void flush_tlb_all(void);
611ae8e3 AS	310	extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
611ae8e3 AS	311	unsigned long end, unsigned long vmflag);
effee4b9	312	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
d291cf83	313
ca6c99c0 AL	314	static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
	315	{
	316	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
	317	}
	318
4595f962	319	void native_flush_tlb_others(const struct cpumask *cpumask,
e7b52ffd AS	320	struct mm_struct *mm,
e7b52ffd AS	321	unsigned long start, unsigned long end);
d291cf83 TG	322
	323	#define TLBSTATE_OK 1
	324	#define TLBSTATE_LAZY 2
	325
913da64b AN	326	static inline void reset_lazy_tlbstate(void)
913da64b AN	327	{
c6ae41e7 AS	328	this_cpu_write(cpu_tlbstate.state, 0);
c6ae41e7 AS	329	this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
913da64b	330	}
d291cf83	331
e73ad5ff AL	332	static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
	333	struct mm_struct *mm)
	334	{
	335	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
	336	}
	337
	338	extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
	339
d291cf83 TG	340	#endif /* SMP */
	341
	342	#ifndef CONFIG_PARAVIRT
e7b52ffd AS	343	#define flush_tlb_others(mask, mm, start, end) \
e7b52ffd AS	344	native_flush_tlb_others(mask, mm, start, end)
96a388de	345	#endif
d291cf83	346
1965aae3	347	#endif /* _ASM_X86_TLBFLUSH_H */