[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / tlbflush.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_TLBFLUSH_H
#define _ASM_X86_TLBFLUSH_H

#include <linux/mm.h>
#include <linux/sched.h>

#include <asm/processor.h>
#include <asm/cpufeature.h>
#include <asm/special_insns.h>
#include <asm/smp.h>
#include <asm/invpcid.h>
#include <asm/pti.h>
#include <asm/processor-flags.h>

/*
 * The x86 feature is called PCID (Process Context IDentifier). It is similar
 * to what is traditionally called ASID on the RISC processors.
 *
 * We don't use the traditional ASID implementation, where each process/mm gets
 * its own ASID and flush/restart when we run out of ASID space.
 *
 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
 * that came by on this CPU, allowing cheaper switch_mm between processes on
 * this CPU.
 *
 * We end up with different spaces for different things. To avoid confusion we
 * use different names for each of them:
 *
 * ASID  - [0, TLB_NR_DYN_ASIDS-1]
 *         the canonical identifier for an mm
 *
 * kPCID - [1, TLB_NR_DYN_ASIDS]
 *         the value we write into the PCID part of CR3; corresponds to the
 *         ASID+1, because PCID 0 is special.
 *
 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
 *         for KPTI each mm has two address spaces and thus needs two
 *         PCID values, but we can still do with a single ASID denomination
 *         for each mm. Corresponds to kPCID + 2048.
 *
 */

/* There are 12 bits of space for ASIDS in CR3 */
#define CR3_HW_ASID_BITS		12

/*
 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
 * user/kernel switches
 */
#ifdef CONFIG_PAGE_TABLE_ISOLATION
# define PTI_CONSUMED_PCID_BITS	1
#else
# define PTI_CONSUMED_PCID_BITS	0
#endif

#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)

/*
 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
 * for them being zero-based.  Another -1 is because PCID 0 is reserved for
 * use by non-PCID-aware users.
 */
#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)

/*
 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
 * lines.
 */
#define TLB_NR_DYN_ASIDS	6

/*
 * Given @asid, compute kPCID
 */
static inline u16 kern_pcid(u16 asid)
{
	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);

#ifdef CONFIG_PAGE_TABLE_ISOLATION
	/*
	 * Make sure that the dynamic ASID space does not confict with the
	 * bit we are using to switch between user and kernel ASIDs.
	 */
	BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_SWITCH_BIT));

	/*
	 * The ASID being passed in here should have respected the
	 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
	 */
	VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_SWITCH_BIT));
#endif
	/*
	 * The dynamically-assigned ASIDs that get passed in are small
	 * (<TLB_NR_DYN_ASIDS).  They never have the high switch bit set,
	 * so do not bother to clear it.
	 *
	 * If PCID is on, ASID-aware code paths put the ASID+1 into the
	 * PCID bits.  This serves two purposes.  It prevents a nasty
	 * situation in which PCID-unaware code saves CR3, loads some other
	 * value (with PCID == 0), and then restores CR3, thus corrupting
	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means
	 * that any bugs involving loading a PCID-enabled CR3 with
	 * CR4.PCIDE off will trigger deterministically.
	 */
	return asid + 1;
}

/*
 * Given @asid, compute uPCID
 */
static inline u16 user_pcid(u16 asid)
{
	u16 ret = kern_pcid(asid);
#ifdef CONFIG_PAGE_TABLE_ISOLATION
	ret |= 1 << X86_CR3_PTI_SWITCH_BIT;
#endif
	return ret;
}

struct pgd_t;
static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
{
	if (static_cpu_has(X86_FEATURE_PCID)) {
		return __sme_pa(pgd) | kern_pcid(asid);
	} else {
		VM_WARN_ON_ONCE(asid != 0);
		return __sme_pa(pgd);
	}
}

static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
{
	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
	VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));
	return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define __flush_tlb() __native_flush_tlb()
#define __flush_tlb_global() __native_flush_tlb_global()
#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
#endif

static inline bool tlb_defer_switch_to_init_mm(void)
{
	/*
	 * If we have PCID, then switching to init_mm is reasonably
	 * fast.  If we don't have PCID, then switching to init_mm is
	 * quite slow, so we try to defer it in the hopes that we can
	 * avoid it entirely.  The latter approach runs the risk of
	 * receiving otherwise unnecessary IPIs.
	 *
	 * This choice is just a heuristic.  The tlb code can handle this
	 * function returning true or false regardless of whether we have
	 * PCID.
	 */
	return !static_cpu_has(X86_FEATURE_PCID);
}

struct tlb_context {
	u64 ctx_id;
	u64 tlb_gen;
};

struct tlb_state {
	/*
	 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
	 * are on.  This means that it may not match current->active_mm,
	 * which will contain the previous user mm when we're in lazy TLB
	 * mode even if we've already switched back to swapper_pg_dir.
	 */
	struct mm_struct *loaded_mm;
	u16 loaded_mm_asid;
	u16 next_asid;

	/*
	 * We can be in one of several states:
	 *
	 *  - Actively using an mm.  Our CPU's bit will be set in
	 *    mm_cpumask(loaded_mm) and is_lazy == false;
	 *
	 *  - Not using a real mm.  loaded_mm == &init_mm.  Our CPU's bit
	 *    will not be set in mm_cpumask(&init_mm) and is_lazy == false.
	 *
	 *  - Lazily using a real mm.  loaded_mm != &init_mm, our bit
	 *    is set in mm_cpumask(loaded_mm), but is_lazy == true.
	 *    We're heuristically guessing that the CR3 load we
	 *    skipped more than makes up for the overhead added by
	 *    lazy mode.
	 */
	bool is_lazy;

	/*
	 * If set we changed the page tables in such a way that we
	 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
	 * This tells us to go invalidate all the non-loaded ctxs[]
	 * on the next context switch.
	 *
	 * The current ctx was kept up-to-date as it ran and does not
	 * need to be invalidated.
	 */
	bool invalidate_other;

	/*
	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
	 * the corresponding user PCID needs a flush next time we
	 * switch to it; see SWITCH_TO_USER_CR3.
	 */
	unsigned short user_pcid_flush_mask;

	/*
	 * Access to this CR4 shadow and to H/W CR4 is protected by
	 * disabling interrupts when modifying either one.
	 */
	unsigned long cr4;

	/*
	 * This is a list of all contexts that might exist in the TLB.
	 * There is one per ASID that we use, and the ASID (what the
	 * CPU calls PCID) is the index into ctxts.
	 *
	 * For each context, ctx_id indicates which mm the TLB's user
	 * entries came from.  As an invariant, the TLB will never
	 * contain entries that are out-of-date as when that mm reached
	 * the tlb_gen in the list.
	 *
	 * To be clear, this means that it's legal for the TLB code to
	 * flush the TLB without updating tlb_gen.  This can happen
	 * (for now, at least) due to paravirt remote flushes.
	 *
	 * NB: context 0 is a bit special, since it's also used by
	 * various bits of init code.  This is fine -- code that
	 * isn't aware of PCID will end up harmlessly flushing
	 * context 0.
	 */
	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
};
DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);

/* Initialize cr4 shadow for this CPU. */
static inline void cr4_init_shadow(void)
{
	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
}

/* Set in this cpu's CR4. */
static inline void cr4_set_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	if ((cr4 | mask) != cr4) {
		cr4 |= mask;
		this_cpu_write(cpu_tlbstate.cr4, cr4);
		__write_cr4(cr4);
	}
}

/* Clear in this cpu's CR4. */
static inline void cr4_clear_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	if ((cr4 & ~mask) != cr4) {
		cr4 &= ~mask;
		this_cpu_write(cpu_tlbstate.cr4, cr4);
		__write_cr4(cr4);
	}
}

static inline void cr4_toggle_bits(unsigned long mask)
{
	unsigned long cr4;

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	cr4 ^= mask;
	this_cpu_write(cpu_tlbstate.cr4, cr4);
	__write_cr4(cr4);
}

/* Read the CR4 shadow. */
static inline unsigned long cr4_read_shadow(void)
{
	return this_cpu_read(cpu_tlbstate.cr4);
}

/*
 * Mark all other ASIDs as invalid, preserves the current.
 */
static inline void invalidate_other_asid(void)
{
	this_cpu_write(cpu_tlbstate.invalidate_other, true);
}

/*
 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB
 * enable and PPro Global page enable), so that any CPU's that boot
 * up after us can get the correct flags.  This should only be used
 * during boot on the boot cpu.
 */
extern unsigned long mmu_cr4_features;
extern u32 *trampoline_cr4_features;

static inline void cr4_set_bits_and_update_boot(unsigned long mask)
{
	mmu_cr4_features |= mask;
	if (trampoline_cr4_features)
		*trampoline_cr4_features = mmu_cr4_features;
	cr4_set_bits(mask);
}

extern void initialize_tlbstate_and_flush(void);

/*
 * Given an ASID, flush the corresponding user ASID.  We can delay this
 * until the next time we switch to it.
 *
 * See SWITCH_TO_USER_CR3.
 */
static inline void invalidate_user_asid(u16 asid)
{
	/* There is no user ASID if address space separation is off */
	if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
		return;

	/*
	 * We only have a single ASID if PCID is off and the CR3
	 * write will have flushed it.
	 */
	if (!cpu_feature_enabled(X86_FEATURE_PCID))
		return;

	if (!static_cpu_has(X86_FEATURE_PTI))
		return;

	__set_bit(kern_pcid(asid),
		  (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
}

/*
 * flush the entire current user mapping
 */
static inline void __native_flush_tlb(void)
{
	/*
	 * Preemption or interrupts must be disabled to protect the access
	 * to the per CPU variable and to prevent being preempted between
	 * read_cr3() and write_cr3().
	 */
	WARN_ON_ONCE(preemptible());

	invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));

	/* If current->mm == NULL then the read_cr3() "borrows" an mm */
	native_write_cr3(__native_read_cr3());
}

/*
 * flush everything
 */
static inline void __native_flush_tlb_global(void)
{
	unsigned long cr4, flags;

	if (static_cpu_has(X86_FEATURE_INVPCID)) {
		/*
		 * Using INVPCID is considerably faster than a pair of writes
		 * to CR4 sandwiched inside an IRQ flag save/restore.
		 *
		 * Note, this works with CR4.PCIDE=0 or 1.
		 */
		invpcid_flush_all();
		return;
	}

	/*
	 * Read-modify-write to CR4 - protect it from preemption and
	 * from interrupts. (Use the raw variant because this code can
	 * be called from deep inside debugging code.)
	 */
	raw_local_irq_save(flags);

	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	/* toggle PGE */
	native_write_cr4(cr4 ^ X86_CR4_PGE);
	/* write old PGE again and flush TLBs */
	native_write_cr4(cr4);

	raw_local_irq_restore(flags);
}

/*
 * flush one page in the user mapping
 */
static inline void __native_flush_tlb_single(unsigned long addr)
{
	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);

	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");

	if (!static_cpu_has(X86_FEATURE_PTI))
		return;

	/*
	 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
	 * Just use invalidate_user_asid() in case we are called early.
	 */
	if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
		invalidate_user_asid(loaded_mm_asid);
	else
		invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
}

/*
 * flush everything
 */
static inline void __flush_tlb_all(void)
{
	if (boot_cpu_has(X86_FEATURE_PGE)) {
		__flush_tlb_global();
	} else {
		/*
		 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
		 */
		__flush_tlb();
	}
}

/*
 * flush one page in the kernel mapping
 */
static inline void __flush_tlb_one(unsigned long addr)
{
	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
	__flush_tlb_single(addr);

	if (!static_cpu_has(X86_FEATURE_PTI))
		return;

	/*
	 * __flush_tlb_single() will have cleared the TLB entry for this ASID,
	 * but since kernel space is replicated across all, we must also
	 * invalidate all others.
	 */
	invalidate_other_asid();
}

#define TLB_FLUSH_ALL	-1UL

/*
 * TLB flushing:
 *
 *  - flush_tlb_all() flushes all processes TLBs
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(vma, start, end) flushes a range of pages
 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
 *  - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
 *
 * ..but the i386 has somewhat limited tlb flushing capabilities,
 * and page-granular flushes are available only on i486 and up.
 */
struct flush_tlb_info {
	/*
	 * We support several kinds of flushes.
	 *
	 * - Fully flush a single mm.  .mm will be set, .end will be
	 *   TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
	 *   which the IPI sender is trying to catch us up.
	 *
	 * - Partially flush a single mm.  .mm will be set, .start and
	 *   .end will indicate the range, and .new_tlb_gen will be set
	 *   such that the changes between generation .new_tlb_gen-1 and
	 *   .new_tlb_gen are entirely contained in the indicated range.
	 *
	 * - Fully flush all mms whose tlb_gens have been updated.  .mm
	 *   will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
	 *   will be zero.
	 */
	struct mm_struct	*mm;
	unsigned long		start;
	unsigned long		end;
	u64			new_tlb_gen;
};

#define local_flush_tlb() __flush_tlb()

#define flush_tlb_mm(mm)	flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)

#define flush_tlb_range(vma, start, end)	\
		flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)

extern void flush_tlb_all(void);
extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
				unsigned long end, unsigned long vmflag);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);

static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
{
	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
}

void native_flush_tlb_others(const struct cpumask *cpumask,
			     const struct flush_tlb_info *info);

static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
{
	/*
	 * Bump the generation count.  This also serves as a full barrier
	 * that synchronizes with switch_mm(): callers are required to order
	 * their read of mm_cpumask after their writes to the paging
	 * structures.
	 */
	return atomic64_inc_return(&mm->context.tlb_gen);
}

static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
					struct mm_struct *mm)
{
	inc_mm_tlb_gen(mm);
	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
}

extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);

#ifndef CONFIG_PARAVIRT
#define flush_tlb_others(mask, info)	\
	native_flush_tlb_others(mask, info)
#endif

#endif /* _ASM_X86_TLBFLUSH_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_TLBFLUSH_H
1965aae3 PA	3	#define _ASM_X86_TLBFLUSH_H
d291cf83 TG	4
	5	#include <linux/mm.h>
	6	#include <linux/sched.h>
	7
	8	#include <asm/processor.h>
cd4d09ec	9	#include <asm/cpufeature.h>
f05e798a	10	#include <asm/special_insns.h>
ce4a4e56	11	#include <asm/smp.h>
1a3b0cae	12	#include <asm/invpcid.h>
6fd166aa PZ	13	#include <asm/pti.h>
6fd166aa PZ	14	#include <asm/processor-flags.h>
060a402a	15
0a126abd PZ	16	/*
	17	* The x86 feature is called PCID (Process Context IDentifier). It is similar
	18	* to what is traditionally called ASID on the RISC processors.
	19	*
	20	* We don't use the traditional ASID implementation, where each process/mm gets
	21	* its own ASID and flush/restart when we run out of ASID space.
	22	*
	23	* Instead we have a small per-cpu array of ASIDs and cache the last few mm's
	24	* that came by on this CPU, allowing cheaper switch_mm between processes on
	25	* this CPU.
	26	*
	27	* We end up with different spaces for different things. To avoid confusion we
	28	* use different names for each of them:
	29	*
	30	* ASID - [0, TLB_NR_DYN_ASIDS-1]
	31	* the canonical identifier for an mm
	32	*
	33	* kPCID - [1, TLB_NR_DYN_ASIDS]
	34	* the value we write into the PCID part of CR3; corresponds to the
	35	* ASID+1, because PCID 0 is special.
	36	*
	37	* uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
	38	* for KPTI each mm has two address spaces and thus needs two
	39	* PCID values, but we can still do with a single ASID denomination
	40	* for each mm. Corresponds to kPCID + 2048.
	41	*
	42	*/
f39681ed	43
cb0a9144 DH	44	/* There are 12 bits of space for ASIDS in CR3 */
cb0a9144 DH	45	#define CR3_HW_ASID_BITS 12
6fd166aa	46
cb0a9144 DH	47	/*
	48	* When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
	49	* user/kernel switches
	50	*/
6fd166aa PZ	51	#ifdef CONFIG_PAGE_TABLE_ISOLATION
	52	# define PTI_CONSUMED_PCID_BITS 1
	53	#else
	54	# define PTI_CONSUMED_PCID_BITS 0
	55	#endif
	56
	57	#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
cb0a9144	58
cb0a9144 DH	59	/*
cb0a9144 DH	60	* ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
0a126abd	61	* for them being zero-based. Another -1 is because PCID 0 is reserved for
cb0a9144 DH	62	* use by non-PCID-aware users.
cb0a9144 DH	63	*/
6fd166aa PZ	64	#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
	65
	66	/*
	67	* 6 because 6 should be plenty and struct tlb_state will fit in two cache
	68	* lines.
	69	*/
	70	#define TLB_NR_DYN_ASIDS 6
cb0a9144	71
0a126abd PZ	72	/*
	73	* Given @asid, compute kPCID
	74	*/
dd95f1a4 DH	75	static inline u16 kern_pcid(u16 asid)
	76	{
	77	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
6fd166aa PZ	78
6fd166aa PZ	79	#ifdef CONFIG_PAGE_TABLE_ISOLATION
dd95f1a4	80	/*
6fd166aa PZ	81	* Make sure that the dynamic ASID space does not confict with the
	82	* bit we are using to switch between user and kernel ASIDs.
	83	*/
	84	BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_SWITCH_BIT));
	85
	86	/*
	87	* The ASID being passed in here should have respected the
	88	* MAX_ASID_AVAILABLE and thus never have the switch bit set.
	89	*/
	90	VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_SWITCH_BIT));
	91	#endif
	92	/*
	93	* The dynamically-assigned ASIDs that get passed in are small
	94	* (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
	95	* so do not bother to clear it.
	96	*
dd95f1a4 DH	97	* If PCID is on, ASID-aware code paths put the ASID+1 into the
	98	* PCID bits. This serves two purposes. It prevents a nasty
	99	* situation in which PCID-unaware code saves CR3, loads some other
	100	* value (with PCID == 0), and then restores CR3, thus corrupting
	101	* the TLB for ASID 0 if the saved ASID was nonzero. It also means
	102	* that any bugs involving loading a PCID-enabled CR3 with
	103	* CR4.PCIDE off will trigger deterministically.
	104	*/
	105	return asid + 1;
	106	}
	107
6cff64b8	108	/*
0a126abd	109	* Given @asid, compute uPCID
6cff64b8 DH	110	*/
	111	static inline u16 user_pcid(u16 asid)
	112	{
	113	u16 ret = kern_pcid(asid);
	114	#ifdef CONFIG_PAGE_TABLE_ISOLATION
	115	ret \|= 1 << X86_CR3_PTI_SWITCH_BIT;
	116	#endif
	117	return ret;
	118	}
	119
50fb83a6 DH	120	struct pgd_t;
	121	static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
	122	{
	123	if (static_cpu_has(X86_FEATURE_PCID)) {
dd95f1a4	124	return __sme_pa(pgd) \| kern_pcid(asid);
50fb83a6 DH	125	} else {
	126	VM_WARN_ON_ONCE(asid != 0);
	127	return __sme_pa(pgd);
	128	}
	129	}
	130
	131	static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
	132	{
cb0a9144	133	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
dd95f1a4 DH	134	VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));
dd95f1a4 DH	135	return __sme_pa(pgd) \| kern_pcid(asid) \| CR3_NOFLUSH;
50fb83a6 DH	136	}
50fb83a6 DH	137
d291cf83 TG	138	#ifdef CONFIG_PARAVIRT
	139	#include <asm/paravirt.h>
	140	#else
	141	#define __flush_tlb() __native_flush_tlb()
	142	#define __flush_tlb_global() __native_flush_tlb_global()
	143	#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
	144	#endif
	145
4e57b946 AL	146	static inline bool tlb_defer_switch_to_init_mm(void)
4e57b946 AL	147	{
7ac7f2c3 AL	148	/*
	149	* If we have PCID, then switching to init_mm is reasonably
	150	* fast. If we don't have PCID, then switching to init_mm is
	151	* quite slow, so we try to defer it in the hopes that we can
	152	* avoid it entirely. The latter approach runs the risk of
	153	* receiving otherwise unnecessary IPIs.
	154	*
	155	* This choice is just a heuristic. The tlb code can handle this
	156	* function returning true or false regardless of whether we have
	157	* PCID.
	158	*/
	159	return !static_cpu_has(X86_FEATURE_PCID);
4e57b946	160	}
b956575b	161
b0579ade AL	162	struct tlb_context {
	163	u64 ctx_id;
	164	u64 tlb_gen;
	165	};
	166
1e02ce4c	167	struct tlb_state {
3d28ebce AL	168	/*
	169	* cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
	170	* are on. This means that it may not match current->active_mm,
	171	* which will contain the previous user mm when we're in lazy TLB
	172	* mode even if we've already switched back to swapper_pg_dir.
	173	*/
	174	struct mm_struct *loaded_mm;
10af6235 AL	175	u16 loaded_mm_asid;
10af6235 AL	176	u16 next_asid;
1e02ce4c	177
b956575b AL	178	/*
	179	* We can be in one of several states:
	180	*
	181	* - Actively using an mm. Our CPU's bit will be set in
	182	* mm_cpumask(loaded_mm) and is_lazy == false;
	183	*
	184	* - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
	185	* will not be set in mm_cpumask(&init_mm) and is_lazy == false.
	186	*
	187	* - Lazily using a real mm. loaded_mm != &init_mm, our bit
	188	* is set in mm_cpumask(loaded_mm), but is_lazy == true.
	189	* We're heuristically guessing that the CR3 load we
	190	* skipped more than makes up for the overhead added by
	191	* lazy mode.
	192	*/
	193	bool is_lazy;
	194
2ea907c4 DH	195	/*
	196	* If set we changed the page tables in such a way that we
	197	* needed an invalidation of all contexts (aka. PCIDs / ASIDs).
	198	* This tells us to go invalidate all the non-loaded ctxs[]
	199	* on the next context switch.
	200	*
	201	* The current ctx was kept up-to-date as it ran and does not
	202	* need to be invalidated.
	203	*/
	204	bool invalidate_other;
	205
6fd166aa PZ	206	/*
	207	* Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
	208	* the corresponding user PCID needs a flush next time we
	209	* switch to it; see SWITCH_TO_USER_CR3.
	210	*/
	211	unsigned short user_pcid_flush_mask;
	212
1e02ce4c AL	213	/*
	214	* Access to this CR4 shadow and to H/W CR4 is protected by
	215	* disabling interrupts when modifying either one.
	216	*/
	217	unsigned long cr4;
b0579ade AL	218
	219	/*
	220	* This is a list of all contexts that might exist in the TLB.
10af6235 AL	221	* There is one per ASID that we use, and the ASID (what the
10af6235 AL	222	* CPU calls PCID) is the index into ctxts.
b0579ade AL	223	*
	224	* For each context, ctx_id indicates which mm the TLB's user
	225	* entries came from. As an invariant, the TLB will never
	226	* contain entries that are out-of-date as when that mm reached
	227	* the tlb_gen in the list.
	228	*
	229	* To be clear, this means that it's legal for the TLB code to
	230	* flush the TLB without updating tlb_gen. This can happen
	231	* (for now, at least) due to paravirt remote flushes.
10af6235 AL	232	*
	233	* NB: context 0 is a bit special, since it's also used by
	234	* various bits of init code. This is fine -- code that
	235	* isn't aware of PCID will end up harmlessly flushing
	236	* context 0.
b0579ade	237	*/
10af6235	238	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
1e02ce4c AL	239	};
	240	DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
	241
	242	/* Initialize cr4 shadow for this CPU. */
	243	static inline void cr4_init_shadow(void)
	244	{
1ef55be1	245	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
1e02ce4c AL	246	}
1e02ce4c AL	247
375074cc AL	248	/* Set in this cpu's CR4. */
	249	static inline void cr4_set_bits(unsigned long mask)
	250	{
	251	unsigned long cr4;
	252
1e02ce4c AL	253	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	254	if ((cr4 \| mask) != cr4) {
	255	cr4 \|= mask;
	256	this_cpu_write(cpu_tlbstate.cr4, cr4);
	257	__write_cr4(cr4);
	258	}
375074cc AL	259	}
	260
	261	/* Clear in this cpu's CR4. */
	262	static inline void cr4_clear_bits(unsigned long mask)
	263	{
	264	unsigned long cr4;
	265
1e02ce4c AL	266	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	267	if ((cr4 & ~mask) != cr4) {
	268	cr4 &= ~mask;
	269	this_cpu_write(cpu_tlbstate.cr4, cr4);
	270	__write_cr4(cr4);
	271	}
	272	}
	273
5a920155 TG	274	static inline void cr4_toggle_bits(unsigned long mask)
	275	{
	276	unsigned long cr4;
	277
	278	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	279	cr4 ^= mask;
	280	this_cpu_write(cpu_tlbstate.cr4, cr4);
	281	__write_cr4(cr4);
	282	}
	283
1e02ce4c AL	284	/* Read the CR4 shadow. */
	285	static inline unsigned long cr4_read_shadow(void)
	286	{
	287	return this_cpu_read(cpu_tlbstate.cr4);
375074cc AL	288	}
375074cc AL	289
2ea907c4 DH	290	/*
	291	* Mark all other ASIDs as invalid, preserves the current.
	292	*/
	293	static inline void invalidate_other_asid(void)
	294	{
	295	this_cpu_write(cpu_tlbstate.invalidate_other, true);
	296	}
	297
375074cc AL	298	/*
	299	* Save some of cr4 feature set we're using (e.g. Pentium 4MB
	300	* enable and PPro Global page enable), so that any CPU's that boot
	301	* up after us can get the correct flags. This should only be used
	302	* during boot on the boot cpu.
	303	*/
	304	extern unsigned long mmu_cr4_features;
	305	extern u32 *trampoline_cr4_features;
	306
	307	static inline void cr4_set_bits_and_update_boot(unsigned long mask)
	308	{
	309	mmu_cr4_features \|= mask;
	310	if (trampoline_cr4_features)
	311	*trampoline_cr4_features = mmu_cr4_features;
	312	cr4_set_bits(mask);
	313	}
	314
72c0098d AL	315	extern void initialize_tlbstate_and_flush(void);
72c0098d AL	316
6fd166aa PZ	317	/*
	318	* Given an ASID, flush the corresponding user ASID. We can delay this
	319	* until the next time we switch to it.
	320	*
	321	* See SWITCH_TO_USER_CR3.
	322	*/
	323	static inline void invalidate_user_asid(u16 asid)
	324	{
	325	/* There is no user ASID if address space separation is off */
	326	if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
	327	return;
	328
	329	/*
	330	* We only have a single ASID if PCID is off and the CR3
	331	* write will have flushed it.
	332	*/
	333	if (!cpu_feature_enabled(X86_FEATURE_PCID))
	334	return;
	335
	336	if (!static_cpu_has(X86_FEATURE_PTI))
	337	return;
	338
	339	__set_bit(kern_pcid(asid),
	340	(unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
	341	}
	342
3f67af51 PZ	343	/*
	344	* flush the entire current user mapping
	345	*/
d291cf83 TG	346	static inline void __native_flush_tlb(void)
d291cf83 TG	347	{
5cf0791d	348	/*
decab088 TG	349	* Preemption or interrupts must be disabled to protect the access
	350	* to the per CPU variable and to prevent being preempted between
	351	* read_cr3() and write_cr3().
5cf0791d	352	*/
decab088 TG	353	WARN_ON_ONCE(preemptible());
	354
	355	invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
	356
	357	/* If current->mm == NULL then the read_cr3() "borrows" an mm */
6c690ee1	358	native_write_cr3(__native_read_cr3());
d291cf83 TG	359	}
d291cf83 TG	360
3f67af51 PZ	361	/*
	362	* flush everything
	363	*/
d291cf83 TG	364	static inline void __native_flush_tlb_global(void)
d291cf83 TG	365	{
23cb7d46	366	unsigned long cr4, flags;
d291cf83	367
d8bced79 AL	368	if (static_cpu_has(X86_FEATURE_INVPCID)) {
	369	/*
	370	* Using INVPCID is considerably faster than a pair of writes
	371	* to CR4 sandwiched inside an IRQ flag save/restore.
6cff64b8 DH	372	*
6cff64b8 DH	373	* Note, this works with CR4.PCIDE=0 or 1.
d8bced79 AL	374	*/
	375	invpcid_flush_all();
	376	return;
	377	}
	378
b1979a5f IM	379	/*
	380	* Read-modify-write to CR4 - protect it from preemption and
	381	* from interrupts. (Use the raw variant because this code can
	382	* be called from deep inside debugging code.)
	383	*/
	384	raw_local_irq_save(flags);
	385
23cb7d46 PZ	386	cr4 = this_cpu_read(cpu_tlbstate.cr4);
	387	/* toggle PGE */
	388	native_write_cr4(cr4 ^ X86_CR4_PGE);
	389	/* write old PGE again and flush TLBs */
	390	native_write_cr4(cr4);
b1979a5f IM	391
b1979a5f IM	392	raw_local_irq_restore(flags);
d291cf83 TG	393	}
d291cf83 TG	394
3f67af51 PZ	395	/*
	396	* flush one page in the user mapping
	397	*/
d291cf83 TG	398	static inline void __native_flush_tlb_single(unsigned long addr)
d291cf83 TG	399	{
6fd166aa PZ	400	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
6fd166aa PZ	401
94cf8de0	402	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
6fd166aa PZ	403
	404	if (!static_cpu_has(X86_FEATURE_PTI))
	405	return;
	406
6cff64b8 DH	407	/*
	408	* Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
	409	* Just use invalidate_user_asid() in case we are called early.
	410	*/
	411	if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
	412	invalidate_user_asid(loaded_mm_asid);
	413	else
	414	invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
d291cf83 TG	415	}
d291cf83 TG	416
3f67af51 PZ	417	/*
	418	* flush everything
	419	*/
d291cf83 TG	420	static inline void __flush_tlb_all(void)
d291cf83 TG	421	{
3f67af51	422	if (boot_cpu_has(X86_FEATURE_PGE)) {
d291cf83	423	__flush_tlb_global();
3f67af51 PZ	424	} else {
	425	/*
	426	* !PGE -> !PCID (setup_pcid()), thus every flush is total.
	427	*/
d291cf83	428	__flush_tlb();
3f67af51	429	}
d291cf83 TG	430	}
d291cf83 TG	431
3f67af51 PZ	432	/*
	433	* flush one page in the kernel mapping
	434	*/
d291cf83 TG	435	static inline void __flush_tlb_one(unsigned long addr)
d291cf83 TG	436	{
ec659934	437	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
e8747f10	438	__flush_tlb_single(addr);
2ea907c4 DH	439
	440	if (!static_cpu_has(X86_FEATURE_PTI))
	441	return;
	442
	443	/*
	444	* __flush_tlb_single() will have cleared the TLB entry for this ASID,
	445	* but since kernel space is replicated across all, we must also
	446	* invalidate all others.
	447	*/
	448	invalidate_other_asid();
d291cf83 TG	449	}
d291cf83 TG	450
3e7f3db0	451	#define TLB_FLUSH_ALL -1UL
d291cf83 TG	452
	453	/*
	454	* TLB flushing:
	455	*
d291cf83 TG	456	* - flush_tlb_all() flushes all processes TLBs
	457	* - flush_tlb_mm(mm) flushes the specified mm context TLB's
	458	* - flush_tlb_page(vma, vmaddr) flushes one page
	459	* - flush_tlb_range(vma, start, end) flushes a range of pages
	460	* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
a2055abe	461	* - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
d291cf83 TG	462	*
	463	* ..but the i386 has somewhat limited tlb flushing capabilities,
	464	* and page-granular flushes are available only on i486 and up.
d291cf83	465	*/
a2055abe	466	struct flush_tlb_info {
b0579ade AL	467	/*
	468	* We support several kinds of flushes.
	469	*
	470	* - Fully flush a single mm. .mm will be set, .end will be
	471	* TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
	472	* which the IPI sender is trying to catch us up.
	473	*
	474	* - Partially flush a single mm. .mm will be set, .start and
	475	* .end will indicate the range, and .new_tlb_gen will be set
	476	* such that the changes between generation .new_tlb_gen-1 and
	477	* .new_tlb_gen are entirely contained in the indicated range.
	478	*
	479	* - Fully flush all mms whose tlb_gens have been updated. .mm
	480	* will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
	481	* will be zero.
	482	*/
	483	struct mm_struct *mm;
	484	unsigned long start;
	485	unsigned long end;
	486	u64 new_tlb_gen;
a2055abe AL	487	};
a2055abe AL	488
d291cf83 TG	489	#define local_flush_tlb() __flush_tlb()
d291cf83 TG	490
611ae8e3 AS	491	#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
	492
	493	#define flush_tlb_range(vma, start, end) \
	494	flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
	495
d291cf83	496	extern void flush_tlb_all(void);
611ae8e3 AS	497	extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
611ae8e3 AS	498	unsigned long end, unsigned long vmflag);
effee4b9	499	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
d291cf83	500
ca6c99c0 AL	501	static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
	502	{
	503	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
	504	}
	505
4595f962	506	void native_flush_tlb_others(const struct cpumask *cpumask,
a2055abe	507	const struct flush_tlb_info *info);
d291cf83	508
0a126abd PZ	509	static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
	510	{
	511	/*
	512	* Bump the generation count. This also serves as a full barrier
	513	* that synchronizes with switch_mm(): callers are required to order
	514	* their read of mm_cpumask after their writes to the paging
	515	* structures.
	516	*/
	517	return atomic64_inc_return(&mm->context.tlb_gen);
	518	}
	519
e73ad5ff AL	520	static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
	521	struct mm_struct *mm)
	522	{
f39681ed	523	inc_mm_tlb_gen(mm);
e73ad5ff AL	524	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
	525	}
	526
	527	extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
	528
d291cf83	529	#ifndef CONFIG_PARAVIRT
a2055abe AL	530	#define flush_tlb_others(mask, info) \
a2055abe AL	531	native_flush_tlb_others(mask, info)
96a388de	532	#endif
d291cf83	533
1965aae3	534	#endif /* _ASM_X86_TLBFLUSH_H */