projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2272b0e0 | 2 | /* |
| 2f0798a3 | 3 | * x86 TSC related functions |
| 2272b0e0 | 4 | */ |
| 1965aae3 PA |
5 | #ifndef _ASM_X86_TSC_H |
| 6 | #define _ASM_X86_TSC_H | |
| 2272b0e0 AS |
7 | |
| 8 | #include <asm/processor.h> | |
| 9 | ||
| 2f0798a3 TG |
10 | #define NS_SCALE 10 /* 2^10, carefully chosen */ |
| 11 | #define US_SCALE 32 /* 2^32, arbitralrily chosen */ | |
| 12 | ||
| 2272b0e0 AS |
13 | /* |
| 14 | * Standard way to access the cycle counter. | |
| 15 | */ | |
| 16 | typedef unsigned long long cycles_t; | |
| 17 | ||
| 18 | extern unsigned int cpu_khz; | |
| 19 | extern unsigned int tsc_khz; | |
| 73018a66 GOC |
20 | |
| 21 | extern void disable_TSC(void); | |
| 2272b0e0 AS |
22 | |
| 23 | static inline cycles_t get_cycles(void) | |
| 24 | { | |
| 2272b0e0 | 25 | #ifndef CONFIG_X86_TSC |
| 59e21e3d | 26 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
| 2272b0e0 AS |
27 | return 0; |
| 28 | #endif | |
| 2272b0e0 | 29 | |
| 4ea1636b | 30 | return rdtsc(); |
| 6d63de8d | 31 | } |
| 4e87173e | 32 | |
| a5a1d1c2 | 33 | extern struct system_counterval_t convert_art_to_tsc(u64 art); |
| f9677e0f | 34 | |
| eb496063 | 35 | extern void tsc_early_delay_calibrate(void); |
| 2272b0e0 | 36 | extern void tsc_init(void); |
| 5a90cf20 | 37 | extern void mark_tsc_unstable(char *reason); |
| 2272b0e0 | 38 | extern int unsynchronized_tsc(void); |
| 2d826404 | 39 | extern int check_tsc_unstable(void); |
| 341102c3 | 40 | extern void mark_tsc_async_resets(char *reason); |
| aa297292 | 41 | extern unsigned long native_calibrate_cpu(void); |
| 2d826404 | 42 | extern unsigned long native_calibrate_tsc(void); |
| a94cab23 | 43 | extern unsigned long long native_sched_clock_from_tsc(u64 tsc); |
| 2272b0e0 | 44 | |
| 28a00184 | 45 | extern int tsc_clocksource_reliable; |
| c0fc9b13 | 46 | #ifdef CONFIG_X86_TSC |
| 341102c3 | 47 | extern bool tsc_async_resets; |
| c0fc9b13 TG |
48 | #else |
| 49 | # define tsc_async_resets false | |
| 50 | #endif | |
| 28a00184 | 51 | |
| 2272b0e0 AS |
52 | /* |
| 53 | * Boot-time check whether the TSCs are synchronized across | |
| 54 | * all CPUs/cores: | |
| 55 | */ | |
| 8b223bc7 | 56 | #ifdef CONFIG_X86_TSC |
| 5bae1562 | 57 | extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); |
| 6a369583 | 58 | extern void tsc_verify_tsc_adjust(bool resume); |
| b8365543 TG |
59 | extern void check_tsc_sync_source(int cpu); |
| 60 | extern void check_tsc_sync_target(void); | |
| 8b223bc7 | 61 | #else |
| 5bae1562 | 62 | static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } |
| 6a369583 | 63 | static inline void tsc_verify_tsc_adjust(bool resume) { } |
| b8365543 TG |
64 | static inline void check_tsc_sync_source(int cpu) { } |
| 65 | static inline void check_tsc_sync_target(void) { } | |
| 8b223bc7 TG |
66 | #endif |
| 67 | ||
| 80ca9c98 | 68 | extern int notsc_setup(char *); |
| b74f05d6 MT |
69 | extern void tsc_save_sched_clock_state(void); |
| 70 | extern void tsc_restore_sched_clock_state(void); | |
| d371698e | 71 | |
| 02c0cd2d | 72 | unsigned long cpu_khz_from_msr(void); |
| 7da7c156 | 73 | |
| 1965aae3 | 74 | #endif /* _ASM_X86_TSC_H */ |