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Commit | Line | Data |
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952cf6d7 JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV architectural definitions | |
7 | * | |
9f5314fb | 8 | * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. |
952cf6d7 JS |
9 | */ |
10 | ||
05e4d316 PA |
11 | #ifndef _ASM_X86_UV_UV_HUB_H |
12 | #define _ASM_X86_UV_UV_HUB_H | |
952cf6d7 | 13 | |
bc5d9940 | 14 | #ifdef CONFIG_X86_64 |
952cf6d7 JS |
15 | #include <linux/numa.h> |
16 | #include <linux/percpu.h> | |
c08b6acc | 17 | #include <linux/timer.h> |
8dc579e8 | 18 | #include <linux/io.h> |
952cf6d7 JS |
19 | #include <asm/types.h> |
20 | #include <asm/percpu.h> | |
66666e50 | 21 | #include <asm/uv/uv_mmrs.h> |
02dd0a06 RH |
22 | #include <asm/irq_vectors.h> |
23 | #include <asm/io_apic.h> | |
952cf6d7 JS |
24 | |
25 | ||
26 | /* | |
27 | * Addressing Terminology | |
28 | * | |
9f5314fb JS |
29 | * M - The low M bits of a physical address represent the offset |
30 | * into the blade local memory. RAM memory on a blade is physically | |
31 | * contiguous (although various IO spaces may punch holes in | |
32 | * it).. | |
952cf6d7 | 33 | * |
39d30770 MT |
34 | * N - Number of bits in the node portion of a socket physical |
35 | * address. | |
9f5314fb | 36 | * |
39d30770 MT |
37 | * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of |
38 | * routers always have low bit of 1, C/MBricks have low bit | |
39 | * equal to 0. Most addressing macros that target UV hub chips | |
40 | * right shift the NASID by 1 to exclude the always-zero bit. | |
41 | * NASIDs contain up to 15 bits. | |
9f5314fb JS |
42 | * |
43 | * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead | |
44 | * of nasids. | |
45 | * | |
39d30770 MT |
46 | * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant |
47 | * of the nasid for socket usage. | |
9f5314fb JS |
48 | * |
49 | * | |
50 | * NumaLink Global Physical Address Format: | |
51 | * +--------------------------------+---------------------+ | |
52 | * |00..000| GNODE | NodeOffset | | |
53 | * +--------------------------------+---------------------+ | |
54 | * |<-------53 - M bits --->|<--------M bits -----> | |
55 | * | |
56 | * M - number of node offset bits (35 .. 40) | |
952cf6d7 JS |
57 | * |
58 | * | |
59 | * Memory/UV-HUB Processor Socket Address Format: | |
9f5314fb JS |
60 | * +----------------+---------------+---------------------+ |
61 | * |00..000000000000| PNODE | NodeOffset | | |
62 | * +----------------+---------------+---------------------+ | |
63 | * <--- N bits --->|<--------M bits -----> | |
952cf6d7 | 64 | * |
9f5314fb JS |
65 | * M - number of node offset bits (35 .. 40) |
66 | * N - number of PNODE bits (0 .. 10) | |
952cf6d7 JS |
67 | * |
68 | * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). | |
69 | * The actual values are configuration dependent and are set at | |
9f5314fb JS |
70 | * boot time. M & N values are set by the hardware/BIOS at boot. |
71 | * | |
952cf6d7 JS |
72 | * |
73 | * APICID format | |
39d30770 MT |
74 | * NOTE!!!!!! This is the current format of the APICID. However, code |
75 | * should assume that this will change in the future. Use functions | |
76 | * in this file for all APICID bit manipulations and conversion. | |
952cf6d7 | 77 | * |
39d30770 MT |
78 | * 1111110000000000 |
79 | * 5432109876543210 | |
9f5314fb | 80 | * pppppppppplc0cch |
952cf6d7 JS |
81 | * sssssssssss |
82 | * | |
9f5314fb | 83 | * p = pnode bits |
952cf6d7 JS |
84 | * l = socket number on board |
85 | * c = core | |
86 | * h = hyperthread | |
9f5314fb | 87 | * s = bits that are in the SOCKET_ID CSR |
952cf6d7 JS |
88 | * |
89 | * Note: Processor only supports 12 bits in the APICID register. The ACPI | |
90 | * tables hold all 16 bits. Software needs to be aware of this. | |
91 | * | |
39d30770 MT |
92 | * Unless otherwise specified, all references to APICID refer to |
93 | * the FULL value contained in ACPI tables, not the subset in the | |
94 | * processor APICID register. | |
952cf6d7 JS |
95 | */ |
96 | ||
97 | ||
98 | /* | |
99 | * Maximum number of bricks in all partitions and in all coherency domains. | |
100 | * This is the total number of bricks accessible in the numalink fabric. It | |
101 | * includes all C & M bricks. Routers are NOT included. | |
102 | * | |
103 | * This value is also the value of the maximum number of non-router NASIDs | |
104 | * in the numalink fabric. | |
105 | * | |
9f5314fb | 106 | * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. |
952cf6d7 JS |
107 | */ |
108 | #define UV_MAX_NUMALINK_BLADES 16384 | |
109 | ||
110 | /* | |
111 | * Maximum number of C/Mbricks within a software SSI (hardware may support | |
112 | * more). | |
113 | */ | |
114 | #define UV_MAX_SSI_BLADES 256 | |
115 | ||
116 | /* | |
117 | * The largest possible NASID of a C or M brick (+ 2) | |
118 | */ | |
1d21e6e3 | 119 | #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) |
952cf6d7 | 120 | |
7f1baa06 MT |
121 | struct uv_scir_s { |
122 | struct timer_list timer; | |
123 | unsigned long offset; | |
124 | unsigned long last; | |
125 | unsigned long idle_on; | |
126 | unsigned long idle_off; | |
127 | unsigned char state; | |
128 | unsigned char enabled; | |
129 | }; | |
130 | ||
952cf6d7 JS |
131 | /* |
132 | * The following defines attributes of the HUB chip. These attributes are | |
133 | * frequently referenced and are kept in the per-cpu data areas of each cpu. | |
134 | * They are kept together in a struct to minimize cache misses. | |
135 | */ | |
136 | struct uv_hub_info_s { | |
69a72a0e MT |
137 | unsigned long global_mmr_base; |
138 | unsigned long gpa_mask; | |
c4ed3f04 | 139 | unsigned int gnode_extra; |
69a72a0e MT |
140 | unsigned long gnode_upper; |
141 | unsigned long lowmem_remap_top; | |
142 | unsigned long lowmem_remap_base; | |
143 | unsigned short pnode; | |
144 | unsigned short pnode_mask; | |
145 | unsigned short coherency_domain_number; | |
146 | unsigned short numa_blade_id; | |
147 | unsigned char blade_processor_id; | |
148 | unsigned char m_val; | |
149 | unsigned char n_val; | |
150 | struct uv_scir_s scir; | |
952cf6d7 | 151 | }; |
7f1baa06 | 152 | |
952cf6d7 | 153 | DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
39d30770 | 154 | #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) |
952cf6d7 JS |
155 | #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) |
156 | ||
157 | /* | |
158 | * Local & Global MMR space macros. | |
39d30770 MT |
159 | * Note: macros are intended to be used ONLY by inline functions |
160 | * in this file - not by other kernel code. | |
161 | * n - NASID (full 15-bit global nasid) | |
162 | * g - GNODE (full 15-bit global nasid, right shifted 1) | |
163 | * p - PNODE (local part of nsids, right shifted 1) | |
952cf6d7 | 164 | */ |
9f5314fb | 165 | #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) |
c4ed3f04 JS |
166 | #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) |
167 | #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) | |
952cf6d7 JS |
168 | |
169 | #define UV_LOCAL_MMR_BASE 0xf4000000UL | |
170 | #define UV_GLOBAL_MMR32_BASE 0xf8000000UL | |
171 | #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) | |
83f5d894 JS |
172 | #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) |
173 | #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) | |
952cf6d7 | 174 | |
56abcf24 JS |
175 | #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 |
176 | ||
9f5314fb JS |
177 | #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 |
178 | #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 | |
952cf6d7 | 179 | |
9f5314fb | 180 | #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) |
952cf6d7 | 181 | |
9f5314fb | 182 | #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
67e83f30 | 183 | (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
9f5314fb JS |
184 | |
185 | #define UV_APIC_PNODE_SHIFT 6 | |
186 | ||
7f1baa06 MT |
187 | /* Local Bus from cpu's perspective */ |
188 | #define LOCAL_BUS_BASE 0x1c00000 | |
189 | #define LOCAL_BUS_SIZE (4 * 1024 * 1024) | |
190 | ||
191 | /* | |
192 | * System Controller Interface Reg | |
193 | * | |
194 | * Note there are NO leds on a UV system. This register is only | |
195 | * used by the system controller to monitor system-wide operation. | |
196 | * There are 64 regs per node. With Nahelem cpus (2 cores per node, | |
197 | * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on | |
198 | * a node. | |
199 | * | |
200 | * The window is located at top of ACPI MMR space | |
201 | */ | |
202 | #define SCIR_WINDOW_COUNT 64 | |
203 | #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ | |
204 | LOCAL_BUS_SIZE - \ | |
205 | SCIR_WINDOW_COUNT) | |
206 | ||
207 | #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ | |
208 | #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ | |
209 | #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ | |
210 | ||
8661984f DS |
211 | /* Loop through all installed blades */ |
212 | #define for_each_possible_blade(bid) \ | |
213 | for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) | |
214 | ||
9f5314fb JS |
215 | /* |
216 | * Macros for converting between kernel virtual addresses, socket local physical | |
217 | * addresses, and UV global physical addresses. | |
39d30770 MT |
218 | * Note: use the standard __pa() & __va() macros for converting |
219 | * between socket virtual and socket physical addresses. | |
9f5314fb JS |
220 | */ |
221 | ||
222 | /* socket phys RAM --> UV global physical address */ | |
223 | static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) | |
224 | { | |
225 | if (paddr < uv_hub_info->lowmem_remap_top) | |
189f67c4 | 226 | paddr |= uv_hub_info->lowmem_remap_base; |
9f5314fb JS |
227 | return paddr | uv_hub_info->gnode_upper; |
228 | } | |
229 | ||
230 | ||
231 | /* socket virtual --> UV global physical address */ | |
232 | static inline unsigned long uv_gpa(void *v) | |
233 | { | |
189f67c4 | 234 | return uv_soc_phys_ram_to_gpa(__pa(v)); |
9f5314fb | 235 | } |
1d21e6e3 | 236 | |
fae419f2 RH |
237 | /* Top two bits indicate the requested address is in MMR space. */ |
238 | static inline int | |
239 | uv_gpa_in_mmr_space(unsigned long gpa) | |
240 | { | |
241 | return (gpa >> 62) == 0x3UL; | |
242 | } | |
243 | ||
729d69e6 RH |
244 | /* UV global physical address --> socket phys RAM */ |
245 | static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) | |
246 | { | |
247 | unsigned long paddr = gpa & uv_hub_info->gpa_mask; | |
248 | unsigned long remap_base = uv_hub_info->lowmem_remap_base; | |
249 | unsigned long remap_top = uv_hub_info->lowmem_remap_top; | |
250 | ||
251 | if (paddr >= remap_base && paddr < remap_base + remap_top) | |
252 | paddr -= remap_base; | |
253 | return paddr; | |
254 | } | |
255 | ||
256 | ||
1d21e6e3 RH |
257 | /* gnode -> pnode */ |
258 | static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) | |
259 | { | |
260 | return gpa >> uv_hub_info->m_val; | |
261 | } | |
262 | ||
263 | /* gpa -> pnode */ | |
264 | static inline int uv_gpa_to_pnode(unsigned long gpa) | |
265 | { | |
266 | unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; | |
267 | ||
268 | return uv_gpa_to_gnode(gpa) & n_mask; | |
269 | } | |
9f5314fb JS |
270 | |
271 | /* pnode, offset --> socket virtual */ | |
272 | static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) | |
273 | { | |
274 | return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); | |
275 | } | |
952cf6d7 | 276 | |
952cf6d7 JS |
277 | |
278 | /* | |
9f5314fb | 279 | * Extract a PNODE from an APICID (full apicid, not processor subset) |
952cf6d7 | 280 | */ |
9f5314fb | 281 | static inline int uv_apicid_to_pnode(int apicid) |
952cf6d7 | 282 | { |
9f5314fb | 283 | return (apicid >> UV_APIC_PNODE_SHIFT); |
952cf6d7 JS |
284 | } |
285 | ||
286 | /* | |
287 | * Access global MMRs using the low memory MMR32 space. This region supports | |
288 | * faster MMR access but not all MMRs are accessible in this space. | |
289 | */ | |
39d30770 | 290 | static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) |
952cf6d7 JS |
291 | { |
292 | return __va(UV_GLOBAL_MMR32_BASE | | |
9f5314fb | 293 | UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
294 | } |
295 | ||
39d30770 | 296 | static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) |
952cf6d7 | 297 | { |
8dc579e8 | 298 | writeq(val, uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
299 | } |
300 | ||
39d30770 | 301 | static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) |
952cf6d7 | 302 | { |
8dc579e8 | 303 | return readq(uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
304 | } |
305 | ||
306 | /* | |
307 | * Access Global MMR space using the MMR space located at the top of physical | |
308 | * memory. | |
309 | */ | |
a289cc7c | 310 | static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) |
952cf6d7 JS |
311 | { |
312 | return __va(UV_GLOBAL_MMR64_BASE | | |
9f5314fb | 313 | UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
314 | } |
315 | ||
39d30770 | 316 | static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) |
952cf6d7 | 317 | { |
8dc579e8 | 318 | writeq(val, uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
319 | } |
320 | ||
39d30770 | 321 | static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) |
952cf6d7 | 322 | { |
8dc579e8 | 323 | return readq(uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
324 | } |
325 | ||
56abcf24 JS |
326 | /* |
327 | * Global MMR space addresses when referenced by the GRU. (GRU does | |
328 | * NOT use socket addressing). | |
329 | */ | |
330 | static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) | |
331 | { | |
e1e0138d JS |
332 | return UV_GLOBAL_GRU_MMR_BASE | offset | |
333 | ((unsigned long)pnode << uv_hub_info->m_val); | |
56abcf24 JS |
334 | } |
335 | ||
39d30770 MT |
336 | static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) |
337 | { | |
338 | writeb(val, uv_global_mmr64_address(pnode, offset)); | |
339 | } | |
340 | ||
341 | static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) | |
342 | { | |
343 | return readb(uv_global_mmr64_address(pnode, offset)); | |
344 | } | |
345 | ||
952cf6d7 | 346 | /* |
9f5314fb | 347 | * Access hub local MMRs. Faster than using global space but only local MMRs |
952cf6d7 JS |
348 | * are accessible. |
349 | */ | |
350 | static inline unsigned long *uv_local_mmr_address(unsigned long offset) | |
351 | { | |
352 | return __va(UV_LOCAL_MMR_BASE | offset); | |
353 | } | |
354 | ||
355 | static inline unsigned long uv_read_local_mmr(unsigned long offset) | |
356 | { | |
8dc579e8 | 357 | return readq(uv_local_mmr_address(offset)); |
952cf6d7 JS |
358 | } |
359 | ||
360 | static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) | |
361 | { | |
8dc579e8 | 362 | writeq(val, uv_local_mmr_address(offset)); |
952cf6d7 JS |
363 | } |
364 | ||
7f1baa06 MT |
365 | static inline unsigned char uv_read_local_mmr8(unsigned long offset) |
366 | { | |
8dc579e8 | 367 | return readb(uv_local_mmr_address(offset)); |
7f1baa06 MT |
368 | } |
369 | ||
370 | static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) | |
371 | { | |
8dc579e8 | 372 | writeb(val, uv_local_mmr_address(offset)); |
7f1baa06 MT |
373 | } |
374 | ||
8400def8 | 375 | /* |
9f5314fb | 376 | * Structures and definitions for converting between cpu, node, pnode, and blade |
8400def8 JS |
377 | * numbers. |
378 | */ | |
379 | struct uv_blade_info { | |
9f5314fb | 380 | unsigned short nr_possible_cpus; |
8400def8 | 381 | unsigned short nr_online_cpus; |
9f5314fb | 382 | unsigned short pnode; |
6c7184b7 | 383 | short memory_nid; |
8400def8 | 384 | }; |
9f5314fb | 385 | extern struct uv_blade_info *uv_blade_info; |
8400def8 JS |
386 | extern short *uv_node_to_blade; |
387 | extern short *uv_cpu_to_blade; | |
388 | extern short uv_possible_blades; | |
389 | ||
390 | /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ | |
391 | static inline int uv_blade_processor_id(void) | |
392 | { | |
393 | return uv_hub_info->blade_processor_id; | |
394 | } | |
395 | ||
396 | /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ | |
397 | static inline int uv_numa_blade_id(void) | |
398 | { | |
399 | return uv_hub_info->numa_blade_id; | |
400 | } | |
401 | ||
402 | /* Convert a cpu number to the the UV blade number */ | |
403 | static inline int uv_cpu_to_blade_id(int cpu) | |
404 | { | |
405 | return uv_cpu_to_blade[cpu]; | |
406 | } | |
407 | ||
408 | /* Convert linux node number to the UV blade number */ | |
409 | static inline int uv_node_to_blade_id(int nid) | |
410 | { | |
411 | return uv_node_to_blade[nid]; | |
412 | } | |
413 | ||
9f5314fb JS |
414 | /* Convert a blade id to the PNODE of the blade */ |
415 | static inline int uv_blade_to_pnode(int bid) | |
8400def8 | 416 | { |
9f5314fb | 417 | return uv_blade_info[bid].pnode; |
8400def8 JS |
418 | } |
419 | ||
6c7184b7 JS |
420 | /* Nid of memory node on blade. -1 if no blade-local memory */ |
421 | static inline int uv_blade_to_memory_nid(int bid) | |
422 | { | |
423 | return uv_blade_info[bid].memory_nid; | |
424 | } | |
425 | ||
8400def8 JS |
426 | /* Determine the number of possible cpus on a blade */ |
427 | static inline int uv_blade_nr_possible_cpus(int bid) | |
428 | { | |
9f5314fb | 429 | return uv_blade_info[bid].nr_possible_cpus; |
8400def8 JS |
430 | } |
431 | ||
432 | /* Determine the number of online cpus on a blade */ | |
433 | static inline int uv_blade_nr_online_cpus(int bid) | |
434 | { | |
435 | return uv_blade_info[bid].nr_online_cpus; | |
436 | } | |
437 | ||
9f5314fb JS |
438 | /* Convert a cpu id to the PNODE of the blade containing the cpu */ |
439 | static inline int uv_cpu_to_pnode(int cpu) | |
8400def8 | 440 | { |
9f5314fb | 441 | return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; |
8400def8 JS |
442 | } |
443 | ||
9f5314fb JS |
444 | /* Convert a linux node number to the PNODE of the blade */ |
445 | static inline int uv_node_to_pnode(int nid) | |
8400def8 | 446 | { |
9f5314fb | 447 | return uv_blade_info[uv_node_to_blade_id(nid)].pnode; |
8400def8 JS |
448 | } |
449 | ||
450 | /* Maximum possible number of blades */ | |
451 | static inline int uv_num_possible_blades(void) | |
452 | { | |
453 | return uv_possible_blades; | |
454 | } | |
455 | ||
7f1baa06 MT |
456 | /* Update SCIR state */ |
457 | static inline void uv_set_scir_bits(unsigned char value) | |
458 | { | |
459 | if (uv_hub_info->scir.state != value) { | |
460 | uv_hub_info->scir.state = value; | |
461 | uv_write_local_mmr8(uv_hub_info->scir.offset, value); | |
462 | } | |
463 | } | |
66666e50 | 464 | |
39d30770 MT |
465 | static inline unsigned long uv_scir_offset(int apicid) |
466 | { | |
467 | return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); | |
468 | } | |
469 | ||
7f1baa06 MT |
470 | static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) |
471 | { | |
472 | if (uv_cpu_hub_info(cpu)->scir.state != value) { | |
39d30770 MT |
473 | uv_write_global_mmr8(uv_cpu_to_pnode(cpu), |
474 | uv_cpu_hub_info(cpu)->scir.offset, value); | |
7f1baa06 | 475 | uv_cpu_hub_info(cpu)->scir.state = value; |
7f1baa06 MT |
476 | } |
477 | } | |
952cf6d7 | 478 | |
56abcf24 JS |
479 | static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) |
480 | { | |
481 | return (1UL << UVH_IPI_INT_SEND_SHFT) | | |
482 | ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | | |
483 | (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | | |
484 | (vector << UVH_IPI_INT_VECTOR_SHFT); | |
485 | } | |
486 | ||
66666e50 JS |
487 | static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) |
488 | { | |
489 | unsigned long val; | |
02dd0a06 RH |
490 | unsigned long dmode = dest_Fixed; |
491 | ||
492 | if (vector == NMI_VECTOR) | |
493 | dmode = dest_NMI; | |
66666e50 | 494 | |
56abcf24 | 495 | val = uv_hub_ipi_value(apicid, vector, dmode); |
66666e50 JS |
496 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
497 | } | |
498 | ||
7a1110e8 JS |
499 | /* |
500 | * Get the minimum revision number of the hub chips within the partition. | |
501 | * 1 - initial rev 1.0 silicon | |
502 | * 2 - rev 2.0 production silicon | |
503 | */ | |
504 | static inline int uv_get_min_hub_revision_id(void) | |
505 | { | |
506 | extern int uv_min_hub_revision_id; | |
507 | ||
508 | return uv_min_hub_revision_id; | |
509 | } | |
510 | ||
bc5d9940 | 511 | #endif /* CONFIG_X86_64 */ |
7f1baa06 | 512 | #endif /* _ASM_X86_UV_UV_HUB_H */ |