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x86/msr-index: Cleanup bit defines
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
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2#ifndef _ASM_X86_PLATFORM_H
3#define _ASM_X86_PLATFORM_H
4
47a3d5da 5#include <asm/bootparam.h>
030cb6c0 6
52fdb568 7struct mpc_bus;
fd6c6661 8struct mpc_cpu;
72302142 9struct mpc_table;
64be4c1c 10struct cpuinfo_x86;
fd6c6661 11
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12/**
13 * struct x86_init_mpparse - platform specific mpparse ops
14 * @mpc_record: platform specific mpc record accounting
de934103 15 * @setup_ioapic_ids: platform specific ioapic id override
fd6c6661 16 * @mpc_apic_id: platform specific mpc apic id assignment
72302142 17 * @smp_read_mpc_oem: platform specific oem mpc table setup
52fdb568 18 * @mpc_oem_pci_bus: platform specific pci bus setup (default NULL)
90e1c696 19 * @mpc_oem_bus_info: platform specific mpc bus info
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20 * @find_smp_config: find the smp configuration
21 * @get_smp_config: get the smp configuration
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22 */
23struct x86_init_mpparse {
24 void (*mpc_record)(unsigned int mode);
de934103 25 void (*setup_ioapic_ids)(void);
fd6c6661 26 int (*mpc_apic_id)(struct mpc_cpu *m);
72302142 27 void (*smp_read_mpc_oem)(struct mpc_table *mpc);
52fdb568 28 void (*mpc_oem_pci_bus)(struct mpc_bus *m);
90e1c696 29 void (*mpc_oem_bus_info)(struct mpc_bus *m, char *name);
b24c2a92 30 void (*find_smp_config)(void);
b3f1b617 31 void (*get_smp_config)(unsigned int early);
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32};
33
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34/**
35 * struct x86_init_resources - platform specific resource related ops
36 * @probe_roms: probe BIOS roms
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37 * @reserve_resources: reserve the standard resources for the
38 * platform
6b18ae3e 39 * @memory_setup: platform specific memory setup
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40 *
41 */
42struct x86_init_resources {
43 void (*probe_roms)(void);
8fee697d 44 void (*reserve_resources)(void);
6b18ae3e 45 char *(*memory_setup)(void);
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46};
47
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48/**
49 * struct x86_init_irqs - platform specific interrupt setup
50 * @pre_vector_init: init code to run before interrupt vectors
51 * are set up.
66bcaf0b 52 * @intr_init: interrupt init code
428cf902 53 * @trap_init: platform specific trap setup
34fba3e6 54 * @intr_mode_init: interrupt delivery mode setup
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55 */
56struct x86_init_irqs {
57 void (*pre_vector_init)(void);
66bcaf0b 58 void (*intr_init)(void);
428cf902 59 void (*trap_init)(void);
34fba3e6 60 void (*intr_mode_init)(void);
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61};
62
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63/**
64 * struct x86_init_oem - oem platform specific customizing functions
22d3c0d6 65 * @arch_setup: platform specific architecture setup
6f30c1ac 66 * @banner: print a platform specific banner
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67 */
68struct x86_init_oem {
69 void (*arch_setup)(void);
6f30c1ac 70 void (*banner)(void);
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71};
72
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73/**
74 * struct x86_init_paging - platform specific paging functions
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75 * @pagetable_init: platform specific paging initialization call to setup
76 * the kernel pagetables and prepare accessors functions.
77 * Callback must call paging_init(). Called once after the
78 * direct mapping for phys memory is available.
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79 */
80struct x86_init_paging {
7737b215 81 void (*pagetable_init)(void);
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82};
83
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84/**
85 * struct x86_init_timers - platform specific timer setup
86 * @setup_perpcu_clockev: set up the per cpu clock event device for the
87 * boot cpu
845b3944 88 * @timer_init: initialize the platform timer (default PIT/HPET)
6b617e22 89 * @wallclock_init: init the wallclock device
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90 */
91struct x86_init_timers {
92 void (*setup_percpu_clockev)(void);
845b3944 93 void (*timer_init)(void);
6b617e22 94 void (*wallclock_init)(void);
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95};
96
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97/**
98 * struct x86_init_iommu - platform specific iommu setup
99 * @iommu_init: platform specific iommu setup
100 */
101struct x86_init_iommu {
102 int (*iommu_init)(void);
103};
104
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105/**
106 * struct x86_init_pci - platform specific pci init functions
107 * @arch_init: platform specific pci arch init call
108 * @init: platform specific pci subsystem init
ab3b3793 109 * @init_irq: platform specific pci irq init
9325a28c 110 * @fixup_irqs: platform specific pci irq fixup
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111 */
112struct x86_init_pci {
4fb6088a 113 int (*arch_init)(void);
b72d0db9 114 int (*init)(void);
ab3b3793 115 void (*init_irq)(void);
9325a28c 116 void (*fixup_irqs)(void);
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117};
118
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119/**
120 * struct x86_hyper_init - x86 hypervisor init functions
121 * @init_platform: platform setup
f3614646 122 * @guest_late_init: guest late init
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123 * @x2apic_available: X2APIC detection
124 * @init_mem_mapping: setup early mappings during init_mem_mapping()
125 */
126struct x86_hyper_init {
127 void (*init_platform)(void);
f3614646 128 void (*guest_late_init)(void);
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129 bool (*x2apic_available)(void);
130 void (*init_mem_mapping)(void);
131};
132
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133/**
134 * struct x86_init_ops - functions for platform specific setup
135 *
136 */
137struct x86_init_ops {
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138 struct x86_init_resources resources;
139 struct x86_init_mpparse mpparse;
d9112f43 140 struct x86_init_irqs irqs;
42bbdb43 141 struct x86_init_oem oem;
030cb6c0 142 struct x86_init_paging paging;
736decac 143 struct x86_init_timers timers;
d07c1be0 144 struct x86_init_iommu iommu;
b72d0db9 145 struct x86_init_pci pci;
f72e38e8 146 struct x86_hyper_init hyper;
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147};
148
149/**
150 * struct x86_cpuinit_ops - platform specific cpu hotplug setups
151 * @setup_percpu_clockev: set up the per cpu clock event device
df156f90 152 * @early_percpu_clock_init: early init of the per cpu clock event device
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153 */
154struct x86_cpuinit_ops {
155 void (*setup_percpu_clockev)(void);
df156f90 156 void (*early_percpu_clock_init)(void);
64be4c1c 157 void (*fixup_cpu_id)(struct cpuinfo_x86 *c, int node);
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158};
159
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160struct timespec;
161
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162/**
163 * struct x86_legacy_devices - legacy x86 devices
164 *
165 * @pnpbios: this platform can have a PNPBIOS. If this is disabled the platform
166 * is known to never have a PNPBIOS.
167 *
168 * These are devices known to require LPC or ISA bus. The definition of legacy
169 * devices adheres to the ACPI 5.2.9.3 IA-PC Boot Architecture flag
170 * ACPI_FADT_LEGACY_DEVICES. These devices consist of user visible devices on
171 * the LPC or ISA bus. User visible devices are devices that have end-user
172 * accessible connectors (for example, LPT parallel port). Legacy devices on
173 * the LPC bus consist for example of serial and parallel ports, PS/2 keyboard
174 * / mouse, and the floppy disk controller. A system that lacks all known
175 * legacy devices can assume all devices can be detected exclusively via
176 * standard device enumeration mechanisms including the ACPI namespace.
177 *
178 * A system which has does not have ACPI_FADT_LEGACY_DEVICES enabled must not
179 * have any of the legacy devices enumerated below present.
180 */
181struct x86_legacy_devices {
182 int pnpbios;
183};
184
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185/**
186 * enum x86_legacy_i8042_state - i8042 keyboard controller state
187 * @X86_LEGACY_I8042_PLATFORM_ABSENT: the controller is always absent on
188 * given platform/subarch.
189 * @X86_LEGACY_I8042_FIRMWARE_ABSENT: firmware reports that the controller
190 * is absent.
191 * @X86_LEGACY_i8042_EXPECTED_PRESENT: the controller is likely to be
192 * present, the i8042 driver should probe for controller existence.
193 */
194enum x86_legacy_i8042_state {
195 X86_LEGACY_I8042_PLATFORM_ABSENT,
196 X86_LEGACY_I8042_FIRMWARE_ABSENT,
197 X86_LEGACY_I8042_EXPECTED_PRESENT,
198};
199
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200/**
201 * struct x86_legacy_features - legacy x86 features
202 *
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203 * @i8042: indicated if we expect the device to have i8042 controller
204 * present.
8d152e7a 205 * @rtc: this device has a CMOS real-time clock present
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206 * @reserve_bios_regions: boot code will search for the EBDA address and the
207 * start of the 640k - 1M BIOS region. If false, the platform must
208 * ensure that its memory map correctly reserves sub-1MB regions as needed.
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209 * @devices: legacy x86 devices, refer to struct x86_legacy_devices
210 * documentation for further details.
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211 */
212struct x86_legacy_features {
93ffa9a4 213 enum x86_legacy_i8042_state i8042;
8d152e7a 214 int rtc;
6d730525 215 int no_vga;
edce2121 216 int reserve_bios_regions;
80dfd83d 217 struct x86_legacy_devices devices;
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218};
219
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220/**
221 * struct x86_hyper_runtime - x86 hypervisor specific runtime callbacks
222 *
223 * @pin_vcpu: pin current vcpu to specified physical cpu (run rarely)
224 */
225struct x86_hyper_runtime {
226 void (*pin_vcpu)(int cpu);
227};
228
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229/**
230 * struct x86_platform_ops - platform specific runtime functions
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231 * @calibrate_cpu: calibrate CPU
232 * @calibrate_tsc: calibrate TSC, if different from CPU
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233 * @get_wallclock: get time from HW clock like RTC etc.
234 * @set_wallclock: set time back to HW clock
eb41c8be 235 * @is_untracked_pat_range exclude from PAT logic
78c06176 236 * @nmi_init enable NMI on cpus
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237 * @save_sched_clock_state: save state for sched_clock() on suspend
238 * @restore_sched_clock_state: restore state for sched_clock() on resume
22d3c0d6 239 * @apic_post_init: adjust apic if needed
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240 * @legacy: legacy features
241 * @set_legacy_features: override legacy features. Use of this callback
242 * is highly discouraged. You should only need
243 * this if your hardware platform requires further
22d3c0d6 244 * custom fine tuning far beyond what may be
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245 * possible in x86_early_init_platform_quirks() by
246 * only using the current x86_hardware_subarch
247 * semantics.
f72e38e8 248 * @hyper: x86 hypervisor specific runtime callbacks
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249 */
250struct x86_platform_ops {
aa297292 251 unsigned long (*calibrate_cpu)(void);
2d826404 252 unsigned long (*calibrate_tsc)(void);
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253 void (*get_wallclock)(struct timespec *ts);
254 int (*set_wallclock)(const struct timespec *ts);
338bac52 255 void (*iommu_shutdown)(void);
eb41c8be 256 bool (*is_untracked_pat_range)(u64 start, u64 end);
78c06176 257 void (*nmi_init)(void);
064a59b6 258 unsigned char (*get_nmi_reason)(void);
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259 void (*save_sched_clock_state)(void);
260 void (*restore_sched_clock_state)(void);
7db971b2 261 void (*apic_post_init)(void);
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262 struct x86_legacy_features legacy;
263 void (*set_legacy_features)(void);
f72e38e8 264 struct x86_hyper_runtime hyper;
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265};
266
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267struct pci_dev;
268
269struct x86_msi_ops {
270 int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
271 void (*teardown_msi_irq)(unsigned int irq);
272 void (*teardown_msi_irqs)(struct pci_dev *dev);
ac8344c4 273 void (*restore_msi_irqs)(struct pci_dev *dev);
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274};
275
4a8e2a31 276struct x86_io_apic_ops {
1c4248ca 277 unsigned int (*read) (unsigned int apic, unsigned int reg);
1c4248ca 278 void (*disable)(void);
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279};
280
57844a8f 281extern struct x86_init_ops x86_init;
736decac 282extern struct x86_cpuinit_ops x86_cpuinit;
2d826404 283extern struct x86_platform_ops x86_platform;
294ee6f8 284extern struct x86_msi_ops x86_msi;
4a8e2a31 285extern struct x86_io_apic_ops x86_io_apic_ops;
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286
287extern void x86_early_init_platform_quirks(void);
57844a8f 288extern void x86_init_noop(void);
f4848472 289extern void x86_init_uint_noop(unsigned int unused);
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290
291#endif