projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1965aae3 PA |
1 | #ifndef _ASM_X86_MSR_INDEX_H |
| 2 | #define _ASM_X86_MSR_INDEX_H | |
| 4bc5aa91 PA |
3 | |
| 4 | /* CPU model specific register (MSR) numbers */ | |
| 5 | ||
| 6 | /* x86-64 specific MSRs */ | |
| 7 | #define MSR_EFER 0xc0000080 /* extended feature register */ | |
| 8 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ | |
| 9 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ | |
| 10 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ | |
| 11 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ | |
| 12 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ | |
| 13 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ | |
| 14 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ | |
| 5df97400 | 15 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
| 4bc5aa91 PA |
16 | |
| 17 | /* EFER bits: */ | |
| 18 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ | |
| 19 | #define _EFER_LME 8 /* Long mode enable */ | |
| 20 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | |
| 21 | #define _EFER_NX 11 /* No execute enable */ | |
| 9962d032 | 22 | #define _EFER_SVME 12 /* Enable virtualization */ |
| eec4b140 | 23 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
| d2062693 | 24 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
| 4bc5aa91 PA |
25 | |
| 26 | #define EFER_SCE (1<<_EFER_SCE) | |
| 27 | #define EFER_LME (1<<_EFER_LME) | |
| 28 | #define EFER_LMA (1<<_EFER_LMA) | |
| 29 | #define EFER_NX (1<<_EFER_NX) | |
| 9962d032 | 30 | #define EFER_SVME (1<<_EFER_SVME) |
| eec4b140 | 31 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
| d2062693 | 32 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
| 4bc5aa91 PA |
33 | |
| 34 | /* Intel MSRs. Some also available on other CPUs */ | |
| 35 | #define MSR_IA32_PERFCTR0 0x000000c1 | |
| 36 | #define MSR_IA32_PERFCTR1 0x000000c2 | |
| 37 | #define MSR_FSB_FREQ 0x000000cd | |
| 9c63a650 | 38 | #define MSR_NHM_PLATFORM_INFO 0x000000ce |
| 4bc5aa91 | 39 | |
| 14796fca LB |
40 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
| 41 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) | |
| 42 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) | |
| bfb53ccf | 43 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
| 9c63a650 LB |
44 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) |
| 45 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) | |
| 14796fca | 46 | |
| 05e99c8c | 47 | #define MSR_PLATFORM_INFO 0x000000ce |
| 4bc5aa91 PA |
48 | #define MSR_MTRRcap 0x000000fe |
| 49 | #define MSR_IA32_BBL_CR_CTL 0x00000119 | |
| 91c9c3ed | 50 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
| 4bc5aa91 PA |
51 | |
| 52 | #define MSR_IA32_SYSENTER_CS 0x00000174 | |
| 53 | #define MSR_IA32_SYSENTER_ESP 0x00000175 | |
| 54 | #define MSR_IA32_SYSENTER_EIP 0x00000176 | |
| 55 | ||
| 56 | #define MSR_IA32_MCG_CAP 0x00000179 | |
| 57 | #define MSR_IA32_MCG_STATUS 0x0000017a | |
| 58 | #define MSR_IA32_MCG_CTL 0x0000017b | |
| 59 | ||
| a7e3ed1e AK |
60 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
| 61 | #define MSR_OFFCORE_RSP_1 0x000001a7 | |
| 9c63a650 LB |
62 | #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad |
| 63 | #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae | |
| a7e3ed1e | 64 | |
| 225ce539 SE |
65 | #define MSR_LBR_SELECT 0x000001c8 |
| 66 | #define MSR_LBR_TOS 0x000001c9 | |
| 67 | #define MSR_LBR_NHM_FROM 0x00000680 | |
| 68 | #define MSR_LBR_NHM_TO 0x000006c0 | |
| 69 | #define MSR_LBR_CORE_FROM 0x00000040 | |
| 70 | #define MSR_LBR_CORE_TO 0x00000060 | |
| 71 | ||
| 4bc5aa91 PA |
72 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
| 73 | #define MSR_IA32_DS_AREA 0x00000600 | |
| 74 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 | |
| f20093ee | 75 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
| 4bc5aa91 | 76 | |
| 52ca9ced AS |
77 | #define MSR_IA32_RTIT_CTL 0x00000570 |
| 78 | #define RTIT_CTL_TRACEEN BIT(0) | |
| 79 | #define RTIT_CTL_OS BIT(2) | |
| 80 | #define RTIT_CTL_USR BIT(3) | |
| 81 | #define RTIT_CTL_CR3EN BIT(7) | |
| 82 | #define RTIT_CTL_TOPA BIT(8) | |
| 83 | #define RTIT_CTL_TSC_EN BIT(10) | |
| 84 | #define RTIT_CTL_DISRETC BIT(11) | |
| 85 | #define RTIT_CTL_BRANCH_EN BIT(13) | |
| 86 | #define MSR_IA32_RTIT_STATUS 0x00000571 | |
| 87 | #define RTIT_STATUS_CONTEXTEN BIT(1) | |
| 88 | #define RTIT_STATUS_TRIGGEREN BIT(2) | |
| 89 | #define RTIT_STATUS_ERROR BIT(4) | |
| 90 | #define RTIT_STATUS_STOPPED BIT(5) | |
| 91 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 | |
| 92 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 | |
| 93 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 | |
| 94 | ||
| 4bc5aa91 PA |
95 | #define MSR_MTRRfix64K_00000 0x00000250 |
| 96 | #define MSR_MTRRfix16K_80000 0x00000258 | |
| 97 | #define MSR_MTRRfix16K_A0000 0x00000259 | |
| 98 | #define MSR_MTRRfix4K_C0000 0x00000268 | |
| 99 | #define MSR_MTRRfix4K_C8000 0x00000269 | |
| 100 | #define MSR_MTRRfix4K_D0000 0x0000026a | |
| 101 | #define MSR_MTRRfix4K_D8000 0x0000026b | |
| 102 | #define MSR_MTRRfix4K_E0000 0x0000026c | |
| 103 | #define MSR_MTRRfix4K_E8000 0x0000026d | |
| 104 | #define MSR_MTRRfix4K_F0000 0x0000026e | |
| 105 | #define MSR_MTRRfix4K_F8000 0x0000026f | |
| 106 | #define MSR_MTRRdefType 0x000002ff | |
| 107 | ||
| 2e5d9c85 | 108 | #define MSR_IA32_CR_PAT 0x00000277 |
| 109 | ||
| 4bc5aa91 PA |
110 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
| 111 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db | |
| 112 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc | |
| 113 | #define MSR_IA32_LASTINTFROMIP 0x000001dd | |
| 114 | #define MSR_IA32_LASTINTTOIP 0x000001de | |
| 115 | ||
| d2499d8b | 116 | /* DEBUGCTLMSR bits (others vary by model): */ |
| 7c5ecaf7 PZ |
117 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
| 118 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ | |
| 119 | #define DEBUGCTLMSR_TR (1UL << 6) | |
| 120 | #define DEBUGCTLMSR_BTS (1UL << 7) | |
| 121 | #define DEBUGCTLMSR_BTINT (1UL << 8) | |
| 122 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) | |
| 123 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) | |
| 124 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) | |
| d2499d8b | 125 | |
| 67920418 LB |
126 | #define MSR_IA32_POWER_CTL 0x000001fc |
| 127 | ||
| 4bc5aa91 PA |
128 | #define MSR_IA32_MC0_CTL 0x00000400 |
| 129 | #define MSR_IA32_MC0_STATUS 0x00000401 | |
| 130 | #define MSR_IA32_MC0_ADDR 0x00000402 | |
| 131 | #define MSR_IA32_MC0_MISC 0x00000403 | |
| 132 | ||
| 9c63a650 LB |
133 | /* C-state Residency Counters */ |
| 134 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 | |
| 135 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 | |
| 136 | #define MSR_PKG_C7_RESIDENCY 0x000003fa | |
| 137 | #define MSR_CORE_C3_RESIDENCY 0x000003fc | |
| 138 | #define MSR_CORE_C6_RESIDENCY 0x000003fd | |
| 139 | #define MSR_CORE_C7_RESIDENCY 0x000003fe | |
| 140 | #define MSR_PKG_C2_RESIDENCY 0x0000060d | |
| ca58710f KCA |
141 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
| 142 | #define MSR_PKG_C9_RESIDENCY 0x00000631 | |
| 143 | #define MSR_PKG_C10_RESIDENCY 0x00000632 | |
| 9c63a650 | 144 | |
| 3fc808aa LB |
145 | /* Run Time Average Power Limiting (RAPL) Interface */ |
| 146 | ||
| 147 | #define MSR_RAPL_POWER_UNIT 0x00000606 | |
| 148 | ||
| 149 | #define MSR_PKG_POWER_LIMIT 0x00000610 | |
| 150 | #define MSR_PKG_ENERGY_STATUS 0x00000611 | |
| 151 | #define MSR_PKG_PERF_STATUS 0x00000613 | |
| 152 | #define MSR_PKG_POWER_INFO 0x00000614 | |
| 153 | ||
| 154 | #define MSR_DRAM_POWER_LIMIT 0x00000618 | |
| 155 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 | |
| 156 | #define MSR_DRAM_PERF_STATUS 0x0000061b | |
| 157 | #define MSR_DRAM_POWER_INFO 0x0000061c | |
| 158 | ||
| 159 | #define MSR_PP0_POWER_LIMIT 0x00000638 | |
| 160 | #define MSR_PP0_ENERGY_STATUS 0x00000639 | |
| 161 | #define MSR_PP0_POLICY 0x0000063a | |
| 162 | #define MSR_PP0_PERF_STATUS 0x0000063b | |
| 163 | ||
| 164 | #define MSR_PP1_POWER_LIMIT 0x00000640 | |
| 165 | #define MSR_PP1_ENERGY_STATUS 0x00000641 | |
| 166 | #define MSR_PP1_POLICY 0x00000642 | |
| 167 | ||
| 144b44b1 LB |
168 | #define MSR_CORE_C1_RES 0x00000660 |
| 169 | ||
| 8c058d53 LB |
170 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
| 171 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 | |
| 172 | ||
| 3a9a941d LB |
173 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
| 174 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 | |
| 175 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 | |
| 176 | ||
| 2f86dc4c DB |
177 | /* Hardware P state interface */ |
| 178 | #define MSR_PPERF 0x0000064e | |
| 179 | #define MSR_PERF_LIMIT_REASONS 0x0000064f | |
| 180 | #define MSR_PM_ENABLE 0x00000770 | |
| 181 | #define MSR_HWP_CAPABILITIES 0x00000771 | |
| 182 | #define MSR_HWP_REQUEST_PKG 0x00000772 | |
| 183 | #define MSR_HWP_INTERRUPT 0x00000773 | |
| 184 | #define MSR_HWP_REQUEST 0x00000774 | |
| 185 | #define MSR_HWP_STATUS 0x00000777 | |
| 186 | ||
| 187 | /* CPUID.6.EAX */ | |
| 188 | #define HWP_BASE_BIT (1<<7) | |
| 189 | #define HWP_NOTIFICATIONS_BIT (1<<8) | |
| 190 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) | |
| 191 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) | |
| 192 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) | |
| 193 | ||
| 194 | /* IA32_HWP_CAPABILITIES */ | |
| 195 | #define HWP_HIGHEST_PERF(x) (x & 0xff) | |
| 196 | #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) | |
| 197 | #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) | |
| 198 | #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) | |
| 199 | ||
| 200 | /* IA32_HWP_REQUEST */ | |
| 201 | #define HWP_MIN_PERF(x) (x & 0xff) | |
| 202 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) | |
| 203 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) | |
| 204 | #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) | |
| 205 | #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) | |
| 206 | #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) | |
| 207 | ||
| 208 | /* IA32_HWP_STATUS */ | |
| 209 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) | |
| 210 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) | |
| 211 | ||
| 212 | /* IA32_HWP_INTERRUPT */ | |
| 213 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) | |
| 214 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) | |
| 215 | ||
| 5bbc097d JR |
216 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
| 217 | ||
| a2d32bcb AK |
218 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
| 219 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) | |
| 220 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) | |
| 221 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) | |
| 222 | ||
| 5bbc097d JR |
223 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
| 224 | ||
| 03195c6b AK |
225 | /* These are consecutive and not in the normal 4er MCE bank block */ |
| 226 | #define MSR_IA32_MC0_CTL2 0x00000280 | |
| a2d32bcb AK |
227 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
| 228 | ||
| 4bc5aa91 PA |
229 | #define MSR_P6_PERFCTR0 0x000000c1 |
| 230 | #define MSR_P6_PERFCTR1 0x000000c2 | |
| 231 | #define MSR_P6_EVNTSEL0 0x00000186 | |
| 232 | #define MSR_P6_EVNTSEL1 0x00000187 | |
| 233 | ||
| e717bf4e VW |
234 | #define MSR_KNC_PERFCTR0 0x00000020 |
| 235 | #define MSR_KNC_PERFCTR1 0x00000021 | |
| 236 | #define MSR_KNC_EVNTSEL0 0x00000028 | |
| 237 | #define MSR_KNC_EVNTSEL1 0x00000029 | |
| 238 | ||
| 069e0c3c AK |
239 | /* Alternative perfctr range with full access. */ |
| 240 | #define MSR_IA32_PMC0 0x000004c1 | |
| 241 | ||
| 4f8a6b1a | 242 | /* AMD64 MSRs. Not complete. See the architecture manual for a more |
| 4bc5aa91 | 243 | complete list. */ |
| 4f8a6b1a | 244 | |
| 29d0887f | 245 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
| fbc0db76 | 246 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
| 12db648c | 247 | #define MSR_AMD64_NB_CFG 0xc001001f |
| 29d0887f | 248 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
| 035a02c1 AH |
249 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
| 250 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 | |
| 3b564968 | 251 | #define MSR_AMD64_LS_CFG 0xc0011020 |
| 67ec6607 | 252 | #define MSR_AMD64_DC_CFG 0xc0011022 |
| f0322bd3 | 253 | #define MSR_AMD64_BU_CFG2 0xc001102a |
| 4f8a6b1a SE |
254 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
| 255 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 | |
| 256 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 | |
| b7074f1f RR |
257 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
| 258 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) | |
| 4f8a6b1a SE |
259 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
| 260 | #define MSR_AMD64_IBSOPRIP 0xc0011034 | |
| 261 | #define MSR_AMD64_IBSOPDATA 0xc0011035 | |
| 262 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 | |
| 263 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 | |
| 264 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 | |
| 265 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 | |
| b7074f1f RR |
266 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
| 267 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) | |
| 4f8a6b1a | 268 | #define MSR_AMD64_IBSCTL 0xc001103a |
| 25da6950 | 269 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
| 904cb367 | 270 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
| b7074f1f | 271 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
| 4f8a6b1a | 272 | |
| c43ca509 JS |
273 | /* Fam 16h MSRs */ |
| 274 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 | |
| 275 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 | |
| d6d55f0b JS |
276 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
| 277 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a | |
| 278 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b | |
| 279 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 | |
| c43ca509 | 280 | |
| da169f5d RR |
281 | /* Fam 15h MSRs */ |
| 282 | #define MSR_F15H_PERF_CTL 0xc0010200 | |
| 283 | #define MSR_F15H_PERF_CTR 0xc0010201 | |
| e259514e JS |
284 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
| 285 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 | |
| da169f5d | 286 | |
| 2274c33e YL |
287 | /* Fam 10h MSRs */ |
| 288 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 | |
| 289 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) | |
| 290 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf | |
| 291 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 | |
| 37db6c8f | 292 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
| 2274c33e | 293 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
| 9d260ebc | 294 | #define MSR_FAM10H_NODE_ID 0xc001100c |
| 2274c33e | 295 | |
| 4f8a6b1a SE |
296 | /* K8 MSRs */ |
| 297 | #define MSR_K8_TOP_MEM1 0xc001001a | |
| 298 | #define MSR_K8_TOP_MEM2 0xc001001d | |
| 299 | #define MSR_K8_SYSCFG 0xc0010010 | |
| aa83f3f2 TG |
300 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
| 301 | /* C1E active bits in int pending message */ | |
| 302 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 | |
| 8346ea17 | 303 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
| 4f8a6b1a SE |
304 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
| 305 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ | |
| 306 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ | |
| 307 | ||
| 308 | /* K7 MSRs */ | |
| 4bc5aa91 PA |
309 | #define MSR_K7_EVNTSEL0 0xc0010000 |
| 310 | #define MSR_K7_PERFCTR0 0xc0010004 | |
| 311 | #define MSR_K7_EVNTSEL1 0xc0010001 | |
| 312 | #define MSR_K7_PERFCTR1 0xc0010005 | |
| 313 | #define MSR_K7_EVNTSEL2 0xc0010002 | |
| 314 | #define MSR_K7_PERFCTR2 0xc0010006 | |
| 315 | #define MSR_K7_EVNTSEL3 0xc0010003 | |
| 316 | #define MSR_K7_PERFCTR3 0xc0010007 | |
| 4bc5aa91 | 317 | #define MSR_K7_CLK_CTL 0xc001001b |
| 4bc5aa91 | 318 | #define MSR_K7_HWCR 0xc0010015 |
| 4bc5aa91 PA |
319 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
| 320 | #define MSR_K7_FID_VID_STATUS 0xc0010042 | |
| 4bc5aa91 PA |
321 | |
| 322 | /* K6 MSRs */ | |
| 4bc5aa91 PA |
323 | #define MSR_K6_WHCR 0xc0000082 |
| 324 | #define MSR_K6_UWCCR 0xc0000085 | |
| 325 | #define MSR_K6_EPMR 0xc0000086 | |
| 326 | #define MSR_K6_PSOR 0xc0000087 | |
| 327 | #define MSR_K6_PFIR 0xc0000088 | |
| 328 | ||
| 329 | /* Centaur-Hauls/IDT defined MSRs. */ | |
| 330 | #define MSR_IDT_FCR1 0x00000107 | |
| 331 | #define MSR_IDT_FCR2 0x00000108 | |
| 332 | #define MSR_IDT_FCR3 0x00000109 | |
| 333 | #define MSR_IDT_FCR4 0x0000010a | |
| 334 | ||
| 335 | #define MSR_IDT_MCR0 0x00000110 | |
| 336 | #define MSR_IDT_MCR1 0x00000111 | |
| 337 | #define MSR_IDT_MCR2 0x00000112 | |
| 338 | #define MSR_IDT_MCR3 0x00000113 | |
| 339 | #define MSR_IDT_MCR4 0x00000114 | |
| 340 | #define MSR_IDT_MCR5 0x00000115 | |
| 341 | #define MSR_IDT_MCR6 0x00000116 | |
| 342 | #define MSR_IDT_MCR7 0x00000117 | |
| 343 | #define MSR_IDT_MCR_CTRL 0x00000120 | |
| 344 | ||
| 345 | /* VIA Cyrix defined MSRs*/ | |
| 346 | #define MSR_VIA_FCR 0x00001107 | |
| 347 | #define MSR_VIA_LONGHAUL 0x0000110a | |
| 348 | #define MSR_VIA_RNG 0x0000110b | |
| 349 | #define MSR_VIA_BCR2 0x00001147 | |
| 350 | ||
| 351 | /* Transmeta defined MSRs */ | |
| 352 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 | |
| 353 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 | |
| 354 | #define MSR_TMTA_LRTI_READOUT 0x80868018 | |
| 355 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a | |
| 356 | ||
| 357 | /* Intel defined MSRs. */ | |
| 358 | #define MSR_IA32_P5_MC_ADDR 0x00000000 | |
| 359 | #define MSR_IA32_P5_MC_TYPE 0x00000001 | |
| 360 | #define MSR_IA32_TSC 0x00000010 | |
| 361 | #define MSR_IA32_PLATFORM_ID 0x00000017 | |
| 362 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | |
| b9a52c4b | 363 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
| 1ed51011 | 364 | #define MSR_SMI_COUNT 0x00000034 |
| 315a6558 | 365 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
| ba904635 | 366 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
| da8999d3 | 367 | #define MSR_IA32_BNDCFGS 0x00000d90 |
| 4bc5aa91 | 368 | |
| 6229ad27 FY |
369 | #define MSR_IA32_XSS 0x00000da0 |
| 370 | ||
| cafd6659 SW |
371 | #define FEATURE_CONTROL_LOCKED (1<<0) |
| 372 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) | |
| 373 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) | |
| defed7ed | 374 | |
| 4bc5aa91 PA |
375 | #define MSR_IA32_APICBASE 0x0000001b |
| 376 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
| 377 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
| 378 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
| 379 | ||
| b90dfb04 LJ |
380 | #define MSR_IA32_TSCDEADLINE 0x000006e0 |
| 381 | ||
| 4bc5aa91 PA |
382 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
| 383 | #define MSR_IA32_UCODE_REV 0x0000008b | |
| 384 | ||
| e9ac033e EK |
385 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
| 386 | #define MSR_IA32_SMBASE 0x0000009e | |
| 387 | ||
| 4bc5aa91 PA |
388 | #define MSR_IA32_PERF_STATUS 0x00000198 |
| 389 | #define MSR_IA32_PERF_CTL 0x00000199 | |
| e7ddf4b7 | 390 | #define INTEL_PERF_CTL_MASK 0xffff |
| f594065f | 391 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
| 3dc9a633 MG |
392 | #define MSR_AMD_PERF_STATUS 0xc0010063 |
| 393 | #define MSR_AMD_PERF_CTL 0xc0010062 | |
| 4bc5aa91 PA |
394 | |
| 395 | #define MSR_IA32_MPERF 0x000000e7 | |
| 396 | #define MSR_IA32_APERF 0x000000e8 | |
| 397 | ||
| 398 | #define MSR_IA32_THERM_CONTROL 0x0000019a | |
| 399 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b | |
| ba2d0f2b | 400 | |
| 9792db61 FY |
401 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
| 402 | #define THERM_INT_LOW_ENABLE (1 << 1) | |
| 403 | #define THERM_INT_PLN_ENABLE (1 << 24) | |
| ba2d0f2b | 404 | |
| 4bc5aa91 | 405 | #define MSR_IA32_THERM_STATUS 0x0000019c |
| ba2d0f2b TG |
406 | |
| 407 | #define THERM_STATUS_PROCHOT (1 << 0) | |
| 9792db61 | 408 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
| ba2d0f2b | 409 | |
| f3a0867b BZ |
410 | #define MSR_THERM2_CTL 0x0000019d |
| 411 | ||
| 412 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) | |
| 413 | ||
| 4bc5aa91 PA |
414 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
| 415 | ||
| a321cedb CE |
416 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
| 417 | ||
| 2f86dc4c DB |
418 | #define MSR_MISC_PWR_MGMT 0x000001aa |
| 419 | ||
| 23016bf0 | 420 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
| abe48b10 LB |
421 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
| 422 | #define ENERGY_PERF_BIAS_NORMAL 6 | |
| 4bb82178 | 423 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
| 23016bf0 | 424 | |
| 9792db61 FY |
425 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
| 426 | ||
| 427 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) | |
| 428 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) | |
| 429 | ||
| 430 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 | |
| 431 | ||
| 432 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) | |
| 433 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) | |
| 434 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) | |
| 435 | ||
| 9e76a97e D |
436 | /* Thermal Thresholds Support */ |
| 437 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) | |
| 438 | #define THERM_SHIFT_THRESHOLD0 8 | |
| 439 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) | |
| 440 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) | |
| 441 | #define THERM_SHIFT_THRESHOLD1 16 | |
| 442 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) | |
| 443 | #define THERM_STATUS_THRESHOLD0 (1 << 6) | |
| 444 | #define THERM_LOG_THRESHOLD0 (1 << 7) | |
| 445 | #define THERM_STATUS_THRESHOLD1 (1 << 8) | |
| 446 | #define THERM_LOG_THRESHOLD1 (1 << 9) | |
| 447 | ||
| bdf21a49 | 448 | /* MISC_ENABLE bits: architectural */ |
| 0b131be8 PA |
449 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
| 450 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) | |
| 451 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 | |
| 452 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) | |
| 453 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 | |
| 454 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) | |
| 455 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 | |
| 456 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) | |
| 457 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 | |
| 458 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) | |
| 459 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 | |
| 460 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) | |
| 461 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 | |
| 462 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) | |
| 463 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 | |
| c45f7736 | 464 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
| 0b131be8 PA |
465 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
| 466 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) | |
| 467 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 | |
| 468 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) | |
| bdf21a49 PA |
469 | |
| 470 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ | |
| 0b131be8 PA |
471 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
| 472 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) | |
| 473 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 | |
| 474 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) | |
| 475 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 | |
| 476 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) | |
| 477 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 | |
| 478 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) | |
| 479 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 | |
| 480 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) | |
| 481 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 | |
| 482 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) | |
| 483 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 | |
| 484 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) | |
| 485 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 | |
| 486 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) | |
| 487 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 | |
| 488 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) | |
| 489 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 | |
| 490 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) | |
| 491 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 | |
| 492 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) | |
| 493 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 | |
| 494 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) | |
| 495 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 | |
| 496 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) | |
| 497 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 | |
| 498 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) | |
| 499 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 | |
| 500 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) | |
| bdf21a49 | 501 | |
| 279f1461 SS |
502 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
| 503 | ||
| 4bc5aa91 PA |
504 | /* P4/Xeon+ specific */ |
| 505 | #define MSR_IA32_MCG_EAX 0x00000180 | |
| 506 | #define MSR_IA32_MCG_EBX 0x00000181 | |
| 507 | #define MSR_IA32_MCG_ECX 0x00000182 | |
| 508 | #define MSR_IA32_MCG_EDX 0x00000183 | |
| 509 | #define MSR_IA32_MCG_ESI 0x00000184 | |
| 510 | #define MSR_IA32_MCG_EDI 0x00000185 | |
| 511 | #define MSR_IA32_MCG_EBP 0x00000186 | |
| 512 | #define MSR_IA32_MCG_ESP 0x00000187 | |
| 513 | #define MSR_IA32_MCG_EFLAGS 0x00000188 | |
| 514 | #define MSR_IA32_MCG_EIP 0x00000189 | |
| 515 | #define MSR_IA32_MCG_RESERVED 0x0000018a | |
| 516 | ||
| 517 | /* Pentium IV performance counter MSRs */ | |
| 518 | #define MSR_P4_BPU_PERFCTR0 0x00000300 | |
| 519 | #define MSR_P4_BPU_PERFCTR1 0x00000301 | |
| 520 | #define MSR_P4_BPU_PERFCTR2 0x00000302 | |
| 521 | #define MSR_P4_BPU_PERFCTR3 0x00000303 | |
| 522 | #define MSR_P4_MS_PERFCTR0 0x00000304 | |
| 523 | #define MSR_P4_MS_PERFCTR1 0x00000305 | |
| 524 | #define MSR_P4_MS_PERFCTR2 0x00000306 | |
| 525 | #define MSR_P4_MS_PERFCTR3 0x00000307 | |
| 526 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 | |
| 527 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 | |
| 528 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a | |
| 529 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b | |
| 530 | #define MSR_P4_IQ_PERFCTR0 0x0000030c | |
| 531 | #define MSR_P4_IQ_PERFCTR1 0x0000030d | |
| 532 | #define MSR_P4_IQ_PERFCTR2 0x0000030e | |
| 533 | #define MSR_P4_IQ_PERFCTR3 0x0000030f | |
| 534 | #define MSR_P4_IQ_PERFCTR4 0x00000310 | |
| 535 | #define MSR_P4_IQ_PERFCTR5 0x00000311 | |
| 536 | #define MSR_P4_BPU_CCCR0 0x00000360 | |
| 537 | #define MSR_P4_BPU_CCCR1 0x00000361 | |
| 538 | #define MSR_P4_BPU_CCCR2 0x00000362 | |
| 539 | #define MSR_P4_BPU_CCCR3 0x00000363 | |
| 540 | #define MSR_P4_MS_CCCR0 0x00000364 | |
| 541 | #define MSR_P4_MS_CCCR1 0x00000365 | |
| 542 | #define MSR_P4_MS_CCCR2 0x00000366 | |
| 543 | #define MSR_P4_MS_CCCR3 0x00000367 | |
| 544 | #define MSR_P4_FLAME_CCCR0 0x00000368 | |
| 545 | #define MSR_P4_FLAME_CCCR1 0x00000369 | |
| 546 | #define MSR_P4_FLAME_CCCR2 0x0000036a | |
| 547 | #define MSR_P4_FLAME_CCCR3 0x0000036b | |
| 548 | #define MSR_P4_IQ_CCCR0 0x0000036c | |
| 549 | #define MSR_P4_IQ_CCCR1 0x0000036d | |
| 550 | #define MSR_P4_IQ_CCCR2 0x0000036e | |
| 551 | #define MSR_P4_IQ_CCCR3 0x0000036f | |
| 552 | #define MSR_P4_IQ_CCCR4 0x00000370 | |
| 553 | #define MSR_P4_IQ_CCCR5 0x00000371 | |
| 554 | #define MSR_P4_ALF_ESCR0 0x000003ca | |
| 555 | #define MSR_P4_ALF_ESCR1 0x000003cb | |
| 556 | #define MSR_P4_BPU_ESCR0 0x000003b2 | |
| 557 | #define MSR_P4_BPU_ESCR1 0x000003b3 | |
| 558 | #define MSR_P4_BSU_ESCR0 0x000003a0 | |
| 559 | #define MSR_P4_BSU_ESCR1 0x000003a1 | |
| 560 | #define MSR_P4_CRU_ESCR0 0x000003b8 | |
| 561 | #define MSR_P4_CRU_ESCR1 0x000003b9 | |
| 562 | #define MSR_P4_CRU_ESCR2 0x000003cc | |
| 563 | #define MSR_P4_CRU_ESCR3 0x000003cd | |
| 564 | #define MSR_P4_CRU_ESCR4 0x000003e0 | |
| 565 | #define MSR_P4_CRU_ESCR5 0x000003e1 | |
| 566 | #define MSR_P4_DAC_ESCR0 0x000003a8 | |
| 567 | #define MSR_P4_DAC_ESCR1 0x000003a9 | |
| 568 | #define MSR_P4_FIRM_ESCR0 0x000003a4 | |
| 569 | #define MSR_P4_FIRM_ESCR1 0x000003a5 | |
| 570 | #define MSR_P4_FLAME_ESCR0 0x000003a6 | |
| 571 | #define MSR_P4_FLAME_ESCR1 0x000003a7 | |
| 572 | #define MSR_P4_FSB_ESCR0 0x000003a2 | |
| 573 | #define MSR_P4_FSB_ESCR1 0x000003a3 | |
| 574 | #define MSR_P4_IQ_ESCR0 0x000003ba | |
| 575 | #define MSR_P4_IQ_ESCR1 0x000003bb | |
| 576 | #define MSR_P4_IS_ESCR0 0x000003b4 | |
| 577 | #define MSR_P4_IS_ESCR1 0x000003b5 | |
| 578 | #define MSR_P4_ITLB_ESCR0 0x000003b6 | |
| 579 | #define MSR_P4_ITLB_ESCR1 0x000003b7 | |
| 580 | #define MSR_P4_IX_ESCR0 0x000003c8 | |
| 581 | #define MSR_P4_IX_ESCR1 0x000003c9 | |
| 582 | #define MSR_P4_MOB_ESCR0 0x000003aa | |
| 583 | #define MSR_P4_MOB_ESCR1 0x000003ab | |
| 584 | #define MSR_P4_MS_ESCR0 0x000003c0 | |
| 585 | #define MSR_P4_MS_ESCR1 0x000003c1 | |
| 586 | #define MSR_P4_PMH_ESCR0 0x000003ac | |
| 587 | #define MSR_P4_PMH_ESCR1 0x000003ad | |
| 588 | #define MSR_P4_RAT_ESCR0 0x000003bc | |
| 589 | #define MSR_P4_RAT_ESCR1 0x000003bd | |
| 590 | #define MSR_P4_SAAT_ESCR0 0x000003ae | |
| 591 | #define MSR_P4_SAAT_ESCR1 0x000003af | |
| 592 | #define MSR_P4_SSU_ESCR0 0x000003be | |
| 593 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ | |
| 594 | ||
| 595 | #define MSR_P4_TBPU_ESCR0 0x000003c2 | |
| 596 | #define MSR_P4_TBPU_ESCR1 0x000003c3 | |
| 597 | #define MSR_P4_TC_ESCR0 0x000003c4 | |
| 598 | #define MSR_P4_TC_ESCR1 0x000003c5 | |
| 599 | #define MSR_P4_U2L_ESCR0 0x000003b0 | |
| 600 | #define MSR_P4_U2L_ESCR1 0x000003b1 | |
| 601 | ||
| cb7d6b50 LM |
602 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
| 603 | ||
| 4bc5aa91 PA |
604 | /* Intel Core-based CPU performance counters */ |
| 605 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 | |
| 606 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a | |
| 607 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b | |
| 608 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d | |
| 609 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e | |
| 610 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f | |
| 611 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 | |
| 612 | ||
| 613 | /* Geode defined MSRs */ | |
| 614 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | |
| 615 | ||
| 315a6558 SY |
616 | /* Intel VT MSRs */ |
| 617 | #define MSR_IA32_VMX_BASIC 0x00000480 | |
| 618 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | |
| 619 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | |
| 620 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | |
| 621 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | |
| 622 | #define MSR_IA32_VMX_MISC 0x00000485 | |
| 623 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | |
| 624 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | |
| 625 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | |
| 626 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | |
| 627 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | |
| 628 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | |
| 629 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | |
| b87a51ae NHE |
630 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
| 631 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e | |
| 632 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f | |
| 633 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 | |
| cae50139 | 634 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
| b87a51ae NHE |
635 | |
| 636 | /* VMX_BASIC bits and bitmasks */ | |
| 637 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 | |
| 3dbcd8da | 638 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
| b87a51ae NHE |
639 | #define VMX_BASIC_64 0x0001000000000000LLU |
| 640 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 | |
| 641 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU | |
| 642 | #define VMX_BASIC_MEM_TYPE_WB 6LLU | |
| 643 | #define VMX_BASIC_INOUT 0x0040000000000000LLU | |
| 315a6558 | 644 | |
| 89662e56 AG |
645 | /* MSR_IA32_VMX_MISC bits */ |
| 646 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) | |
| 7854cbca | 647 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
| 9962d032 AG |
648 | /* AMD-V MSRs */ |
| 649 | ||
| 650 | #define MSR_VM_CR 0xc0010114 | |
| 0367b433 | 651 | #define MSR_VM_IGNNE 0xc0010115 |
| 9962d032 AG |
652 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 653 | ||
| 1965aae3 | 654 | #endif /* _ASM_X86_MSR_INDEX_H */ |