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Commit | Line | Data |
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4fc2fba8 PM |
1 | /* |
2 | * sleep.c - x86-specific ACPI sleep support. | |
3 | * | |
4 | * Copyright (C) 2001-2003 Patrick Mochel | |
a2531293 | 5 | * Copyright (C) 2001-2003 Pavel Machek <pavel@ucw.cz> |
4fc2fba8 PM |
6 | */ |
7 | ||
8 | #include <linux/acpi.h> | |
9 | #include <linux/bootmem.h> | |
a9ce6bc1 | 10 | #include <linux/memblock.h> |
4fc2fba8 PM |
11 | #include <linux/dmi.h> |
12 | #include <linux/cpumask.h> | |
4fdf08b5 | 13 | #include <asm/segment.h> |
3038edab | 14 | #include <asm/desc.h> |
b40827fa | 15 | #include <asm/pgtable.h> |
d344e38b | 16 | #include <asm/cacheflush.h> |
c9b77ccb | 17 | #include <asm/realmode.h> |
b40827fa | 18 | |
c4845474 | 19 | #include "../../realmode/rm/wakeup.h" |
e44b7b75 | 20 | #include "sleep.h" |
4fc2fba8 | 21 | |
4fc2fba8 | 22 | unsigned long acpi_realmode_flags; |
4fc2fba8 | 23 | |
9744f5a3 | 24 | #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) |
5000cadc | 25 | static char temp_stack[4096]; |
e44b7b75 | 26 | #endif |
4fc2fba8 | 27 | |
40bce100 LZ |
28 | /** |
29 | * x86_acpi_enter_sleep_state - enter sleep state | |
30 | * @state: Sleep state to enter. | |
31 | * | |
32 | * Wrapper around acpi_enter_sleep_state() to be called by assmebly. | |
33 | */ | |
2605fc21 | 34 | acpi_status asmlinkage __visible x86_acpi_enter_sleep_state(u8 state) |
40bce100 LZ |
35 | { |
36 | return acpi_enter_sleep_state(state); | |
37 | } | |
38 | ||
4fc2fba8 | 39 | /** |
d6a77ead | 40 | * x86_acpi_suspend_lowlevel - save kernel state |
4fc2fba8 PM |
41 | * |
42 | * Create an identity mapped page table and copy the wakeup routine to | |
43 | * low memory. | |
44 | */ | |
d6a77ead | 45 | int x86_acpi_suspend_lowlevel(void) |
4fc2fba8 | 46 | { |
c9b77ccb | 47 | struct wakeup_header *header = |
b429dbf6 | 48 | (struct wakeup_header *) __va(real_mode_header->wakeup_header); |
e44b7b75 | 49 | |
d1ee4335 | 50 | if (header->signature != WAKEUP_HEADER_SIGNATURE) { |
e44b7b75 PM |
51 | printk(KERN_ERR "wakeup header does not match\n"); |
52 | return -EINVAL; | |
53 | } | |
54 | ||
55 | header->video_mode = saved_video_mode; | |
56 | ||
73201dbe PA |
57 | header->pmode_behavior = 0; |
58 | ||
e44b7b75 | 59 | #ifndef CONFIG_64BIT |
357d1226 | 60 | native_store_gdt((struct desc_ptr *)&header->pmode_gdt); |
e44b7b75 | 61 | |
5ff560fd PA |
62 | /* |
63 | * We have to check that we can write back the value, and not | |
64 | * just read it. At least on 90 nm Pentium M (Family 6, Model | |
65 | * 13), reading an invalid MSR is not guaranteed to trap, see | |
66 | * Erratum X4 in "Intel Pentium M Processor on 90 nm Process | |
67 | * with 2-MB L2 Cache and IntelĀ® Processor A100 and A110 on 90 | |
68 | * nm process with 512-KB L2 Cache Specification Update". | |
69 | */ | |
73201dbe PA |
70 | if (!rdmsr_safe(MSR_EFER, |
71 | &header->pmode_efer_low, | |
5ff560fd PA |
72 | &header->pmode_efer_high) && |
73 | !wrmsr_safe(MSR_EFER, | |
74 | header->pmode_efer_low, | |
75 | header->pmode_efer_high)) | |
73201dbe | 76 | header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER); |
e44b7b75 PM |
77 | #endif /* !CONFIG_64BIT */ |
78 | ||
79 | header->pmode_cr0 = read_cr0(); | |
73201dbe | 80 | if (__this_cpu_read(cpu_info.cpuid_level) >= 0) { |
1e02ce4c | 81 | header->pmode_cr4 = __read_cr4(); |
73201dbe PA |
82 | header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4); |
83 | } | |
7a313666 KC |
84 | if (!rdmsr_safe(MSR_IA32_MISC_ENABLE, |
85 | &header->pmode_misc_en_low, | |
5ff560fd PA |
86 | &header->pmode_misc_en_high) && |
87 | !wrmsr_safe(MSR_IA32_MISC_ENABLE, | |
88 | header->pmode_misc_en_low, | |
89 | header->pmode_misc_en_high)) | |
7a313666 KC |
90 | header->pmode_behavior |= |
91 | (1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE); | |
e44b7b75 PM |
92 | header->realmode_flags = acpi_realmode_flags; |
93 | header->real_magic = 0x12345678; | |
94 | ||
95 | #ifndef CONFIG_64BIT | |
96 | header->pmode_entry = (u32)&wakeup_pmode_return; | |
afd51a0e | 97 | header->pmode_cr3 = (u32)__pa_symbol(initial_page_table); |
e44b7b75 PM |
98 | saved_magic = 0x12345678; |
99 | #else /* CONFIG_64BIT */ | |
1ea598c2 | 100 | #ifdef CONFIG_SMP |
11d4c3f9 | 101 | stack_start = (unsigned long)temp_stack + sizeof(temp_stack); |
3038edab RW |
102 | early_gdt_descr.address = |
103 | (unsigned long)get_cpu_gdt_table(smp_processor_id()); | |
004aa322 | 104 | initial_gs = per_cpu_offset(smp_processor_id()); |
1ea598c2 | 105 | #endif |
e44b7b75 | 106 | initial_code = (unsigned long)wakeup_long64; |
ce4b3c55 | 107 | saved_magic = 0x123456789abcdef0L; |
e44b7b75 | 108 | #endif /* CONFIG_64BIT */ |
4fc2fba8 | 109 | |
f1a2003e | 110 | do_suspend_lowlevel(); |
4fc2fba8 PM |
111 | return 0; |
112 | } | |
113 | ||
4fc2fba8 PM |
114 | static int __init acpi_sleep_setup(char *str) |
115 | { | |
116 | while ((str != NULL) && (*str != '\0')) { | |
117 | if (strncmp(str, "s3_bios", 7) == 0) | |
118 | acpi_realmode_flags |= 1; | |
119 | if (strncmp(str, "s3_mode", 7) == 0) | |
120 | acpi_realmode_flags |= 2; | |
121 | if (strncmp(str, "s3_beep", 7) == 0) | |
122 | acpi_realmode_flags |= 4; | |
bdfe6b7c SL |
123 | #ifdef CONFIG_HIBERNATION |
124 | if (strncmp(str, "s4_nohwsig", 10) == 0) | |
125 | acpi_no_s4_hw_signature(); | |
126 | #endif | |
72ad5d77 RW |
127 | if (strncmp(str, "nonvs", 5) == 0) |
128 | acpi_nvs_nosave(); | |
1bad2f19 KCA |
129 | if (strncmp(str, "nonvs_s3", 8) == 0) |
130 | acpi_nvs_nosave_s3(); | |
d8f3de0d RW |
131 | if (strncmp(str, "old_ordering", 12) == 0) |
132 | acpi_old_suspend_ordering(); | |
4fc2fba8 PM |
133 | str = strchr(str, ','); |
134 | if (str != NULL) | |
135 | str += strspn(str, ", \t"); | |
136 | } | |
137 | return 1; | |
138 | } | |
139 | ||
140 | __setup("acpi_sleep=", acpi_sleep_setup); |