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Commit | Line | Data |
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0920654f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 4 | * |
1da177e4 LT |
5 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
6 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 7 | * with more than 4GB. |
1da177e4 | 8 | * |
985098a0 | 9 | * See Documentation/core-api/dma-api-howto.rst for the interface specification. |
05fccb0e | 10 | * |
1da177e4 LT |
11 | * Copyright 2002 Andi Kleen, SuSE Labs. |
12 | */ | |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
d43c36dc | 19 | #include <linux/sched.h> |
b17b0153 | 20 | #include <linux/sched/debug.h> |
1da177e4 LT |
21 | #include <linux/string.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/pci.h> | |
1da177e4 LT |
24 | #include <linux/topology.h> |
25 | #include <linux/interrupt.h> | |
a66022c4 | 26 | #include <linux/bitmap.h> |
1eeb66a1 | 27 | #include <linux/kdebug.h> |
9ee1bea4 | 28 | #include <linux/scatterlist.h> |
fde9a109 | 29 | #include <linux/iommu-helper.h> |
f3c6ea1b | 30 | #include <linux/syscore_ops.h> |
237a6224 | 31 | #include <linux/io.h> |
5a0e3ad6 | 32 | #include <linux/gfp.h> |
60063497 | 33 | #include <linux/atomic.h> |
ea8c64ac | 34 | #include <linux/dma-direct.h> |
1da177e4 | 35 | #include <asm/mtrr.h> |
1da177e4 | 36 | #include <asm/proto.h> |
46a7fa27 | 37 | #include <asm/iommu.h> |
395624fc | 38 | #include <asm/gart.h> |
d1163651 | 39 | #include <asm/set_memory.h> |
17a941d8 MBY |
40 | #include <asm/swiotlb.h> |
41 | #include <asm/dma.h> | |
23ac4ae8 | 42 | #include <asm/amd_nb.h> |
338bac52 | 43 | #include <asm/x86_init.h> |
22e6daf4 | 44 | #include <asm/iommu_table.h> |
1da177e4 | 45 | |
79da0874 | 46 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 47 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
48 | static unsigned long iommu_pages; /* .. and in pages */ |
49 | ||
05fccb0e | 50 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 51 | |
05fccb0e IM |
52 | /* |
53 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
54 | * of only flushing when an mapping is reused. With it true the GART is | |
55 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
56 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
57 | * has been also also seen with Qlogic at least). | |
58 | */ | |
c854c919 | 59 | static int iommu_fullflush = 1; |
1da177e4 | 60 | |
05fccb0e | 61 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 62 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
63 | /* Guarded by iommu_bitmap_lock: */ |
64 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 65 | |
05fccb0e | 66 | static u32 gart_unmapped_entry; |
1da177e4 LT |
67 | |
68 | #define GPTE_VALID 1 | |
69 | #define GPTE_COHERENT 2 | |
70 | #define GPTE_ENCODE(x) \ | |
71 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
72 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
73 | ||
1da177e4 LT |
74 | #ifdef CONFIG_AGP |
75 | #define AGPEXTERN extern | |
76 | #else | |
77 | #define AGPEXTERN | |
78 | #endif | |
79 | ||
665d3e2a JR |
80 | /* GART can only remap to physical addresses < 1TB */ |
81 | #define GART_MAX_PHYS_ADDR (1ULL << 40) | |
82 | ||
1da177e4 LT |
83 | /* backdoor interface to AGP driver */ |
84 | AGPEXTERN int agp_memory_reserved; | |
85 | AGPEXTERN __u32 *agp_gatt_table; | |
86 | ||
87 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
3610f211 | 88 | static bool need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 89 | |
7b22ff53 FT |
90 | static unsigned long alloc_iommu(struct device *dev, int size, |
91 | unsigned long align_mask) | |
05fccb0e | 92 | { |
1da177e4 | 93 | unsigned long offset, flags; |
fde9a109 FT |
94 | unsigned long boundary_size; |
95 | unsigned long base_index; | |
96 | ||
97 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
98 | PAGE_SIZE) >> PAGE_SHIFT; | |
123bf0e2 | 99 | boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 100 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 101 | |
05fccb0e | 102 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 103 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 104 | size, base_index, boundary_size, align_mask); |
1da177e4 | 105 | if (offset == -1) { |
3610f211 | 106 | need_flush = true; |
fde9a109 | 107 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
108 | size, base_index, boundary_size, |
109 | align_mask); | |
1da177e4 | 110 | } |
05fccb0e | 111 | if (offset != -1) { |
05fccb0e IM |
112 | next_bit = offset+size; |
113 | if (next_bit >= iommu_pages) { | |
1da177e4 | 114 | next_bit = 0; |
3610f211 | 115 | need_flush = true; |
05fccb0e IM |
116 | } |
117 | } | |
1da177e4 | 118 | if (iommu_fullflush) |
3610f211 | 119 | need_flush = true; |
05fccb0e IM |
120 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
121 | ||
1da177e4 | 122 | return offset; |
05fccb0e | 123 | } |
1da177e4 LT |
124 | |
125 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 126 | { |
1da177e4 | 127 | unsigned long flags; |
05fccb0e | 128 | |
1da177e4 | 129 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a66022c4 | 130 | bitmap_clear(iommu_gart_bitmap, offset, size); |
70d7d357 JR |
131 | if (offset >= next_bit) |
132 | next_bit = offset + size; | |
1da177e4 | 133 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 134 | } |
1da177e4 | 135 | |
05fccb0e | 136 | /* |
1da177e4 LT |
137 | * Use global flush state to avoid races with multiple flushers. |
138 | */ | |
a32073bf | 139 | static void flush_gart(void) |
05fccb0e | 140 | { |
1da177e4 | 141 | unsigned long flags; |
05fccb0e | 142 | |
1da177e4 | 143 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf | 144 | if (need_flush) { |
eec1d4fa | 145 | amd_flush_garts(); |
3610f211 | 146 | need_flush = false; |
05fccb0e | 147 | } |
1da177e4 | 148 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 149 | } |
1da177e4 | 150 | |
1da177e4 | 151 | #ifdef CONFIG_IOMMU_LEAK |
1da177e4 | 152 | /* Debugging aid for drivers that don't free their IOMMU tables */ |
79da0874 | 153 | static void dump_leak(void) |
1da177e4 | 154 | { |
05fccb0e IM |
155 | static int dump; |
156 | ||
19c1a6f5 | 157 | if (dump) |
05fccb0e | 158 | return; |
1da177e4 | 159 | dump = 1; |
05fccb0e | 160 | |
9cb8f069 | 161 | show_stack(NULL, NULL, KERN_ERR); |
19c1a6f5 | 162 | debug_dma_dump_mappings(NULL); |
1da177e4 | 163 | } |
1da177e4 LT |
164 | #endif |
165 | ||
17a941d8 | 166 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 167 | { |
05fccb0e | 168 | /* |
1da177e4 LT |
169 | * Ran out of IOMMU space for this operation. This is very bad. |
170 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 171 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
172 | * let the Northbridge deal with it. This will result in garbage |
173 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 174 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 175 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
176 | */ |
177 | ||
fc3a8828 | 178 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 179 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 180 | dump_leak(); |
1da177e4 | 181 | #endif |
05fccb0e | 182 | } |
1da177e4 | 183 | |
05fccb0e IM |
184 | static inline int |
185 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
186 | { | |
68a33b17 | 187 | return force_iommu || !dma_capable(dev, addr, size, true); |
1da177e4 LT |
188 | } |
189 | ||
05fccb0e IM |
190 | static inline int |
191 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
192 | { | |
68a33b17 | 193 | return !dma_capable(dev, addr, size, true); |
1da177e4 LT |
194 | } |
195 | ||
196 | /* Map a single continuous physical area into the IOMMU. | |
197 | * Caller needs to check if the iommu is needed and flush. | |
198 | */ | |
17a941d8 | 199 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
7b22ff53 | 200 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 201 | { |
1477b8e5 | 202 | unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); |
665d3e2a | 203 | unsigned long iommu_page; |
1da177e4 | 204 | int i; |
05fccb0e | 205 | |
665d3e2a | 206 | if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR)) |
9e8aa6b5 | 207 | return DMA_MAPPING_ERROR; |
665d3e2a JR |
208 | |
209 | iommu_page = alloc_iommu(dev, npages, align_mask); | |
1da177e4 LT |
210 | if (iommu_page == -1) { |
211 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 212 | return phys_mem; |
1da177e4 LT |
213 | if (panic_on_overflow) |
214 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 215 | iommu_full(dev, size, dir); |
9e8aa6b5 | 216 | return DMA_MAPPING_ERROR; |
1da177e4 LT |
217 | } |
218 | ||
219 | for (i = 0; i < npages; i++) { | |
220 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
1da177e4 LT |
221 | phys_mem += PAGE_SIZE; |
222 | } | |
223 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
224 | } | |
225 | ||
226 | /* Map a single area into the IOMMU */ | |
052aedbf FT |
227 | static dma_addr_t gart_map_page(struct device *dev, struct page *page, |
228 | unsigned long offset, size_t size, | |
229 | enum dma_data_direction dir, | |
00085f1e | 230 | unsigned long attrs) |
1da177e4 | 231 | { |
2be62149 | 232 | unsigned long bus; |
052aedbf | 233 | phys_addr_t paddr = page_to_phys(page) + offset; |
1da177e4 | 234 | |
2be62149 IM |
235 | if (!need_iommu(dev, paddr, size)) |
236 | return paddr; | |
1da177e4 | 237 | |
7b22ff53 FT |
238 | bus = dma_map_area(dev, paddr, size, dir, 0); |
239 | flush_gart(); | |
05fccb0e IM |
240 | |
241 | return bus; | |
17a941d8 MBY |
242 | } |
243 | ||
7c2d9cd2 JM |
244 | /* |
245 | * Free a DMA mapping. | |
246 | */ | |
052aedbf FT |
247 | static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr, |
248 | size_t size, enum dma_data_direction dir, | |
00085f1e | 249 | unsigned long attrs) |
7c2d9cd2 JM |
250 | { |
251 | unsigned long iommu_page; | |
252 | int npages; | |
253 | int i; | |
254 | ||
06f55fd2 CH |
255 | if (WARN_ON_ONCE(dma_addr == DMA_MAPPING_ERROR)) |
256 | return; | |
257 | ||
258 | /* | |
259 | * This driver will not always use a GART mapping, but might have | |
260 | * created a direct mapping instead. If that is the case there is | |
261 | * nothing to unmap here. | |
262 | */ | |
263 | if (dma_addr < iommu_bus_base || | |
7c2d9cd2 JM |
264 | dma_addr >= iommu_bus_base + iommu_size) |
265 | return; | |
05fccb0e | 266 | |
7c2d9cd2 | 267 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
1477b8e5 | 268 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
7c2d9cd2 JM |
269 | for (i = 0; i < npages; i++) { |
270 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
7c2d9cd2 JM |
271 | } |
272 | free_iommu(iommu_page, npages); | |
273 | } | |
274 | ||
17a941d8 MBY |
275 | /* |
276 | * Wrapper for pci_unmap_single working with scatterlists. | |
277 | */ | |
160c1d8e | 278 | static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 279 | enum dma_data_direction dir, unsigned long attrs) |
17a941d8 | 280 | { |
9ee1bea4 | 281 | struct scatterlist *s; |
17a941d8 MBY |
282 | int i; |
283 | ||
9ee1bea4 | 284 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 285 | if (!s->dma_length || !s->length) |
17a941d8 | 286 | break; |
00085f1e | 287 | gart_unmap_page(dev, s->dma_address, s->dma_length, dir, 0); |
17a941d8 MBY |
288 | } |
289 | } | |
1da177e4 LT |
290 | |
291 | /* Fallback for dma_map_sg in case of overflow */ | |
292 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
293 | int nents, int dir) | |
294 | { | |
9ee1bea4 | 295 | struct scatterlist *s; |
1da177e4 LT |
296 | int i; |
297 | ||
298 | #ifdef CONFIG_IOMMU_DEBUG | |
123bf0e2 | 299 | pr_debug("dma_map_sg overflow\n"); |
1da177e4 LT |
300 | #endif |
301 | ||
9ee1bea4 | 302 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 303 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
304 | |
305 | if (nonforced_iommu(dev, addr, s->length)) { | |
7b22ff53 | 306 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
9e8aa6b5 | 307 | if (addr == DMA_MAPPING_ERROR) { |
05fccb0e | 308 | if (i > 0) |
00085f1e | 309 | gart_unmap_sg(dev, sg, i, dir, 0); |
05fccb0e | 310 | nents = 0; |
1da177e4 LT |
311 | sg[0].dma_length = 0; |
312 | break; | |
313 | } | |
314 | } | |
315 | s->dma_address = addr; | |
316 | s->dma_length = s->length; | |
317 | } | |
a32073bf | 318 | flush_gart(); |
05fccb0e | 319 | |
1da177e4 LT |
320 | return nents; |
321 | } | |
322 | ||
323 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
324 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
325 | int nelems, struct scatterlist *sout, | |
326 | unsigned long pages) | |
1da177e4 | 327 | { |
7b22ff53 | 328 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
05fccb0e | 329 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 330 | struct scatterlist *s; |
1da177e4 LT |
331 | int i; |
332 | ||
333 | if (iommu_start == -1) | |
334 | return -1; | |
9ee1bea4 JA |
335 | |
336 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
337 | unsigned long pages, addr; |
338 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 339 | |
9ee1bea4 JA |
340 | BUG_ON(s != start && s->offset); |
341 | if (s == start) { | |
1da177e4 LT |
342 | sout->dma_address = iommu_bus_base; |
343 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
344 | sout->dma_length = s->length; | |
05fccb0e IM |
345 | } else { |
346 | sout->dma_length += s->length; | |
1da177e4 LT |
347 | } |
348 | ||
349 | addr = phys_addr; | |
1477b8e5 | 350 | pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
05fccb0e IM |
351 | while (pages--) { |
352 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
353 | addr += PAGE_SIZE; |
354 | iommu_page++; | |
0d541064 | 355 | } |
05fccb0e IM |
356 | } |
357 | BUG_ON(iommu_page - iommu_start != pages); | |
358 | ||
1da177e4 LT |
359 | return 0; |
360 | } | |
361 | ||
05fccb0e | 362 | static inline int |
fde9a109 FT |
363 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
364 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 365 | { |
9ee1bea4 JA |
366 | if (!need) { |
367 | BUG_ON(nelems != 1); | |
e88a39de | 368 | sout->dma_address = start->dma_address; |
9ee1bea4 | 369 | sout->dma_length = start->length; |
1da177e4 | 370 | return 0; |
9ee1bea4 | 371 | } |
fde9a109 | 372 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 373 | } |
05fccb0e | 374 | |
1da177e4 LT |
375 | /* |
376 | * DMA map all entries in a scatterlist. | |
05fccb0e | 377 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 378 | */ |
160c1d8e | 379 | static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 380 | enum dma_data_direction dir, unsigned long attrs) |
1da177e4 | 381 | { |
9ee1bea4 | 382 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
383 | int need = 0, nextneed, i, out, start; |
384 | unsigned long pages = 0; | |
42d00284 FT |
385 | unsigned int seg_size; |
386 | unsigned int max_seg_size; | |
1da177e4 | 387 | |
05fccb0e | 388 | if (nents == 0) |
1da177e4 LT |
389 | return 0; |
390 | ||
123bf0e2 IM |
391 | out = 0; |
392 | start = 0; | |
393 | start_sg = sg; | |
394 | sgmap = sg; | |
395 | seg_size = 0; | |
396 | max_seg_size = dma_get_max_seg_size(dev); | |
397 | ps = NULL; /* shut up gcc */ | |
398 | ||
9ee1bea4 | 399 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 400 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 401 | |
1da177e4 | 402 | s->dma_address = addr; |
05fccb0e | 403 | BUG_ON(s->length == 0); |
1da177e4 | 404 | |
05fccb0e | 405 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
406 | |
407 | /* Handle the previous not yet processed entries */ | |
408 | if (i > start) { | |
05fccb0e IM |
409 | /* |
410 | * Can only merge when the last chunk ends on a | |
411 | * page boundary and the new one doesn't have an | |
412 | * offset. | |
413 | */ | |
1da177e4 | 414 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 415 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 416 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
417 | if (dma_map_cont(dev, start_sg, i - start, |
418 | sgmap, pages, need) < 0) | |
1da177e4 LT |
419 | goto error; |
420 | out++; | |
123bf0e2 IM |
421 | |
422 | seg_size = 0; | |
423 | sgmap = sg_next(sgmap); | |
424 | pages = 0; | |
425 | start = i; | |
426 | start_sg = s; | |
1da177e4 LT |
427 | } |
428 | } | |
429 | ||
42d00284 | 430 | seg_size += s->length; |
1da177e4 | 431 | need = nextneed; |
1477b8e5 | 432 | pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
9ee1bea4 | 433 | ps = s; |
1da177e4 | 434 | } |
fde9a109 | 435 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
436 | goto error; |
437 | out++; | |
a32073bf | 438 | flush_gart(); |
9ee1bea4 JA |
439 | if (out < nents) { |
440 | sgmap = sg_next(sgmap); | |
441 | sgmap->dma_length = 0; | |
442 | } | |
1da177e4 LT |
443 | return out; |
444 | ||
445 | error: | |
a32073bf | 446 | flush_gart(); |
00085f1e | 447 | gart_unmap_sg(dev, sg, out, dir, 0); |
05fccb0e | 448 | |
a1002a48 KV |
449 | /* When it was forced or merged try again in a dumb way */ |
450 | if (force_iommu || iommu_merge) { | |
451 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
452 | if (out > 0) | |
453 | return out; | |
454 | } | |
1da177e4 LT |
455 | if (panic_on_overflow) |
456 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 457 | |
17a941d8 | 458 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 | 459 | for_each_sg(sg, s, nents, i) |
9e8aa6b5 | 460 | s->dma_address = DMA_MAPPING_ERROR; |
1da177e4 | 461 | return 0; |
05fccb0e | 462 | } |
1da177e4 | 463 | |
94581094 JR |
464 | /* allocate and map a coherent mapping */ |
465 | static void * | |
466 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
00085f1e | 467 | gfp_t flag, unsigned long attrs) |
94581094 | 468 | { |
51c7eeba CH |
469 | void *vaddr; |
470 | ||
bc3ec75d | 471 | vaddr = dma_direct_alloc_pages(dev, size, dma_addr, flag, attrs); |
51c7eeba CH |
472 | if (!vaddr || |
473 | !force_iommu || dev->coherent_dma_mask <= DMA_BIT_MASK(24)) | |
474 | return vaddr; | |
94581094 | 475 | |
51c7eeba CH |
476 | *dma_addr = dma_map_area(dev, virt_to_phys(vaddr), size, |
477 | DMA_BIDIRECTIONAL, (1UL << get_order(size)) - 1); | |
478 | flush_gart(); | |
9e8aa6b5 | 479 | if (unlikely(*dma_addr == DMA_MAPPING_ERROR)) |
51c7eeba CH |
480 | goto out_free; |
481 | return vaddr; | |
482 | out_free: | |
bc3ec75d | 483 | dma_direct_free_pages(dev, size, vaddr, *dma_addr, attrs); |
94581094 JR |
484 | return NULL; |
485 | } | |
486 | ||
43a5a5a0 JR |
487 | /* free a coherent mapping */ |
488 | static void | |
489 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
00085f1e | 490 | dma_addr_t dma_addr, unsigned long attrs) |
43a5a5a0 | 491 | { |
00085f1e | 492 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, 0); |
bc3ec75d | 493 | dma_direct_free_pages(dev, size, vaddr, dma_addr, attrs); |
43a5a5a0 JR |
494 | } |
495 | ||
17a941d8 | 496 | static int no_agp; |
1da177e4 LT |
497 | |
498 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
499 | { |
500 | unsigned long a; | |
501 | ||
502 | if (!iommu_size) { | |
503 | iommu_size = aper_size; | |
504 | if (!no_agp) | |
505 | iommu_size /= 2; | |
506 | } | |
507 | ||
508 | a = aper + iommu_size; | |
31422c51 | 509 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 510 | |
05fccb0e | 511 | if (iommu_size < 64*1024*1024) { |
8d3bcc44 | 512 | pr_warn("PCI-DMA: Warning: Small IOMMU %luMB." |
05fccb0e | 513 | " Consider increasing the AGP aperture in BIOS\n", |
8d3bcc44 | 514 | iommu_size >> 20); |
05fccb0e IM |
515 | } |
516 | ||
1da177e4 | 517 | return iommu_size; |
05fccb0e | 518 | } |
1da177e4 | 519 | |
05fccb0e IM |
520 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
521 | { | |
522 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 523 | u64 aper_base; |
1da177e4 | 524 | |
3bb6fbf9 PM |
525 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
526 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 527 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 528 | |
05fccb0e | 529 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
530 | aper_base <<= 25; |
531 | ||
05fccb0e IM |
532 | aper_size = (32 * 1024 * 1024) << aper_order; |
533 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
534 | aper_base = 0; |
535 | ||
536 | *size = aper_size; | |
537 | return aper_base; | |
05fccb0e | 538 | } |
1da177e4 | 539 | |
6703f6d1 RW |
540 | static void enable_gart_translations(void) |
541 | { | |
542 | int i; | |
543 | ||
9653a5c7 | 544 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
545 | return; |
546 | ||
9653a5c7 HR |
547 | for (i = 0; i < amd_nb_num(); i++) { |
548 | struct pci_dev *dev = node_to_amd_nb(i)->misc; | |
6703f6d1 RW |
549 | |
550 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
551 | } | |
4b83873d JR |
552 | |
553 | /* Flush the GART-TLB to remove stale entries */ | |
eec1d4fa | 554 | amd_flush_garts(); |
6703f6d1 RW |
555 | } |
556 | ||
557 | /* | |
558 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
559 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
560 | */ | |
561 | static bool fix_up_north_bridges; | |
562 | static u32 aperture_order; | |
563 | static u32 aperture_alloc; | |
564 | ||
565 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
566 | { | |
567 | fix_up_north_bridges = true; | |
568 | aperture_order = aper_order; | |
569 | aperture_alloc = aper_alloc; | |
570 | } | |
571 | ||
f3c6ea1b | 572 | static void gart_fixup_northbridges(void) |
cd76374e | 573 | { |
123bf0e2 | 574 | int i; |
6703f6d1 | 575 | |
123bf0e2 IM |
576 | if (!fix_up_north_bridges) |
577 | return; | |
6703f6d1 | 578 | |
9653a5c7 | 579 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
580 | return; |
581 | ||
123bf0e2 | 582 | pr_info("PCI-DMA: Restoring GART aperture settings\n"); |
6703f6d1 | 583 | |
9653a5c7 HR |
584 | for (i = 0; i < amd_nb_num(); i++) { |
585 | struct pci_dev *dev = node_to_amd_nb(i)->misc; | |
6703f6d1 | 586 | |
123bf0e2 IM |
587 | /* |
588 | * Don't enable translations just yet. That is the next | |
589 | * step. Restore the pre-suspend aperture settings. | |
590 | */ | |
260133ab | 591 | gart_set_size_and_enable(dev, aperture_order); |
123bf0e2 | 592 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25); |
6703f6d1 | 593 | } |
123bf0e2 IM |
594 | } |
595 | ||
f3c6ea1b | 596 | static void gart_resume(void) |
123bf0e2 IM |
597 | { |
598 | pr_info("PCI-DMA: Resuming GART IOMMU\n"); | |
599 | ||
f3c6ea1b | 600 | gart_fixup_northbridges(); |
6703f6d1 RW |
601 | |
602 | enable_gart_translations(); | |
cd76374e PM |
603 | } |
604 | ||
f3c6ea1b | 605 | static struct syscore_ops gart_syscore_ops = { |
123bf0e2 | 606 | .resume = gart_resume, |
cd76374e PM |
607 | |
608 | }; | |
609 | ||
05fccb0e | 610 | /* |
1da177e4 | 611 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 612 | * AGP driver for some reason. |
1da177e4 | 613 | */ |
eec1d4fa | 614 | static __init int init_amd_gatt(struct agp_kern_info *info) |
05fccb0e IM |
615 | { |
616 | unsigned aper_size, gatt_size, new_aper_size; | |
617 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
618 | struct pci_dev *dev; |
619 | void *gatt; | |
f3c6ea1b | 620 | int i; |
a32073bf | 621 | |
123bf0e2 IM |
622 | pr_info("PCI-DMA: Disabling AGP.\n"); |
623 | ||
1da177e4 | 624 | aper_size = aper_base = info->aper_size = 0; |
a32073bf | 625 | dev = NULL; |
9653a5c7 HR |
626 | for (i = 0; i < amd_nb_num(); i++) { |
627 | dev = node_to_amd_nb(i)->misc; | |
05fccb0e IM |
628 | new_aper_base = read_aperture(dev, &new_aper_size); |
629 | if (!new_aper_base) | |
630 | goto nommu; | |
631 | ||
632 | if (!aper_base) { | |
1da177e4 LT |
633 | aper_size = new_aper_size; |
634 | aper_base = new_aper_base; | |
05fccb0e IM |
635 | } |
636 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
637 | goto nommu; |
638 | } | |
639 | if (!aper_base) | |
05fccb0e | 640 | goto nommu; |
123bf0e2 | 641 | |
1da177e4 | 642 | info->aper_base = aper_base; |
05fccb0e | 643 | info->aper_size = aper_size >> 20; |
1da177e4 | 644 | |
05fccb0e | 645 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
0114267b JR |
646 | gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
647 | get_order(gatt_size)); | |
05fccb0e | 648 | if (!gatt) |
cf6387da | 649 | panic("Cannot allocate GATT table"); |
6d238cc4 | 650 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 651 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 652 | |
1da177e4 | 653 | agp_gatt_table = gatt; |
a32073bf | 654 | |
f3c6ea1b | 655 | register_syscore_ops(&gart_syscore_ops); |
6703f6d1 | 656 | |
a32073bf | 657 | flush_gart(); |
05fccb0e | 658 | |
123bf0e2 | 659 | pr_info("PCI-DMA: aperture base @ %x size %u KB\n", |
05fccb0e | 660 | aper_base, aper_size>>10); |
7ab073b6 | 661 | |
1da177e4 LT |
662 | return 0; |
663 | ||
664 | nommu: | |
05fccb0e | 665 | /* Should not happen anymore */ |
8d3bcc44 | 666 | pr_warn("PCI-DMA: More than 4GB of RAM and no IOMMU - falling back to iommu=soft.\n"); |
05fccb0e IM |
667 | return -1; |
668 | } | |
1da177e4 | 669 | |
5299709d | 670 | static const struct dma_map_ops gart_dma_ops = { |
05fccb0e IM |
671 | .map_sg = gart_map_sg, |
672 | .unmap_sg = gart_unmap_sg, | |
052aedbf FT |
673 | .map_page = gart_map_page, |
674 | .unmap_page = gart_unmap_page, | |
baa676fc AP |
675 | .alloc = gart_alloc_coherent, |
676 | .free = gart_free_coherent, | |
f9f3232a CH |
677 | .mmap = dma_common_mmap, |
678 | .get_sgtable = dma_common_get_sgtable, | |
fec777c3 | 679 | .dma_supported = dma_direct_supported, |
249baa54 | 680 | .get_required_mask = dma_direct_get_required_mask, |
17a941d8 MBY |
681 | }; |
682 | ||
338bac52 | 683 | static void gart_iommu_shutdown(void) |
bc2cea6a YL |
684 | { |
685 | struct pci_dev *dev; | |
686 | int i; | |
687 | ||
f3eee542 YL |
688 | /* don't shutdown it if there is AGP installed */ |
689 | if (!no_agp) | |
bc2cea6a YL |
690 | return; |
691 | ||
9653a5c7 | 692 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
693 | return; |
694 | ||
9653a5c7 | 695 | for (i = 0; i < amd_nb_num(); i++) { |
05fccb0e | 696 | u32 ctl; |
bc2cea6a | 697 | |
9653a5c7 | 698 | dev = node_to_amd_nb(i)->misc; |
3bb6fbf9 | 699 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 700 | |
3bb6fbf9 | 701 | ctl &= ~GARTEN; |
bc2cea6a | 702 | |
3bb6fbf9 | 703 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 704 | } |
bc2cea6a YL |
705 | } |
706 | ||
de957628 | 707 | int __init gart_iommu_init(void) |
05fccb0e | 708 | { |
1da177e4 | 709 | struct agp_kern_info info; |
1da177e4 | 710 | unsigned long iommu_start; |
d99e9016 YL |
711 | unsigned long aper_base, aper_size; |
712 | unsigned long start_pfn, end_pfn; | |
1da177e4 | 713 | unsigned long scratch; |
1da177e4 | 714 | |
9653a5c7 | 715 | if (!amd_nb_has_feature(AMD_NB_GART)) |
de957628 | 716 | return 0; |
a32073bf | 717 | |
1da177e4 | 718 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 719 | no_agp = 1; |
1da177e4 LT |
720 | #else |
721 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
eec1d4fa | 722 | /* Add other AMD AGP bridge drivers here */ |
05fccb0e IM |
723 | no_agp = no_agp || |
724 | (agp_amd64_init() < 0) || | |
1da177e4 | 725 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 726 | #endif |
1da177e4 | 727 | |
1da177e4 | 728 | if (no_iommu || |
c987d12f | 729 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 730 | !gart_iommu_aperture || |
eec1d4fa | 731 | (no_agp && init_amd_gatt(&info) < 0)) { |
c987d12f | 732 | if (max_pfn > MAX_DMA32_PFN) { |
8d3bcc44 KW |
733 | pr_warn("More than 4GB of memory but GART IOMMU not available.\n"); |
734 | pr_warn("falling back to iommu=soft.\n"); | |
5b7b644c | 735 | } |
de957628 | 736 | return 0; |
1da177e4 LT |
737 | } |
738 | ||
d99e9016 | 739 | /* need to map that range */ |
123bf0e2 IM |
740 | aper_size = info.aper_size << 20; |
741 | aper_base = info.aper_base; | |
742 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
743 | ||
5101730c YL |
744 | start_pfn = PFN_DOWN(aper_base); |
745 | if (!pfn_range_is_mapped(start_pfn, end_pfn)) | |
c164fbb4 LG |
746 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT, |
747 | PAGE_KERNEL); | |
d99e9016 | 748 | |
123bf0e2 | 749 | pr_info("PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
750 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
751 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
752 | ||
0114267b | 753 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, |
05fccb0e IM |
754 | get_order(iommu_pages/8)); |
755 | if (!iommu_gart_bitmap) | |
756 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 | 757 | |
123bf0e2 | 758 | pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", |
05fccb0e | 759 | iommu_size >> 20); |
1da177e4 | 760 | |
123bf0e2 IM |
761 | agp_memory_reserved = iommu_size; |
762 | iommu_start = aper_size - iommu_size; | |
763 | iommu_bus_base = info.aper_base + iommu_start; | |
123bf0e2 | 764 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); |
1da177e4 | 765 | |
05fccb0e | 766 | /* |
1da177e4 LT |
767 | * Unmap the IOMMU part of the GART. The alias of the page is |
768 | * always mapped with cache enabled and there is no full cache | |
769 | * coherency across the GART remapping. The unmapping avoids | |
770 | * automatic prefetches from the CPU allocating cache lines in | |
771 | * there. All CPU accesses are done via the direct mapping to | |
772 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 773 | * devices. |
1da177e4 | 774 | */ |
28d6ee41 AK |
775 | set_memory_np((unsigned long)__va(iommu_bus_base), |
776 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
777 | /* |
778 | * Tricky. The GART table remaps the physical memory range, | |
779 | * so the CPU wont notice potential aliases and if the memory | |
780 | * is remapped to UC later on, we might surprise the PCI devices | |
781 | * with a stray writeout of a cacheline. So play it sure and | |
782 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
783 | * the pages as Not-Present: | |
784 | */ | |
785 | wbinvd(); | |
123bf0e2 | 786 | |
fe2245c9 ML |
787 | /* |
788 | * Now all caches are flushed and we can safely enable | |
789 | * GART hardware. Doing it early leaves the possibility | |
790 | * of stale cache entries that can lead to GART PTE | |
791 | * errors. | |
792 | */ | |
793 | enable_gart_translations(); | |
1da177e4 | 794 | |
05fccb0e | 795 | /* |
fa3d319a | 796 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 797 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 798 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 799 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 800 | */ |
05fccb0e IM |
801 | scratch = get_zeroed_page(GFP_KERNEL); |
802 | if (!scratch) | |
1da177e4 LT |
803 | panic("Cannot allocate iommu scratch page"); |
804 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
1da177e4 | 805 | |
a32073bf | 806 | flush_gart(); |
17a941d8 | 807 | dma_ops = &gart_dma_ops; |
338bac52 | 808 | x86_platform.iommu_shutdown = gart_iommu_shutdown; |
75f1cdf1 | 809 | swiotlb = 0; |
de957628 FT |
810 | |
811 | return 0; | |
05fccb0e | 812 | } |
1da177e4 | 813 | |
43999d9e | 814 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
815 | { |
816 | int arg; | |
817 | ||
17a941d8 MBY |
818 | if (isdigit(*p) && get_option(&p, &arg)) |
819 | iommu_size = arg; | |
41855b77 | 820 | if (!strncmp(p, "fullflush", 9)) |
17a941d8 | 821 | iommu_fullflush = 1; |
05fccb0e | 822 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 823 | iommu_fullflush = 0; |
05fccb0e | 824 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 825 | no_agp = 1; |
05fccb0e | 826 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
827 | fix_aperture = 0; |
828 | /* duplicated from pci-dma.c */ | |
05fccb0e | 829 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 830 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 831 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 832 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
833 | if (!strncmp(p, "memaper", 7)) { |
834 | fallback_aper_force = 1; | |
835 | p += 7; | |
836 | if (*p == '=') { | |
837 | ++p; | |
838 | if (get_option(&p, &arg)) | |
839 | fallback_aper_order = arg; | |
840 | } | |
841 | } | |
842 | } | |
22e6daf4 | 843 | IOMMU_INIT_POST(gart_iommu_hole_init); |