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Commit | Line | Data |
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b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
bd0e5211 JR |
60 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
61 | struct unity_map_entry *e); | |
e275a2a0 | 62 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bc3e127 | 63 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
64 | unsigned long address, int end_lvl, |
65 | u64 **pte_page, gfp_t gfp); | |
00cd122a JR |
66 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
67 | unsigned long start_page, | |
68 | unsigned int pages); | |
a345b23b | 69 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
9355a081 | 70 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 71 | unsigned long address, int map_size); |
04bfdd84 | 72 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 73 | |
7f26508b JR |
74 | #ifdef CONFIG_AMD_IOMMU_STATS |
75 | ||
76 | /* | |
77 | * Initialization code for statistics collection | |
78 | */ | |
79 | ||
da49f6df | 80 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 81 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 82 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 83 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 84 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 85 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 86 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 87 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 88 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 89 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 90 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 91 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 92 | |
7f26508b JR |
93 | static struct dentry *stats_dir; |
94 | static struct dentry *de_isolate; | |
95 | static struct dentry *de_fflush; | |
96 | ||
97 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
98 | { | |
99 | if (stats_dir == NULL) | |
100 | return; | |
101 | ||
102 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
103 | &cnt->value); | |
104 | } | |
105 | ||
106 | static void amd_iommu_stats_init(void) | |
107 | { | |
108 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
109 | if (stats_dir == NULL) | |
110 | return; | |
111 | ||
112 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
113 | (u32 *)&amd_iommu_isolate); | |
114 | ||
115 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
116 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
117 | |
118 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 119 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 120 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 121 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 122 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 123 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 124 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 125 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 126 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 127 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 128 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 129 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
130 | } |
131 | ||
132 | #endif | |
133 | ||
431b2a20 | 134 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
135 | static int iommu_has_npcache(struct amd_iommu *iommu) |
136 | { | |
ae9b9403 | 137 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
138 | } |
139 | ||
a80dc3e0 JR |
140 | /**************************************************************************** |
141 | * | |
142 | * Interrupt handling functions | |
143 | * | |
144 | ****************************************************************************/ | |
145 | ||
e3e59876 JR |
146 | static void dump_dte_entry(u16 devid) |
147 | { | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < 8; ++i) | |
151 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
152 | amd_iommu_dev_table[devid].data[i]); | |
153 | } | |
154 | ||
945b4ac4 JR |
155 | static void dump_command(unsigned long phys_addr) |
156 | { | |
157 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
158 | int i; | |
159 | ||
160 | for (i = 0; i < 4; ++i) | |
161 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
162 | } | |
163 | ||
a345b23b | 164 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
165 | { |
166 | u32 *event = __evt; | |
167 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
168 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
169 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
170 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
171 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
172 | ||
4c6f40d4 | 173 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
174 | |
175 | switch (type) { | |
176 | case EVENT_TYPE_ILL_DEV: | |
177 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
178 | "address=0x%016llx flags=0x%04x]\n", | |
179 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
180 | address, flags); | |
e3e59876 | 181 | dump_dte_entry(devid); |
90008ee4 JR |
182 | break; |
183 | case EVENT_TYPE_IO_FAULT: | |
184 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
185 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
186 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
187 | domid, address, flags); | |
188 | break; | |
189 | case EVENT_TYPE_DEV_TAB_ERR: | |
190 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
191 | "address=0x%016llx flags=0x%04x]\n", | |
192 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
193 | address, flags); | |
194 | break; | |
195 | case EVENT_TYPE_PAGE_TAB_ERR: | |
196 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
197 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
198 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
199 | domid, address, flags); | |
200 | break; | |
201 | case EVENT_TYPE_ILL_CMD: | |
202 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 203 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 204 | dump_command(address); |
90008ee4 JR |
205 | break; |
206 | case EVENT_TYPE_CMD_HARD_ERR: | |
207 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
208 | "flags=0x%04x]\n", address, flags); | |
209 | break; | |
210 | case EVENT_TYPE_IOTLB_INV_TO: | |
211 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
212 | "address=0x%016llx]\n", | |
213 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
214 | address); | |
215 | break; | |
216 | case EVENT_TYPE_INV_DEV_REQ: | |
217 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
218 | "address=0x%016llx flags=0x%04x]\n", | |
219 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
220 | address, flags); | |
221 | break; | |
222 | default: | |
223 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
224 | } | |
225 | } | |
226 | ||
227 | static void iommu_poll_events(struct amd_iommu *iommu) | |
228 | { | |
229 | u32 head, tail; | |
230 | unsigned long flags; | |
231 | ||
232 | spin_lock_irqsave(&iommu->lock, flags); | |
233 | ||
234 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
235 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
236 | ||
237 | while (head != tail) { | |
a345b23b | 238 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
239 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
240 | } | |
241 | ||
242 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
243 | ||
244 | spin_unlock_irqrestore(&iommu->lock, flags); | |
245 | } | |
246 | ||
a80dc3e0 JR |
247 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
248 | { | |
90008ee4 JR |
249 | struct amd_iommu *iommu; |
250 | ||
3bd22172 | 251 | for_each_iommu(iommu) |
90008ee4 JR |
252 | iommu_poll_events(iommu); |
253 | ||
254 | return IRQ_HANDLED; | |
a80dc3e0 JR |
255 | } |
256 | ||
431b2a20 JR |
257 | /**************************************************************************** |
258 | * | |
259 | * IOMMU command queuing functions | |
260 | * | |
261 | ****************************************************************************/ | |
262 | ||
263 | /* | |
264 | * Writes the command to the IOMMUs command buffer and informs the | |
265 | * hardware about the new command. Must be called with iommu->lock held. | |
266 | */ | |
d6449536 | 267 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
268 | { |
269 | u32 tail, head; | |
270 | u8 *target; | |
271 | ||
272 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 273 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
274 | memcpy_toio(target, cmd, sizeof(*cmd)); |
275 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
276 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
277 | if (tail == head) | |
278 | return -ENOMEM; | |
279 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
431b2a20 JR |
284 | /* |
285 | * General queuing function for commands. Takes iommu->lock and calls | |
286 | * __iommu_queue_command(). | |
287 | */ | |
d6449536 | 288 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
289 | { |
290 | unsigned long flags; | |
291 | int ret; | |
292 | ||
293 | spin_lock_irqsave(&iommu->lock, flags); | |
294 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 295 | if (!ret) |
0cfd7aa9 | 296 | iommu->need_sync = true; |
a19ae1ec JR |
297 | spin_unlock_irqrestore(&iommu->lock, flags); |
298 | ||
299 | return ret; | |
300 | } | |
301 | ||
8d201968 JR |
302 | /* |
303 | * This function waits until an IOMMU has completed a completion | |
304 | * wait command | |
305 | */ | |
306 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
307 | { | |
308 | int ready = 0; | |
309 | unsigned status = 0; | |
310 | unsigned long i = 0; | |
311 | ||
da49f6df JR |
312 | INC_STATS_COUNTER(compl_wait); |
313 | ||
8d201968 JR |
314 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
315 | ++i; | |
316 | /* wait for the bit to become one */ | |
317 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
318 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
319 | } | |
320 | ||
321 | /* set bit back to zero */ | |
322 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
323 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
324 | ||
6a1eddd2 JR |
325 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
326 | spin_unlock(&iommu->lock); | |
327 | reset_iommu_command_buffer(iommu); | |
328 | spin_lock(&iommu->lock); | |
329 | } | |
8d201968 JR |
330 | } |
331 | ||
332 | /* | |
333 | * This function queues a completion wait command into the command | |
334 | * buffer of an IOMMU | |
335 | */ | |
336 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
337 | { | |
338 | struct iommu_cmd cmd; | |
339 | ||
340 | memset(&cmd, 0, sizeof(cmd)); | |
341 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
342 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
343 | ||
344 | return __iommu_queue_command(iommu, &cmd); | |
345 | } | |
346 | ||
431b2a20 JR |
347 | /* |
348 | * This function is called whenever we need to ensure that the IOMMU has | |
349 | * completed execution of all commands we sent. It sends a | |
350 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
351 | * us about that by writing a value to a physical address we pass with | |
352 | * the command. | |
353 | */ | |
a19ae1ec JR |
354 | static int iommu_completion_wait(struct amd_iommu *iommu) |
355 | { | |
8d201968 JR |
356 | int ret = 0; |
357 | unsigned long flags; | |
a19ae1ec | 358 | |
7e4f88da JR |
359 | spin_lock_irqsave(&iommu->lock, flags); |
360 | ||
09ee17eb JR |
361 | if (!iommu->need_sync) |
362 | goto out; | |
363 | ||
8d201968 | 364 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 365 | |
0cfd7aa9 | 366 | iommu->need_sync = false; |
a19ae1ec JR |
367 | |
368 | if (ret) | |
7e4f88da | 369 | goto out; |
a19ae1ec | 370 | |
8d201968 | 371 | __iommu_wait_for_completion(iommu); |
84df8175 | 372 | |
7e4f88da JR |
373 | out: |
374 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
0518a3a4 JR |
379 | static void iommu_flush_complete(struct protection_domain *domain) |
380 | { | |
381 | int i; | |
382 | ||
383 | for (i = 0; i < amd_iommus_present; ++i) { | |
384 | if (!domain->dev_iommu[i]) | |
385 | continue; | |
386 | ||
387 | /* | |
388 | * Devices of this domain are behind this IOMMU | |
389 | * We need to wait for completion of all commands. | |
390 | */ | |
391 | iommu_completion_wait(amd_iommus[i]); | |
392 | } | |
393 | } | |
394 | ||
431b2a20 JR |
395 | /* |
396 | * Command send function for invalidating a device table entry | |
397 | */ | |
a19ae1ec JR |
398 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
399 | { | |
d6449536 | 400 | struct iommu_cmd cmd; |
ee2fa743 | 401 | int ret; |
a19ae1ec JR |
402 | |
403 | BUG_ON(iommu == NULL); | |
404 | ||
405 | memset(&cmd, 0, sizeof(cmd)); | |
406 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
407 | cmd.data[0] = devid; | |
408 | ||
ee2fa743 JR |
409 | ret = iommu_queue_command(iommu, &cmd); |
410 | ||
ee2fa743 | 411 | return ret; |
a19ae1ec JR |
412 | } |
413 | ||
237b6f33 JR |
414 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
415 | u16 domid, int pde, int s) | |
416 | { | |
417 | memset(cmd, 0, sizeof(*cmd)); | |
418 | address &= PAGE_MASK; | |
419 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
420 | cmd->data[1] |= domid; | |
421 | cmd->data[2] = lower_32_bits(address); | |
422 | cmd->data[3] = upper_32_bits(address); | |
423 | if (s) /* size bit - we flush more than one 4kb page */ | |
424 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
425 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
426 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
427 | } | |
428 | ||
431b2a20 JR |
429 | /* |
430 | * Generic command send function for invalidaing TLB entries | |
431 | */ | |
a19ae1ec JR |
432 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
433 | u64 address, u16 domid, int pde, int s) | |
434 | { | |
d6449536 | 435 | struct iommu_cmd cmd; |
ee2fa743 | 436 | int ret; |
a19ae1ec | 437 | |
237b6f33 | 438 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 439 | |
ee2fa743 JR |
440 | ret = iommu_queue_command(iommu, &cmd); |
441 | ||
ee2fa743 | 442 | return ret; |
a19ae1ec JR |
443 | } |
444 | ||
431b2a20 JR |
445 | /* |
446 | * TLB invalidation function which is called from the mapping functions. | |
447 | * It invalidates a single PTE if the range to flush is within a single | |
448 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
449 | */ | |
a19ae1ec JR |
450 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
451 | u64 address, size_t size) | |
452 | { | |
999ba417 | 453 | int s = 0; |
e3c449f5 | 454 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
455 | |
456 | address &= PAGE_MASK; | |
457 | ||
999ba417 JR |
458 | if (pages > 1) { |
459 | /* | |
460 | * If we have to flush more than one page, flush all | |
461 | * TLB entries for this domain | |
462 | */ | |
463 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
464 | s = 1; | |
a19ae1ec JR |
465 | } |
466 | ||
999ba417 JR |
467 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
468 | ||
a19ae1ec JR |
469 | return 0; |
470 | } | |
b6c02715 | 471 | |
1c655773 JR |
472 | /* Flush the whole IO/TLB for a given protection domain */ |
473 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
474 | { | |
475 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
476 | ||
f57d98ae JR |
477 | INC_STATS_COUNTER(domain_flush_single); |
478 | ||
1c655773 JR |
479 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
480 | } | |
481 | ||
42a49f96 CW |
482 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
483 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
484 | { | |
485 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
486 | ||
487 | INC_STATS_COUNTER(domain_flush_single); | |
488 | ||
489 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
490 | } | |
491 | ||
43f49609 | 492 | /* |
e394d72a | 493 | * This function flushes one domain on one IOMMU |
43f49609 | 494 | */ |
e394d72a | 495 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 496 | { |
43f49609 | 497 | struct iommu_cmd cmd; |
e394d72a | 498 | unsigned long flags; |
18811f55 | 499 | |
43f49609 JR |
500 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
501 | domid, 1, 1); | |
502 | ||
e394d72a JR |
503 | spin_lock_irqsave(&iommu->lock, flags); |
504 | __iommu_queue_command(iommu, &cmd); | |
505 | __iommu_completion_wait(iommu); | |
506 | __iommu_wait_for_completion(iommu); | |
507 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 508 | } |
43f49609 | 509 | |
e394d72a | 510 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
511 | { |
512 | int i; | |
513 | ||
514 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
515 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
516 | continue; | |
e394d72a | 517 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 518 | } |
e394d72a JR |
519 | |
520 | } | |
521 | ||
43f49609 JR |
522 | /* |
523 | * This function is used to flush the IO/TLB for a given protection domain | |
524 | * on every IOMMU in the system | |
525 | */ | |
526 | static void iommu_flush_domain(u16 domid) | |
527 | { | |
43f49609 | 528 | struct amd_iommu *iommu; |
43f49609 | 529 | |
18811f55 JR |
530 | INC_STATS_COUNTER(domain_flush_all); |
531 | ||
e394d72a JR |
532 | for_each_iommu(iommu) |
533 | flush_domain_on_iommu(iommu, domid); | |
43f49609 | 534 | } |
43f49609 | 535 | |
bfd1be18 | 536 | void amd_iommu_flush_all_domains(void) |
e394d72a JR |
537 | { |
538 | struct amd_iommu *iommu; | |
539 | ||
540 | for_each_iommu(iommu) | |
541 | flush_all_domains_on_iommu(iommu); | |
bfd1be18 JR |
542 | } |
543 | ||
d586d785 | 544 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
545 | { |
546 | int i; | |
547 | ||
d586d785 JR |
548 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
549 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 550 | continue; |
d586d785 JR |
551 | |
552 | iommu_queue_inv_dev_entry(iommu, i); | |
553 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
554 | } |
555 | } | |
556 | ||
6a0dbcbe | 557 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
558 | { |
559 | struct amd_iommu *iommu; | |
560 | int i; | |
561 | ||
562 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
563 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
564 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
565 | continue; |
566 | ||
567 | iommu = amd_iommu_rlookup_table[i]; | |
568 | if (!iommu) | |
569 | continue; | |
570 | ||
571 | iommu_queue_inv_dev_entry(iommu, i); | |
572 | iommu_completion_wait(iommu); | |
573 | } | |
574 | } | |
575 | ||
a345b23b JR |
576 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
577 | { | |
578 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
579 | ||
b26e81b8 JR |
580 | if (iommu->reset_in_progress) |
581 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
582 | ||
583 | iommu->reset_in_progress = true; | |
584 | ||
a345b23b JR |
585 | amd_iommu_reset_cmd_buffer(iommu); |
586 | flush_all_devices_for_iommu(iommu); | |
587 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
588 | |
589 | iommu->reset_in_progress = false; | |
a345b23b JR |
590 | } |
591 | ||
6a0dbcbe JR |
592 | void amd_iommu_flush_all_devices(void) |
593 | { | |
594 | flush_devices_by_domain(NULL); | |
595 | } | |
596 | ||
431b2a20 JR |
597 | /**************************************************************************** |
598 | * | |
599 | * The functions below are used the create the page table mappings for | |
600 | * unity mapped regions. | |
601 | * | |
602 | ****************************************************************************/ | |
603 | ||
604 | /* | |
605 | * Generic mapping functions. It maps a physical address into a DMA | |
606 | * address space. It allocates the page table pages if necessary. | |
607 | * In the future it can be extended to a generic mapping function | |
608 | * supporting all features of AMD IOMMU page tables like level skipping | |
609 | * and full 64 bit address spaces. | |
610 | */ | |
38e817fe JR |
611 | static int iommu_map_page(struct protection_domain *dom, |
612 | unsigned long bus_addr, | |
613 | unsigned long phys_addr, | |
abdc5eb3 JR |
614 | int prot, |
615 | int map_size) | |
bd0e5211 | 616 | { |
8bda3092 | 617 | u64 __pte, *pte; |
bd0e5211 JR |
618 | |
619 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 620 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 621 | |
abdc5eb3 JR |
622 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
623 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
624 | ||
bad1cac2 | 625 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
626 | return -EINVAL; |
627 | ||
abdc5eb3 | 628 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
629 | |
630 | if (IOMMU_PTE_PRESENT(*pte)) | |
631 | return -EBUSY; | |
632 | ||
633 | __pte = phys_addr | IOMMU_PTE_P; | |
634 | if (prot & IOMMU_PROT_IR) | |
635 | __pte |= IOMMU_PTE_IR; | |
636 | if (prot & IOMMU_PROT_IW) | |
637 | __pte |= IOMMU_PTE_IW; | |
638 | ||
639 | *pte = __pte; | |
640 | ||
04bfdd84 JR |
641 | update_domain(dom); |
642 | ||
bd0e5211 JR |
643 | return 0; |
644 | } | |
645 | ||
eb74ff6c | 646 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 647 | unsigned long bus_addr, int map_size) |
eb74ff6c | 648 | { |
a6b256b4 | 649 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 650 | |
38a76eee JR |
651 | if (pte) |
652 | *pte = 0; | |
eb74ff6c | 653 | } |
eb74ff6c | 654 | |
431b2a20 JR |
655 | /* |
656 | * This function checks if a specific unity mapping entry is needed for | |
657 | * this specific IOMMU. | |
658 | */ | |
bd0e5211 JR |
659 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
660 | struct unity_map_entry *entry) | |
661 | { | |
662 | u16 bdf, i; | |
663 | ||
664 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
665 | bdf = amd_iommu_alias_table[i]; | |
666 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
667 | return 1; | |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
431b2a20 JR |
673 | /* |
674 | * Init the unity mappings for a specific IOMMU in the system | |
675 | * | |
676 | * Basically iterates over all unity mapping entries and applies them to | |
677 | * the default domain DMA of that IOMMU if necessary. | |
678 | */ | |
bd0e5211 JR |
679 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
680 | { | |
681 | struct unity_map_entry *entry; | |
682 | int ret; | |
683 | ||
684 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
685 | if (!iommu_for_unity_map(iommu, entry)) | |
686 | continue; | |
687 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
688 | if (ret) | |
689 | return ret; | |
690 | } | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
431b2a20 JR |
695 | /* |
696 | * This function actually applies the mapping to the page table of the | |
697 | * dma_ops domain. | |
698 | */ | |
bd0e5211 JR |
699 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
700 | struct unity_map_entry *e) | |
701 | { | |
702 | u64 addr; | |
703 | int ret; | |
704 | ||
705 | for (addr = e->address_start; addr < e->address_end; | |
706 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
707 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
708 | PM_MAP_4k); | |
bd0e5211 JR |
709 | if (ret) |
710 | return ret; | |
711 | /* | |
712 | * if unity mapping is in aperture range mark the page | |
713 | * as allocated in the aperture | |
714 | */ | |
715 | if (addr < dma_dom->aperture_size) | |
c3239567 | 716 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 717 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
718 | } |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
431b2a20 JR |
723 | /* |
724 | * Inits the unity mappings required for a specific device | |
725 | */ | |
bd0e5211 JR |
726 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
727 | u16 devid) | |
728 | { | |
729 | struct unity_map_entry *e; | |
730 | int ret; | |
731 | ||
732 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
733 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
734 | continue; | |
735 | ret = dma_ops_unity_map(dma_dom, e); | |
736 | if (ret) | |
737 | return ret; | |
738 | } | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
431b2a20 JR |
743 | /**************************************************************************** |
744 | * | |
745 | * The next functions belong to the address allocator for the dma_ops | |
746 | * interface functions. They work like the allocators in the other IOMMU | |
747 | * drivers. Its basically a bitmap which marks the allocated pages in | |
748 | * the aperture. Maybe it could be enhanced in the future to a more | |
749 | * efficient allocator. | |
750 | * | |
751 | ****************************************************************************/ | |
d3086444 | 752 | |
431b2a20 | 753 | /* |
384de729 | 754 | * The address allocator core functions. |
431b2a20 JR |
755 | * |
756 | * called with domain->lock held | |
757 | */ | |
384de729 | 758 | |
00cd122a JR |
759 | /* |
760 | * This function checks if there is a PTE for a given dma address. If | |
761 | * there is one, it returns the pointer to it. | |
762 | */ | |
9355a081 | 763 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 764 | unsigned long address, int map_size) |
00cd122a | 765 | { |
9355a081 | 766 | int level; |
00cd122a JR |
767 | u64 *pte; |
768 | ||
9355a081 JR |
769 | level = domain->mode - 1; |
770 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 771 | |
a6b256b4 | 772 | while (level > map_size) { |
9355a081 JR |
773 | if (!IOMMU_PTE_PRESENT(*pte)) |
774 | return NULL; | |
00cd122a | 775 | |
9355a081 | 776 | level -= 1; |
00cd122a | 777 | |
9355a081 JR |
778 | pte = IOMMU_PTE_PAGE(*pte); |
779 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 780 | |
a6b256b4 JR |
781 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { |
782 | pte = NULL; | |
783 | break; | |
784 | } | |
9355a081 | 785 | } |
00cd122a JR |
786 | |
787 | return pte; | |
788 | } | |
789 | ||
9cabe89b JR |
790 | /* |
791 | * This function is used to add a new aperture range to an existing | |
792 | * aperture in case of dma_ops domain allocation or address allocation | |
793 | * failure. | |
794 | */ | |
00cd122a JR |
795 | static int alloc_new_range(struct amd_iommu *iommu, |
796 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
797 | bool populate, gfp_t gfp) |
798 | { | |
799 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 800 | int i; |
9cabe89b | 801 | |
f5e9705c JR |
802 | #ifdef CONFIG_IOMMU_STRESS |
803 | populate = false; | |
804 | #endif | |
805 | ||
9cabe89b JR |
806 | if (index >= APERTURE_MAX_RANGES) |
807 | return -ENOMEM; | |
808 | ||
809 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
810 | if (!dma_dom->aperture[index]) | |
811 | return -ENOMEM; | |
812 | ||
813 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
814 | if (!dma_dom->aperture[index]->bitmap) | |
815 | goto out_free; | |
816 | ||
817 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
818 | ||
819 | if (populate) { | |
820 | unsigned long address = dma_dom->aperture_size; | |
821 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
822 | u64 *pte, *pte_page; | |
823 | ||
824 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 825 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
826 | &pte_page, gfp); |
827 | if (!pte) | |
828 | goto out_free; | |
829 | ||
830 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
831 | ||
832 | address += APERTURE_RANGE_SIZE / 64; | |
833 | } | |
834 | } | |
835 | ||
836 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
837 | ||
00cd122a JR |
838 | /* Intialize the exclusion range if necessary */ |
839 | if (iommu->exclusion_start && | |
840 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
841 | iommu->exclusion_start < dma_dom->aperture_size) { | |
842 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
843 | int pages = iommu_num_pages(iommu->exclusion_start, | |
844 | iommu->exclusion_length, | |
845 | PAGE_SIZE); | |
846 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
847 | } | |
848 | ||
849 | /* | |
850 | * Check for areas already mapped as present in the new aperture | |
851 | * range and mark those pages as reserved in the allocator. Such | |
852 | * mappings may already exist as a result of requested unity | |
853 | * mappings for devices. | |
854 | */ | |
855 | for (i = dma_dom->aperture[index]->offset; | |
856 | i < dma_dom->aperture_size; | |
857 | i += PAGE_SIZE) { | |
a6b256b4 | 858 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
859 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
860 | continue; | |
861 | ||
862 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
863 | } | |
864 | ||
04bfdd84 JR |
865 | update_domain(&dma_dom->domain); |
866 | ||
9cabe89b JR |
867 | return 0; |
868 | ||
869 | out_free: | |
04bfdd84 JR |
870 | update_domain(&dma_dom->domain); |
871 | ||
9cabe89b JR |
872 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
873 | ||
874 | kfree(dma_dom->aperture[index]); | |
875 | dma_dom->aperture[index] = NULL; | |
876 | ||
877 | return -ENOMEM; | |
878 | } | |
879 | ||
384de729 JR |
880 | static unsigned long dma_ops_area_alloc(struct device *dev, |
881 | struct dma_ops_domain *dom, | |
882 | unsigned int pages, | |
883 | unsigned long align_mask, | |
884 | u64 dma_mask, | |
885 | unsigned long start) | |
886 | { | |
803b8cb4 | 887 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
888 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
889 | int i = start >> APERTURE_RANGE_SHIFT; | |
890 | unsigned long boundary_size; | |
891 | unsigned long address = -1; | |
892 | unsigned long limit; | |
893 | ||
803b8cb4 JR |
894 | next_bit >>= PAGE_SHIFT; |
895 | ||
384de729 JR |
896 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
897 | PAGE_SIZE) >> PAGE_SHIFT; | |
898 | ||
899 | for (;i < max_index; ++i) { | |
900 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
901 | ||
902 | if (dom->aperture[i]->offset >= dma_mask) | |
903 | break; | |
904 | ||
905 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
906 | dma_mask >> PAGE_SHIFT); | |
907 | ||
908 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
909 | limit, next_bit, pages, 0, | |
910 | boundary_size, align_mask); | |
911 | if (address != -1) { | |
912 | address = dom->aperture[i]->offset + | |
913 | (address << PAGE_SHIFT); | |
803b8cb4 | 914 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
915 | break; |
916 | } | |
917 | ||
918 | next_bit = 0; | |
919 | } | |
920 | ||
921 | return address; | |
922 | } | |
923 | ||
d3086444 JR |
924 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
925 | struct dma_ops_domain *dom, | |
6d4f343f | 926 | unsigned int pages, |
832a90c3 JR |
927 | unsigned long align_mask, |
928 | u64 dma_mask) | |
d3086444 | 929 | { |
d3086444 | 930 | unsigned long address; |
d3086444 | 931 | |
fe16f088 JR |
932 | #ifdef CONFIG_IOMMU_STRESS |
933 | dom->next_address = 0; | |
934 | dom->need_flush = true; | |
935 | #endif | |
d3086444 | 936 | |
384de729 | 937 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 938 | dma_mask, dom->next_address); |
d3086444 | 939 | |
1c655773 | 940 | if (address == -1) { |
803b8cb4 | 941 | dom->next_address = 0; |
384de729 JR |
942 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
943 | dma_mask, 0); | |
1c655773 JR |
944 | dom->need_flush = true; |
945 | } | |
d3086444 | 946 | |
384de729 | 947 | if (unlikely(address == -1)) |
8fd524b3 | 948 | address = DMA_ERROR_CODE; |
d3086444 JR |
949 | |
950 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
951 | ||
952 | return address; | |
953 | } | |
954 | ||
431b2a20 JR |
955 | /* |
956 | * The address free function. | |
957 | * | |
958 | * called with domain->lock held | |
959 | */ | |
d3086444 JR |
960 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
961 | unsigned long address, | |
962 | unsigned int pages) | |
963 | { | |
384de729 JR |
964 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
965 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 966 | |
384de729 JR |
967 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
968 | ||
47bccd6b JR |
969 | #ifdef CONFIG_IOMMU_STRESS |
970 | if (i < 4) | |
971 | return; | |
972 | #endif | |
80be308d | 973 | |
803b8cb4 | 974 | if (address >= dom->next_address) |
80be308d | 975 | dom->need_flush = true; |
384de729 JR |
976 | |
977 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 978 | |
384de729 JR |
979 | iommu_area_free(range->bitmap, address, pages); |
980 | ||
d3086444 JR |
981 | } |
982 | ||
431b2a20 JR |
983 | /**************************************************************************** |
984 | * | |
985 | * The next functions belong to the domain allocation. A domain is | |
986 | * allocated for every IOMMU as the default domain. If device isolation | |
987 | * is enabled, every device get its own domain. The most important thing | |
988 | * about domains is the page table mapping the DMA address space they | |
989 | * contain. | |
990 | * | |
991 | ****************************************************************************/ | |
992 | ||
ec487d1a JR |
993 | static u16 domain_id_alloc(void) |
994 | { | |
995 | unsigned long flags; | |
996 | int id; | |
997 | ||
998 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
999 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1000 | BUG_ON(id == 0); | |
1001 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1002 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1003 | else | |
1004 | id = 0; | |
1005 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1006 | ||
1007 | return id; | |
1008 | } | |
1009 | ||
a2acfb75 JR |
1010 | static void domain_id_free(int id) |
1011 | { | |
1012 | unsigned long flags; | |
1013 | ||
1014 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1015 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1016 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1017 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1018 | } | |
a2acfb75 | 1019 | |
431b2a20 JR |
1020 | /* |
1021 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1022 | * ranges. | |
1023 | */ | |
ec487d1a JR |
1024 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
1025 | unsigned long start_page, | |
1026 | unsigned int pages) | |
1027 | { | |
384de729 | 1028 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
1029 | |
1030 | if (start_page + pages > last_page) | |
1031 | pages = last_page - start_page; | |
1032 | ||
384de729 JR |
1033 | for (i = start_page; i < start_page + pages; ++i) { |
1034 | int index = i / APERTURE_RANGE_PAGES; | |
1035 | int page = i % APERTURE_RANGE_PAGES; | |
1036 | __set_bit(page, dom->aperture[index]->bitmap); | |
1037 | } | |
ec487d1a JR |
1038 | } |
1039 | ||
86db2e5d | 1040 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1041 | { |
1042 | int i, j; | |
1043 | u64 *p1, *p2, *p3; | |
1044 | ||
86db2e5d | 1045 | p1 = domain->pt_root; |
ec487d1a JR |
1046 | |
1047 | if (!p1) | |
1048 | return; | |
1049 | ||
1050 | for (i = 0; i < 512; ++i) { | |
1051 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1052 | continue; | |
1053 | ||
1054 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1055 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1056 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1057 | continue; | |
1058 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1059 | free_page((unsigned long)p3); | |
1060 | } | |
1061 | ||
1062 | free_page((unsigned long)p2); | |
1063 | } | |
1064 | ||
1065 | free_page((unsigned long)p1); | |
86db2e5d JR |
1066 | |
1067 | domain->pt_root = NULL; | |
ec487d1a JR |
1068 | } |
1069 | ||
431b2a20 JR |
1070 | /* |
1071 | * Free a domain, only used if something went wrong in the | |
1072 | * allocation path and we need to free an already allocated page table | |
1073 | */ | |
ec487d1a JR |
1074 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1075 | { | |
384de729 JR |
1076 | int i; |
1077 | ||
ec487d1a JR |
1078 | if (!dom) |
1079 | return; | |
1080 | ||
86db2e5d | 1081 | free_pagetable(&dom->domain); |
ec487d1a | 1082 | |
384de729 JR |
1083 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1084 | if (!dom->aperture[i]) | |
1085 | continue; | |
1086 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1087 | kfree(dom->aperture[i]); | |
1088 | } | |
ec487d1a JR |
1089 | |
1090 | kfree(dom); | |
1091 | } | |
1092 | ||
431b2a20 JR |
1093 | /* |
1094 | * Allocates a new protection domain usable for the dma_ops functions. | |
1095 | * It also intializes the page table and the address allocator data | |
1096 | * structures required for the dma_ops interface | |
1097 | */ | |
d9cfed92 | 1098 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1099 | { |
1100 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1101 | |
1102 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1103 | if (!dma_dom) | |
1104 | return NULL; | |
1105 | ||
1106 | spin_lock_init(&dma_dom->domain.lock); | |
1107 | ||
1108 | dma_dom->domain.id = domain_id_alloc(); | |
1109 | if (dma_dom->domain.id == 0) | |
1110 | goto free_dma_dom; | |
8f7a017c | 1111 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1112 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1113 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1114 | dma_dom->domain.priv = dma_dom; |
1115 | if (!dma_dom->domain.pt_root) | |
1116 | goto free_dma_dom; | |
ec487d1a | 1117 | |
1c655773 | 1118 | dma_dom->need_flush = false; |
bd60b735 | 1119 | dma_dom->target_dev = 0xffff; |
1c655773 | 1120 | |
00cd122a | 1121 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1122 | goto free_dma_dom; |
ec487d1a | 1123 | |
431b2a20 | 1124 | /* |
ec487d1a JR |
1125 | * mark the first page as allocated so we never return 0 as |
1126 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1127 | */ |
384de729 | 1128 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1129 | dma_dom->next_address = 0; |
ec487d1a | 1130 | |
ec487d1a JR |
1131 | |
1132 | return dma_dom; | |
1133 | ||
1134 | free_dma_dom: | |
1135 | dma_ops_domain_free(dma_dom); | |
1136 | ||
1137 | return NULL; | |
1138 | } | |
1139 | ||
5b28df6f JR |
1140 | /* |
1141 | * little helper function to check whether a given protection domain is a | |
1142 | * dma_ops domain | |
1143 | */ | |
1144 | static bool dma_ops_domain(struct protection_domain *domain) | |
1145 | { | |
1146 | return domain->flags & PD_DMA_OPS_MASK; | |
1147 | } | |
1148 | ||
431b2a20 JR |
1149 | /* |
1150 | * Find out the protection domain structure for a given PCI device. This | |
1151 | * will give us the pointer to the page table root for example. | |
1152 | */ | |
b20ac0d4 JR |
1153 | static struct protection_domain *domain_for_device(u16 devid) |
1154 | { | |
1155 | struct protection_domain *dom; | |
1156 | unsigned long flags; | |
1157 | ||
1158 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1159 | dom = amd_iommu_pd_table[devid]; | |
1160 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1161 | ||
1162 | return dom; | |
1163 | } | |
1164 | ||
407d733e | 1165 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1166 | { |
b20ac0d4 | 1167 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1168 | |
38ddf41b JR |
1169 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1170 | << DEV_ENTRY_MODE_SHIFT; | |
1171 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1172 | |
b20ac0d4 | 1173 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1174 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1175 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1176 | |
1177 | amd_iommu_pd_table[devid] = domain; | |
2b681faf JR |
1178 | } |
1179 | ||
1180 | /* | |
1181 | * If a device is not yet associated with a domain, this function does | |
1182 | * assigns it visible for the hardware | |
1183 | */ | |
1184 | static void __attach_device(struct amd_iommu *iommu, | |
1185 | struct protection_domain *domain, | |
1186 | u16 devid) | |
1187 | { | |
1188 | /* lock domain */ | |
1189 | spin_lock(&domain->lock); | |
1190 | ||
1191 | /* update DTE entry */ | |
1192 | set_dte_entry(devid, domain); | |
eba6ac60 | 1193 | |
c4596114 JR |
1194 | /* Do reference counting */ |
1195 | domain->dev_iommu[iommu->index] += 1; | |
1196 | domain->dev_cnt += 1; | |
eba6ac60 JR |
1197 | |
1198 | /* ready */ | |
1199 | spin_unlock(&domain->lock); | |
0feae533 | 1200 | } |
b20ac0d4 | 1201 | |
407d733e JR |
1202 | /* |
1203 | * If a device is not yet associated with a domain, this function does | |
1204 | * assigns it visible for the hardware | |
1205 | */ | |
0feae533 JR |
1206 | static void attach_device(struct amd_iommu *iommu, |
1207 | struct protection_domain *domain, | |
1208 | u16 devid) | |
1209 | { | |
eba6ac60 JR |
1210 | unsigned long flags; |
1211 | ||
1212 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
0feae533 | 1213 | __attach_device(iommu, domain, devid); |
b20ac0d4 JR |
1214 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1215 | ||
0feae533 JR |
1216 | /* |
1217 | * We might boot into a crash-kernel here. The crashed kernel | |
1218 | * left the caches in the IOMMU dirty. So we have to flush | |
1219 | * here to evict all dirty stuff. | |
1220 | */ | |
b20ac0d4 | 1221 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1222 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1223 | } |
1224 | ||
355bf553 JR |
1225 | /* |
1226 | * Removes a device from a protection domain (unlocked) | |
1227 | */ | |
1228 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1229 | { | |
c4596114 JR |
1230 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
1231 | ||
1232 | BUG_ON(!iommu); | |
355bf553 JR |
1233 | |
1234 | /* lock domain */ | |
1235 | spin_lock(&domain->lock); | |
1236 | ||
1237 | /* remove domain from the lookup table */ | |
1238 | amd_iommu_pd_table[devid] = NULL; | |
1239 | ||
1240 | /* remove entry from the device table seen by the hardware */ | |
1241 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1242 | amd_iommu_dev_table[devid].data[1] = 0; | |
1243 | amd_iommu_dev_table[devid].data[2] = 0; | |
1244 | ||
c5cca146 JR |
1245 | amd_iommu_apply_erratum_63(devid); |
1246 | ||
c4596114 JR |
1247 | /* decrease reference counters */ |
1248 | domain->dev_iommu[iommu->index] -= 1; | |
1249 | domain->dev_cnt -= 1; | |
355bf553 JR |
1250 | |
1251 | /* ready */ | |
1252 | spin_unlock(&domain->lock); | |
21129f78 JR |
1253 | |
1254 | /* | |
1255 | * If we run in passthrough mode the device must be assigned to the | |
1256 | * passthrough domain if it is detached from any other domain | |
1257 | */ | |
1258 | if (iommu_pass_through) { | |
1259 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1260 | __attach_device(iommu, pt_domain, devid); | |
1261 | } | |
355bf553 JR |
1262 | } |
1263 | ||
1264 | /* | |
1265 | * Removes a device from a protection domain (with devtable_lock held) | |
1266 | */ | |
1267 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1268 | { | |
1269 | unsigned long flags; | |
1270 | ||
1271 | /* lock device table */ | |
1272 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1273 | __detach_device(domain, devid); | |
1274 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1275 | } | |
e275a2a0 JR |
1276 | |
1277 | static int device_change_notifier(struct notifier_block *nb, | |
1278 | unsigned long action, void *data) | |
1279 | { | |
1280 | struct device *dev = data; | |
1281 | struct pci_dev *pdev = to_pci_dev(dev); | |
1282 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1283 | struct protection_domain *domain; | |
1284 | struct dma_ops_domain *dma_domain; | |
1285 | struct amd_iommu *iommu; | |
1ac4cbbc | 1286 | unsigned long flags; |
e275a2a0 JR |
1287 | |
1288 | if (devid > amd_iommu_last_bdf) | |
1289 | goto out; | |
1290 | ||
1291 | devid = amd_iommu_alias_table[devid]; | |
1292 | ||
1293 | iommu = amd_iommu_rlookup_table[devid]; | |
1294 | if (iommu == NULL) | |
1295 | goto out; | |
1296 | ||
1297 | domain = domain_for_device(devid); | |
1298 | ||
1299 | if (domain && !dma_ops_domain(domain)) | |
1300 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1301 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1302 | ||
1303 | switch (action) { | |
c1eee67b | 1304 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1305 | if (!domain) |
1306 | goto out; | |
a1ca331c JR |
1307 | if (iommu_pass_through) |
1308 | break; | |
e275a2a0 | 1309 | detach_device(domain, devid); |
1ac4cbbc JR |
1310 | break; |
1311 | case BUS_NOTIFY_ADD_DEVICE: | |
1312 | /* allocate a protection domain if a device is added */ | |
1313 | dma_domain = find_protection_domain(devid); | |
1314 | if (dma_domain) | |
1315 | goto out; | |
d9cfed92 | 1316 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1317 | if (!dma_domain) |
1318 | goto out; | |
1319 | dma_domain->target_dev = devid; | |
1320 | ||
1321 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1322 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1323 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1324 | ||
e275a2a0 JR |
1325 | break; |
1326 | default: | |
1327 | goto out; | |
1328 | } | |
1329 | ||
1330 | iommu_queue_inv_dev_entry(iommu, devid); | |
1331 | iommu_completion_wait(iommu); | |
1332 | ||
1333 | out: | |
1334 | return 0; | |
1335 | } | |
1336 | ||
b25ae679 | 1337 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1338 | .notifier_call = device_change_notifier, |
1339 | }; | |
355bf553 | 1340 | |
431b2a20 JR |
1341 | /***************************************************************************** |
1342 | * | |
1343 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1344 | * | |
1345 | *****************************************************************************/ | |
1346 | ||
dbcc112e JR |
1347 | /* |
1348 | * This function checks if the driver got a valid device from the caller to | |
1349 | * avoid dereferencing invalid pointers. | |
1350 | */ | |
1351 | static bool check_device(struct device *dev) | |
1352 | { | |
1353 | if (!dev || !dev->dma_mask) | |
1354 | return false; | |
1355 | ||
1356 | return true; | |
1357 | } | |
1358 | ||
bd60b735 JR |
1359 | /* |
1360 | * In this function the list of preallocated protection domains is traversed to | |
1361 | * find the domain for a specific device | |
1362 | */ | |
1363 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1364 | { | |
1365 | struct dma_ops_domain *entry, *ret = NULL; | |
1366 | unsigned long flags; | |
1367 | ||
1368 | if (list_empty(&iommu_pd_list)) | |
1369 | return NULL; | |
1370 | ||
1371 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1372 | ||
1373 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1374 | if (entry->target_dev == devid) { | |
1375 | ret = entry; | |
bd60b735 JR |
1376 | break; |
1377 | } | |
1378 | } | |
1379 | ||
1380 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1381 | ||
1382 | return ret; | |
1383 | } | |
1384 | ||
431b2a20 JR |
1385 | /* |
1386 | * In the dma_ops path we only have the struct device. This function | |
1387 | * finds the corresponding IOMMU, the protection domain and the | |
1388 | * requestor id for a given device. | |
1389 | * If the device is not yet associated with a domain this is also done | |
1390 | * in this function. | |
1391 | */ | |
b20ac0d4 JR |
1392 | static int get_device_resources(struct device *dev, |
1393 | struct amd_iommu **iommu, | |
1394 | struct protection_domain **domain, | |
1395 | u16 *bdf) | |
1396 | { | |
1397 | struct dma_ops_domain *dma_dom; | |
1398 | struct pci_dev *pcidev; | |
1399 | u16 _bdf; | |
1400 | ||
dbcc112e JR |
1401 | *iommu = NULL; |
1402 | *domain = NULL; | |
1403 | *bdf = 0xffff; | |
1404 | ||
1405 | if (dev->bus != &pci_bus_type) | |
1406 | return 0; | |
b20ac0d4 JR |
1407 | |
1408 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1409 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1410 | |
431b2a20 | 1411 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1412 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1413 | return 0; |
b20ac0d4 JR |
1414 | |
1415 | *bdf = amd_iommu_alias_table[_bdf]; | |
1416 | ||
1417 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1418 | if (*iommu == NULL) | |
1419 | return 0; | |
b20ac0d4 JR |
1420 | *domain = domain_for_device(*bdf); |
1421 | if (*domain == NULL) { | |
bd60b735 JR |
1422 | dma_dom = find_protection_domain(*bdf); |
1423 | if (!dma_dom) | |
1424 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1425 | *domain = &dma_dom->domain; |
f1179dc0 | 1426 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1427 | DUMP_printk("Using protection domain %d for device %s\n", |
1428 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1429 | } |
1430 | ||
f91ba190 | 1431 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1432 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1433 | |
b20ac0d4 JR |
1434 | return 1; |
1435 | } | |
1436 | ||
04bfdd84 JR |
1437 | static void update_device_table(struct protection_domain *domain) |
1438 | { | |
2b681faf | 1439 | unsigned long flags; |
04bfdd84 JR |
1440 | int i; |
1441 | ||
1442 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1443 | if (amd_iommu_pd_table[i] != domain) | |
1444 | continue; | |
2b681faf | 1445 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1446 | set_dte_entry(i, domain); |
2b681faf | 1447 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1448 | } |
1449 | } | |
1450 | ||
1451 | static void update_domain(struct protection_domain *domain) | |
1452 | { | |
1453 | if (!domain->updated) | |
1454 | return; | |
1455 | ||
1456 | update_device_table(domain); | |
1457 | flush_devices_by_domain(domain); | |
1458 | iommu_flush_domain(domain->id); | |
1459 | ||
1460 | domain->updated = false; | |
1461 | } | |
1462 | ||
8bda3092 | 1463 | /* |
50020fb6 JR |
1464 | * This function is used to add another level to an IO page table. Adding |
1465 | * another level increases the size of the address space by 9 bits to a size up | |
1466 | * to 64 bits. | |
8bda3092 | 1467 | */ |
50020fb6 JR |
1468 | static bool increase_address_space(struct protection_domain *domain, |
1469 | gfp_t gfp) | |
1470 | { | |
1471 | u64 *pte; | |
1472 | ||
1473 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1474 | /* address space already 64 bit large */ | |
1475 | return false; | |
1476 | ||
1477 | pte = (void *)get_zeroed_page(gfp); | |
1478 | if (!pte) | |
1479 | return false; | |
1480 | ||
1481 | *pte = PM_LEVEL_PDE(domain->mode, | |
1482 | virt_to_phys(domain->pt_root)); | |
1483 | domain->pt_root = pte; | |
1484 | domain->mode += 1; | |
1485 | domain->updated = true; | |
1486 | ||
1487 | return true; | |
1488 | } | |
1489 | ||
8bc3e127 | 1490 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
1491 | unsigned long address, |
1492 | int end_lvl, | |
1493 | u64 **pte_page, | |
1494 | gfp_t gfp) | |
8bda3092 JR |
1495 | { |
1496 | u64 *pte, *page; | |
8bc3e127 | 1497 | int level; |
8bda3092 | 1498 | |
8bc3e127 JR |
1499 | while (address > PM_LEVEL_SIZE(domain->mode)) |
1500 | increase_address_space(domain, gfp); | |
8bda3092 | 1501 | |
8bc3e127 JR |
1502 | level = domain->mode - 1; |
1503 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
8bda3092 | 1504 | |
abdc5eb3 | 1505 | while (level > end_lvl) { |
8bc3e127 JR |
1506 | if (!IOMMU_PTE_PRESENT(*pte)) { |
1507 | page = (u64 *)get_zeroed_page(gfp); | |
1508 | if (!page) | |
1509 | return NULL; | |
1510 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1511 | } | |
8bda3092 | 1512 | |
8bc3e127 | 1513 | level -= 1; |
8bda3092 | 1514 | |
8bc3e127 | 1515 | pte = IOMMU_PTE_PAGE(*pte); |
8bda3092 | 1516 | |
abdc5eb3 | 1517 | if (pte_page && level == end_lvl) |
8bc3e127 | 1518 | *pte_page = pte; |
8bda3092 | 1519 | |
8bc3e127 JR |
1520 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
1521 | } | |
8bda3092 JR |
1522 | |
1523 | return pte; | |
1524 | } | |
1525 | ||
1526 | /* | |
1527 | * This function fetches the PTE for a given address in the aperture | |
1528 | */ | |
1529 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1530 | unsigned long address) | |
1531 | { | |
384de729 | 1532 | struct aperture_range *aperture; |
8bda3092 JR |
1533 | u64 *pte, *pte_page; |
1534 | ||
384de729 JR |
1535 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1536 | if (!aperture) | |
1537 | return NULL; | |
1538 | ||
1539 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1540 | if (!pte) { |
abdc5eb3 JR |
1541 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1542 | GFP_ATOMIC); | |
384de729 JR |
1543 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1544 | } else | |
8c8c143c | 1545 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1546 | |
04bfdd84 | 1547 | update_domain(&dom->domain); |
8bda3092 JR |
1548 | |
1549 | return pte; | |
1550 | } | |
1551 | ||
431b2a20 JR |
1552 | /* |
1553 | * This is the generic map function. It maps one 4kb page at paddr to | |
1554 | * the given address in the DMA address space for the domain. | |
1555 | */ | |
cb76c322 JR |
1556 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1557 | struct dma_ops_domain *dom, | |
1558 | unsigned long address, | |
1559 | phys_addr_t paddr, | |
1560 | int direction) | |
1561 | { | |
1562 | u64 *pte, __pte; | |
1563 | ||
1564 | WARN_ON(address > dom->aperture_size); | |
1565 | ||
1566 | paddr &= PAGE_MASK; | |
1567 | ||
8bda3092 | 1568 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1569 | if (!pte) |
8fd524b3 | 1570 | return DMA_ERROR_CODE; |
cb76c322 JR |
1571 | |
1572 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1573 | ||
1574 | if (direction == DMA_TO_DEVICE) | |
1575 | __pte |= IOMMU_PTE_IR; | |
1576 | else if (direction == DMA_FROM_DEVICE) | |
1577 | __pte |= IOMMU_PTE_IW; | |
1578 | else if (direction == DMA_BIDIRECTIONAL) | |
1579 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1580 | ||
1581 | WARN_ON(*pte); | |
1582 | ||
1583 | *pte = __pte; | |
1584 | ||
1585 | return (dma_addr_t)address; | |
1586 | } | |
1587 | ||
431b2a20 JR |
1588 | /* |
1589 | * The generic unmapping function for on page in the DMA address space. | |
1590 | */ | |
cb76c322 JR |
1591 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1592 | struct dma_ops_domain *dom, | |
1593 | unsigned long address) | |
1594 | { | |
384de729 | 1595 | struct aperture_range *aperture; |
cb76c322 JR |
1596 | u64 *pte; |
1597 | ||
1598 | if (address >= dom->aperture_size) | |
1599 | return; | |
1600 | ||
384de729 JR |
1601 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1602 | if (!aperture) | |
1603 | return; | |
1604 | ||
1605 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1606 | if (!pte) | |
1607 | return; | |
cb76c322 | 1608 | |
8c8c143c | 1609 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1610 | |
1611 | WARN_ON(!*pte); | |
1612 | ||
1613 | *pte = 0ULL; | |
1614 | } | |
1615 | ||
431b2a20 JR |
1616 | /* |
1617 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1618 | * contiguous memory region into DMA address space. It is used by all |
1619 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1620 | * Must be called with the domain lock held. |
1621 | */ | |
cb76c322 JR |
1622 | static dma_addr_t __map_single(struct device *dev, |
1623 | struct amd_iommu *iommu, | |
1624 | struct dma_ops_domain *dma_dom, | |
1625 | phys_addr_t paddr, | |
1626 | size_t size, | |
6d4f343f | 1627 | int dir, |
832a90c3 JR |
1628 | bool align, |
1629 | u64 dma_mask) | |
cb76c322 JR |
1630 | { |
1631 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1632 | dma_addr_t address, start, ret; |
cb76c322 | 1633 | unsigned int pages; |
6d4f343f | 1634 | unsigned long align_mask = 0; |
cb76c322 JR |
1635 | int i; |
1636 | ||
e3c449f5 | 1637 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1638 | paddr &= PAGE_MASK; |
1639 | ||
8ecaf8f1 JR |
1640 | INC_STATS_COUNTER(total_map_requests); |
1641 | ||
c1858976 JR |
1642 | if (pages > 1) |
1643 | INC_STATS_COUNTER(cross_page); | |
1644 | ||
6d4f343f JR |
1645 | if (align) |
1646 | align_mask = (1UL << get_order(size)) - 1; | |
1647 | ||
11b83888 | 1648 | retry: |
832a90c3 JR |
1649 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1650 | dma_mask); | |
8fd524b3 | 1651 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1652 | /* |
1653 | * setting next_address here will let the address | |
1654 | * allocator only scan the new allocated range in the | |
1655 | * first run. This is a small optimization. | |
1656 | */ | |
1657 | dma_dom->next_address = dma_dom->aperture_size; | |
1658 | ||
1659 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1660 | goto out; | |
1661 | ||
1662 | /* | |
1663 | * aperture was sucessfully enlarged by 128 MB, try | |
1664 | * allocation again | |
1665 | */ | |
1666 | goto retry; | |
1667 | } | |
cb76c322 JR |
1668 | |
1669 | start = address; | |
1670 | for (i = 0; i < pages; ++i) { | |
53812c11 | 1671 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
8fd524b3 | 1672 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1673 | goto out_unmap; |
1674 | ||
cb76c322 JR |
1675 | paddr += PAGE_SIZE; |
1676 | start += PAGE_SIZE; | |
1677 | } | |
1678 | address += offset; | |
1679 | ||
5774f7c5 JR |
1680 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1681 | ||
afa9fdc2 | 1682 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1683 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1684 | dma_dom->need_flush = false; | |
1685 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1686 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1687 | ||
cb76c322 JR |
1688 | out: |
1689 | return address; | |
53812c11 JR |
1690 | |
1691 | out_unmap: | |
1692 | ||
1693 | for (--i; i >= 0; --i) { | |
1694 | start -= PAGE_SIZE; | |
1695 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1696 | } | |
1697 | ||
1698 | dma_ops_free_addresses(dma_dom, address, pages); | |
1699 | ||
8fd524b3 | 1700 | return DMA_ERROR_CODE; |
cb76c322 JR |
1701 | } |
1702 | ||
431b2a20 JR |
1703 | /* |
1704 | * Does the reverse of the __map_single function. Must be called with | |
1705 | * the domain lock held too | |
1706 | */ | |
cb76c322 JR |
1707 | static void __unmap_single(struct amd_iommu *iommu, |
1708 | struct dma_ops_domain *dma_dom, | |
1709 | dma_addr_t dma_addr, | |
1710 | size_t size, | |
1711 | int dir) | |
1712 | { | |
1713 | dma_addr_t i, start; | |
1714 | unsigned int pages; | |
1715 | ||
8fd524b3 | 1716 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1717 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1718 | return; |
1719 | ||
e3c449f5 | 1720 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1721 | dma_addr &= PAGE_MASK; |
1722 | start = dma_addr; | |
1723 | ||
1724 | for (i = 0; i < pages; ++i) { | |
1725 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1726 | start += PAGE_SIZE; | |
1727 | } | |
1728 | ||
5774f7c5 JR |
1729 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1730 | ||
cb76c322 | 1731 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1732 | |
80be308d | 1733 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1734 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1735 | dma_dom->need_flush = false; |
1736 | } | |
cb76c322 JR |
1737 | } |
1738 | ||
431b2a20 JR |
1739 | /* |
1740 | * The exported map_single function for dma_ops. | |
1741 | */ | |
51491367 FT |
1742 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1743 | unsigned long offset, size_t size, | |
1744 | enum dma_data_direction dir, | |
1745 | struct dma_attrs *attrs) | |
4da70b9e JR |
1746 | { |
1747 | unsigned long flags; | |
1748 | struct amd_iommu *iommu; | |
1749 | struct protection_domain *domain; | |
1750 | u16 devid; | |
1751 | dma_addr_t addr; | |
832a90c3 | 1752 | u64 dma_mask; |
51491367 | 1753 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1754 | |
0f2a86f2 JR |
1755 | INC_STATS_COUNTER(cnt_map_single); |
1756 | ||
dbcc112e | 1757 | if (!check_device(dev)) |
8fd524b3 | 1758 | return DMA_ERROR_CODE; |
dbcc112e | 1759 | |
832a90c3 | 1760 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1761 | |
1762 | get_device_resources(dev, &iommu, &domain, &devid); | |
1763 | ||
1764 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1765 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1766 | return (dma_addr_t)paddr; |
1767 | ||
5b28df6f | 1768 | if (!dma_ops_domain(domain)) |
8fd524b3 | 1769 | return DMA_ERROR_CODE; |
5b28df6f | 1770 | |
4da70b9e | 1771 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1772 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1773 | dma_mask); | |
8fd524b3 | 1774 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1775 | goto out; |
1776 | ||
0518a3a4 | 1777 | iommu_flush_complete(domain); |
4da70b9e JR |
1778 | |
1779 | out: | |
1780 | spin_unlock_irqrestore(&domain->lock, flags); | |
1781 | ||
1782 | return addr; | |
1783 | } | |
1784 | ||
431b2a20 JR |
1785 | /* |
1786 | * The exported unmap_single function for dma_ops. | |
1787 | */ | |
51491367 FT |
1788 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1789 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1790 | { |
1791 | unsigned long flags; | |
1792 | struct amd_iommu *iommu; | |
1793 | struct protection_domain *domain; | |
1794 | u16 devid; | |
1795 | ||
146a6917 JR |
1796 | INC_STATS_COUNTER(cnt_unmap_single); |
1797 | ||
dbcc112e JR |
1798 | if (!check_device(dev) || |
1799 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1800 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1801 | return; |
1802 | ||
5b28df6f JR |
1803 | if (!dma_ops_domain(domain)) |
1804 | return; | |
1805 | ||
4da70b9e JR |
1806 | spin_lock_irqsave(&domain->lock, flags); |
1807 | ||
1808 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1809 | ||
0518a3a4 | 1810 | iommu_flush_complete(domain); |
4da70b9e JR |
1811 | |
1812 | spin_unlock_irqrestore(&domain->lock, flags); | |
1813 | } | |
1814 | ||
431b2a20 JR |
1815 | /* |
1816 | * This is a special map_sg function which is used if we should map a | |
1817 | * device which is not handled by an AMD IOMMU in the system. | |
1818 | */ | |
65b050ad JR |
1819 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1820 | int nelems, int dir) | |
1821 | { | |
1822 | struct scatterlist *s; | |
1823 | int i; | |
1824 | ||
1825 | for_each_sg(sglist, s, nelems, i) { | |
1826 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1827 | s->dma_length = s->length; | |
1828 | } | |
1829 | ||
1830 | return nelems; | |
1831 | } | |
1832 | ||
431b2a20 JR |
1833 | /* |
1834 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1835 | * lists). | |
1836 | */ | |
65b050ad | 1837 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1838 | int nelems, enum dma_data_direction dir, |
1839 | struct dma_attrs *attrs) | |
65b050ad JR |
1840 | { |
1841 | unsigned long flags; | |
1842 | struct amd_iommu *iommu; | |
1843 | struct protection_domain *domain; | |
1844 | u16 devid; | |
1845 | int i; | |
1846 | struct scatterlist *s; | |
1847 | phys_addr_t paddr; | |
1848 | int mapped_elems = 0; | |
832a90c3 | 1849 | u64 dma_mask; |
65b050ad | 1850 | |
d03f067a JR |
1851 | INC_STATS_COUNTER(cnt_map_sg); |
1852 | ||
dbcc112e JR |
1853 | if (!check_device(dev)) |
1854 | return 0; | |
1855 | ||
832a90c3 | 1856 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1857 | |
1858 | get_device_resources(dev, &iommu, &domain, &devid); | |
1859 | ||
1860 | if (!iommu || !domain) | |
1861 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1862 | ||
5b28df6f JR |
1863 | if (!dma_ops_domain(domain)) |
1864 | return 0; | |
1865 | ||
65b050ad JR |
1866 | spin_lock_irqsave(&domain->lock, flags); |
1867 | ||
1868 | for_each_sg(sglist, s, nelems, i) { | |
1869 | paddr = sg_phys(s); | |
1870 | ||
1871 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1872 | paddr, s->length, dir, false, |
1873 | dma_mask); | |
65b050ad JR |
1874 | |
1875 | if (s->dma_address) { | |
1876 | s->dma_length = s->length; | |
1877 | mapped_elems++; | |
1878 | } else | |
1879 | goto unmap; | |
65b050ad JR |
1880 | } |
1881 | ||
0518a3a4 | 1882 | iommu_flush_complete(domain); |
65b050ad JR |
1883 | |
1884 | out: | |
1885 | spin_unlock_irqrestore(&domain->lock, flags); | |
1886 | ||
1887 | return mapped_elems; | |
1888 | unmap: | |
1889 | for_each_sg(sglist, s, mapped_elems, i) { | |
1890 | if (s->dma_address) | |
1891 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1892 | s->dma_length, dir); | |
1893 | s->dma_address = s->dma_length = 0; | |
1894 | } | |
1895 | ||
1896 | mapped_elems = 0; | |
1897 | ||
1898 | goto out; | |
1899 | } | |
1900 | ||
431b2a20 JR |
1901 | /* |
1902 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1903 | * lists). | |
1904 | */ | |
65b050ad | 1905 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1906 | int nelems, enum dma_data_direction dir, |
1907 | struct dma_attrs *attrs) | |
65b050ad JR |
1908 | { |
1909 | unsigned long flags; | |
1910 | struct amd_iommu *iommu; | |
1911 | struct protection_domain *domain; | |
1912 | struct scatterlist *s; | |
1913 | u16 devid; | |
1914 | int i; | |
1915 | ||
55877a6b JR |
1916 | INC_STATS_COUNTER(cnt_unmap_sg); |
1917 | ||
dbcc112e JR |
1918 | if (!check_device(dev) || |
1919 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1920 | return; |
1921 | ||
5b28df6f JR |
1922 | if (!dma_ops_domain(domain)) |
1923 | return; | |
1924 | ||
65b050ad JR |
1925 | spin_lock_irqsave(&domain->lock, flags); |
1926 | ||
1927 | for_each_sg(sglist, s, nelems, i) { | |
1928 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1929 | s->dma_length, dir); | |
65b050ad JR |
1930 | s->dma_address = s->dma_length = 0; |
1931 | } | |
1932 | ||
0518a3a4 | 1933 | iommu_flush_complete(domain); |
65b050ad JR |
1934 | |
1935 | spin_unlock_irqrestore(&domain->lock, flags); | |
1936 | } | |
1937 | ||
431b2a20 JR |
1938 | /* |
1939 | * The exported alloc_coherent function for dma_ops. | |
1940 | */ | |
5d8b53cf JR |
1941 | static void *alloc_coherent(struct device *dev, size_t size, |
1942 | dma_addr_t *dma_addr, gfp_t flag) | |
1943 | { | |
1944 | unsigned long flags; | |
1945 | void *virt_addr; | |
1946 | struct amd_iommu *iommu; | |
1947 | struct protection_domain *domain; | |
1948 | u16 devid; | |
1949 | phys_addr_t paddr; | |
832a90c3 | 1950 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1951 | |
c8f0fb36 JR |
1952 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1953 | ||
dbcc112e JR |
1954 | if (!check_device(dev)) |
1955 | return NULL; | |
5d8b53cf | 1956 | |
13d9fead FT |
1957 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1958 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1959 | |
c97ac535 | 1960 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1961 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1962 | if (!virt_addr) | |
b25ae679 | 1963 | return NULL; |
5d8b53cf | 1964 | |
5d8b53cf JR |
1965 | paddr = virt_to_phys(virt_addr); |
1966 | ||
5d8b53cf JR |
1967 | if (!iommu || !domain) { |
1968 | *dma_addr = (dma_addr_t)paddr; | |
1969 | return virt_addr; | |
1970 | } | |
1971 | ||
5b28df6f JR |
1972 | if (!dma_ops_domain(domain)) |
1973 | goto out_free; | |
1974 | ||
832a90c3 JR |
1975 | if (!dma_mask) |
1976 | dma_mask = *dev->dma_mask; | |
1977 | ||
5d8b53cf JR |
1978 | spin_lock_irqsave(&domain->lock, flags); |
1979 | ||
1980 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1981 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1982 | |
8fd524b3 | 1983 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 1984 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 1985 | goto out_free; |
367d04c4 | 1986 | } |
5d8b53cf | 1987 | |
0518a3a4 | 1988 | iommu_flush_complete(domain); |
5d8b53cf | 1989 | |
5d8b53cf JR |
1990 | spin_unlock_irqrestore(&domain->lock, flags); |
1991 | ||
1992 | return virt_addr; | |
5b28df6f JR |
1993 | |
1994 | out_free: | |
1995 | ||
1996 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1997 | ||
1998 | return NULL; | |
5d8b53cf JR |
1999 | } |
2000 | ||
431b2a20 JR |
2001 | /* |
2002 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2003 | */ |
5d8b53cf JR |
2004 | static void free_coherent(struct device *dev, size_t size, |
2005 | void *virt_addr, dma_addr_t dma_addr) | |
2006 | { | |
2007 | unsigned long flags; | |
2008 | struct amd_iommu *iommu; | |
2009 | struct protection_domain *domain; | |
2010 | u16 devid; | |
2011 | ||
5d31ee7e JR |
2012 | INC_STATS_COUNTER(cnt_free_coherent); |
2013 | ||
dbcc112e JR |
2014 | if (!check_device(dev)) |
2015 | return; | |
2016 | ||
5d8b53cf JR |
2017 | get_device_resources(dev, &iommu, &domain, &devid); |
2018 | ||
2019 | if (!iommu || !domain) | |
2020 | goto free_mem; | |
2021 | ||
5b28df6f JR |
2022 | if (!dma_ops_domain(domain)) |
2023 | goto free_mem; | |
2024 | ||
5d8b53cf JR |
2025 | spin_lock_irqsave(&domain->lock, flags); |
2026 | ||
2027 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2028 | |
0518a3a4 | 2029 | iommu_flush_complete(domain); |
5d8b53cf JR |
2030 | |
2031 | spin_unlock_irqrestore(&domain->lock, flags); | |
2032 | ||
2033 | free_mem: | |
2034 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2035 | } | |
2036 | ||
b39ba6ad JR |
2037 | /* |
2038 | * This function is called by the DMA layer to find out if we can handle a | |
2039 | * particular device. It is part of the dma_ops. | |
2040 | */ | |
2041 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2042 | { | |
2043 | u16 bdf; | |
2044 | struct pci_dev *pcidev; | |
2045 | ||
2046 | /* No device or no PCI device */ | |
2047 | if (!dev || dev->bus != &pci_bus_type) | |
2048 | return 0; | |
2049 | ||
2050 | pcidev = to_pci_dev(dev); | |
2051 | ||
2052 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
2053 | ||
2054 | /* Out of our scope? */ | |
2055 | if (bdf > amd_iommu_last_bdf) | |
2056 | return 0; | |
2057 | ||
2058 | return 1; | |
2059 | } | |
2060 | ||
c432f3df | 2061 | /* |
431b2a20 JR |
2062 | * The function for pre-allocating protection domains. |
2063 | * | |
c432f3df JR |
2064 | * If the driver core informs the DMA layer if a driver grabs a device |
2065 | * we don't need to preallocate the protection domains anymore. | |
2066 | * For now we have to. | |
2067 | */ | |
0e93dd88 | 2068 | static void prealloc_protection_domains(void) |
c432f3df JR |
2069 | { |
2070 | struct pci_dev *dev = NULL; | |
2071 | struct dma_ops_domain *dma_dom; | |
2072 | struct amd_iommu *iommu; | |
be831297 | 2073 | u16 devid, __devid; |
c432f3df JR |
2074 | |
2075 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
be831297 | 2076 | __devid = devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 2077 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
2078 | continue; |
2079 | devid = amd_iommu_alias_table[devid]; | |
2080 | if (domain_for_device(devid)) | |
2081 | continue; | |
2082 | iommu = amd_iommu_rlookup_table[devid]; | |
2083 | if (!iommu) | |
2084 | continue; | |
d9cfed92 | 2085 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
2086 | if (!dma_dom) |
2087 | continue; | |
2088 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2089 | dma_dom->target_dev = devid; |
2090 | ||
be831297 JR |
2091 | attach_device(iommu, &dma_dom->domain, devid); |
2092 | if (__devid != devid) | |
2093 | attach_device(iommu, &dma_dom->domain, __devid); | |
2094 | ||
bd60b735 | 2095 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2096 | } |
2097 | } | |
2098 | ||
160c1d8e | 2099 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2100 | .alloc_coherent = alloc_coherent, |
2101 | .free_coherent = free_coherent, | |
51491367 FT |
2102 | .map_page = map_page, |
2103 | .unmap_page = unmap_page, | |
6631ee9d JR |
2104 | .map_sg = map_sg, |
2105 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2106 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2107 | }; |
2108 | ||
431b2a20 JR |
2109 | /* |
2110 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2111 | */ | |
6631ee9d JR |
2112 | int __init amd_iommu_init_dma_ops(void) |
2113 | { | |
2114 | struct amd_iommu *iommu; | |
6631ee9d JR |
2115 | int ret; |
2116 | ||
431b2a20 JR |
2117 | /* |
2118 | * first allocate a default protection domain for every IOMMU we | |
2119 | * found in the system. Devices not assigned to any other | |
2120 | * protection domain will be assigned to the default one. | |
2121 | */ | |
3bd22172 | 2122 | for_each_iommu(iommu) { |
d9cfed92 | 2123 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
2124 | if (iommu->default_dom == NULL) |
2125 | return -ENOMEM; | |
e2dc14a2 | 2126 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2127 | ret = iommu_init_unity_mappings(iommu); |
2128 | if (ret) | |
2129 | goto free_domains; | |
2130 | } | |
2131 | ||
431b2a20 JR |
2132 | /* |
2133 | * If device isolation is enabled, pre-allocate the protection | |
2134 | * domains for each device. | |
2135 | */ | |
6631ee9d JR |
2136 | if (amd_iommu_isolate) |
2137 | prealloc_protection_domains(); | |
2138 | ||
2139 | iommu_detected = 1; | |
75f1cdf1 | 2140 | swiotlb = 0; |
92af4e29 | 2141 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2142 | gart_iommu_aperture_disabled = 1; |
2143 | gart_iommu_aperture = 0; | |
92af4e29 | 2144 | #endif |
6631ee9d | 2145 | |
431b2a20 | 2146 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2147 | dma_ops = &amd_iommu_dma_ops; |
2148 | ||
26961efe | 2149 | register_iommu(&amd_iommu_ops); |
26961efe | 2150 | |
e275a2a0 JR |
2151 | bus_register_notifier(&pci_bus_type, &device_nb); |
2152 | ||
7f26508b JR |
2153 | amd_iommu_stats_init(); |
2154 | ||
6631ee9d JR |
2155 | return 0; |
2156 | ||
2157 | free_domains: | |
2158 | ||
3bd22172 | 2159 | for_each_iommu(iommu) { |
6631ee9d JR |
2160 | if (iommu->default_dom) |
2161 | dma_ops_domain_free(iommu->default_dom); | |
2162 | } | |
2163 | ||
2164 | return ret; | |
2165 | } | |
6d98cd80 JR |
2166 | |
2167 | /***************************************************************************** | |
2168 | * | |
2169 | * The following functions belong to the exported interface of AMD IOMMU | |
2170 | * | |
2171 | * This interface allows access to lower level functions of the IOMMU | |
2172 | * like protection domain handling and assignement of devices to domains | |
2173 | * which is not possible with the dma_ops interface. | |
2174 | * | |
2175 | *****************************************************************************/ | |
2176 | ||
6d98cd80 JR |
2177 | static void cleanup_domain(struct protection_domain *domain) |
2178 | { | |
2179 | unsigned long flags; | |
2180 | u16 devid; | |
2181 | ||
2182 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2183 | ||
2184 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2185 | if (amd_iommu_pd_table[devid] == domain) | |
2186 | __detach_device(domain, devid); | |
2187 | ||
2188 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2189 | } | |
2190 | ||
2650815f JR |
2191 | static void protection_domain_free(struct protection_domain *domain) |
2192 | { | |
2193 | if (!domain) | |
2194 | return; | |
2195 | ||
2196 | if (domain->id) | |
2197 | domain_id_free(domain->id); | |
2198 | ||
2199 | kfree(domain); | |
2200 | } | |
2201 | ||
2202 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2203 | { |
2204 | struct protection_domain *domain; | |
2205 | ||
2206 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2207 | if (!domain) | |
2650815f | 2208 | return NULL; |
c156e347 JR |
2209 | |
2210 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2211 | domain->id = domain_id_alloc(); |
2212 | if (!domain->id) | |
2650815f JR |
2213 | goto out_err; |
2214 | ||
2215 | return domain; | |
2216 | ||
2217 | out_err: | |
2218 | kfree(domain); | |
2219 | ||
2220 | return NULL; | |
2221 | } | |
2222 | ||
2223 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2224 | { | |
2225 | struct protection_domain *domain; | |
2226 | ||
2227 | domain = protection_domain_alloc(); | |
2228 | if (!domain) | |
c156e347 | 2229 | goto out_free; |
2650815f JR |
2230 | |
2231 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2232 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2233 | if (!domain->pt_root) | |
2234 | goto out_free; | |
2235 | ||
2236 | dom->priv = domain; | |
2237 | ||
2238 | return 0; | |
2239 | ||
2240 | out_free: | |
2650815f | 2241 | protection_domain_free(domain); |
c156e347 JR |
2242 | |
2243 | return -ENOMEM; | |
2244 | } | |
2245 | ||
98383fc3 JR |
2246 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2247 | { | |
2248 | struct protection_domain *domain = dom->priv; | |
2249 | ||
2250 | if (!domain) | |
2251 | return; | |
2252 | ||
2253 | if (domain->dev_cnt > 0) | |
2254 | cleanup_domain(domain); | |
2255 | ||
2256 | BUG_ON(domain->dev_cnt != 0); | |
2257 | ||
2258 | free_pagetable(domain); | |
2259 | ||
2260 | domain_id_free(domain->id); | |
2261 | ||
2262 | kfree(domain); | |
2263 | ||
2264 | dom->priv = NULL; | |
2265 | } | |
2266 | ||
684f2888 JR |
2267 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2268 | struct device *dev) | |
2269 | { | |
2270 | struct protection_domain *domain = dom->priv; | |
2271 | struct amd_iommu *iommu; | |
2272 | struct pci_dev *pdev; | |
2273 | u16 devid; | |
2274 | ||
2275 | if (dev->bus != &pci_bus_type) | |
2276 | return; | |
2277 | ||
2278 | pdev = to_pci_dev(dev); | |
2279 | ||
2280 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2281 | ||
2282 | if (devid > 0) | |
2283 | detach_device(domain, devid); | |
2284 | ||
2285 | iommu = amd_iommu_rlookup_table[devid]; | |
2286 | if (!iommu) | |
2287 | return; | |
2288 | ||
2289 | iommu_queue_inv_dev_entry(iommu, devid); | |
2290 | iommu_completion_wait(iommu); | |
2291 | } | |
2292 | ||
01106066 JR |
2293 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2294 | struct device *dev) | |
2295 | { | |
2296 | struct protection_domain *domain = dom->priv; | |
2297 | struct protection_domain *old_domain; | |
2298 | struct amd_iommu *iommu; | |
2299 | struct pci_dev *pdev; | |
2300 | u16 devid; | |
2301 | ||
2302 | if (dev->bus != &pci_bus_type) | |
2303 | return -EINVAL; | |
2304 | ||
2305 | pdev = to_pci_dev(dev); | |
2306 | ||
2307 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2308 | ||
2309 | if (devid >= amd_iommu_last_bdf || | |
2310 | devid != amd_iommu_alias_table[devid]) | |
2311 | return -EINVAL; | |
2312 | ||
2313 | iommu = amd_iommu_rlookup_table[devid]; | |
2314 | if (!iommu) | |
2315 | return -EINVAL; | |
2316 | ||
2317 | old_domain = domain_for_device(devid); | |
2318 | if (old_domain) | |
71ff3bca | 2319 | detach_device(old_domain, devid); |
01106066 JR |
2320 | |
2321 | attach_device(iommu, domain, devid); | |
2322 | ||
2323 | iommu_completion_wait(iommu); | |
2324 | ||
2325 | return 0; | |
2326 | } | |
2327 | ||
c6229ca6 JR |
2328 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2329 | unsigned long iova, phys_addr_t paddr, | |
2330 | size_t size, int iommu_prot) | |
2331 | { | |
2332 | struct protection_domain *domain = dom->priv; | |
2333 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2334 | int prot = 0; | |
2335 | int ret; | |
2336 | ||
2337 | if (iommu_prot & IOMMU_READ) | |
2338 | prot |= IOMMU_PROT_IR; | |
2339 | if (iommu_prot & IOMMU_WRITE) | |
2340 | prot |= IOMMU_PROT_IW; | |
2341 | ||
2342 | iova &= PAGE_MASK; | |
2343 | paddr &= PAGE_MASK; | |
2344 | ||
2345 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2346 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2347 | if (ret) |
2348 | return ret; | |
2349 | ||
2350 | iova += PAGE_SIZE; | |
2351 | paddr += PAGE_SIZE; | |
2352 | } | |
2353 | ||
2354 | return 0; | |
2355 | } | |
2356 | ||
eb74ff6c JR |
2357 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2358 | unsigned long iova, size_t size) | |
2359 | { | |
2360 | ||
2361 | struct protection_domain *domain = dom->priv; | |
2362 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2363 | ||
2364 | iova &= PAGE_MASK; | |
2365 | ||
2366 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2367 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2368 | iova += PAGE_SIZE; |
2369 | } | |
2370 | ||
2371 | iommu_flush_domain(domain->id); | |
2372 | } | |
2373 | ||
645c4c8d JR |
2374 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2375 | unsigned long iova) | |
2376 | { | |
2377 | struct protection_domain *domain = dom->priv; | |
2378 | unsigned long offset = iova & ~PAGE_MASK; | |
2379 | phys_addr_t paddr; | |
2380 | u64 *pte; | |
2381 | ||
a6b256b4 | 2382 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2383 | |
a6d41a40 | 2384 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2385 | return 0; |
2386 | ||
2387 | paddr = *pte & IOMMU_PAGE_MASK; | |
2388 | paddr |= offset; | |
2389 | ||
2390 | return paddr; | |
2391 | } | |
2392 | ||
dbb9fd86 SY |
2393 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2394 | unsigned long cap) | |
2395 | { | |
2396 | return 0; | |
2397 | } | |
2398 | ||
26961efe JR |
2399 | static struct iommu_ops amd_iommu_ops = { |
2400 | .domain_init = amd_iommu_domain_init, | |
2401 | .domain_destroy = amd_iommu_domain_destroy, | |
2402 | .attach_dev = amd_iommu_attach_device, | |
2403 | .detach_dev = amd_iommu_detach_device, | |
2404 | .map = amd_iommu_map_range, | |
2405 | .unmap = amd_iommu_unmap_range, | |
2406 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2407 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2408 | }; |
2409 | ||
0feae533 JR |
2410 | /***************************************************************************** |
2411 | * | |
2412 | * The next functions do a basic initialization of IOMMU for pass through | |
2413 | * mode | |
2414 | * | |
2415 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2416 | * DMA-API translation. | |
2417 | * | |
2418 | *****************************************************************************/ | |
2419 | ||
2420 | int __init amd_iommu_init_passthrough(void) | |
2421 | { | |
2422 | struct pci_dev *dev = NULL; | |
2423 | u16 devid, devid2; | |
2424 | ||
2425 | /* allocate passthroug domain */ | |
2426 | pt_domain = protection_domain_alloc(); | |
2427 | if (!pt_domain) | |
2428 | return -ENOMEM; | |
2429 | ||
2430 | pt_domain->mode |= PAGE_MODE_NONE; | |
2431 | ||
2432 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2433 | struct amd_iommu *iommu; | |
2434 | ||
2435 | devid = calc_devid(dev->bus->number, dev->devfn); | |
2436 | if (devid > amd_iommu_last_bdf) | |
2437 | continue; | |
2438 | ||
2439 | devid2 = amd_iommu_alias_table[devid]; | |
2440 | ||
2441 | iommu = amd_iommu_rlookup_table[devid2]; | |
2442 | if (!iommu) | |
2443 | continue; | |
2444 | ||
2445 | __attach_device(iommu, pt_domain, devid); | |
2446 | __attach_device(iommu, pt_domain, devid2); | |
2447 | } | |
2448 | ||
2449 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2450 | ||
2451 | return 0; | |
2452 | } |