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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
b6c02715 | 30 | #include <asm/proto.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
27c2127a | 33 | #include <asm/dma.h> |
6a9401a7 | 34 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 35 | #include <asm/amd_iommu_types.h> |
c6da992e | 36 | #include <asm/amd_iommu.h> |
b6c02715 JR |
37 | |
38 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
39 | ||
815b33fd | 40 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 41 | |
b6c02715 JR |
42 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
43 | ||
bd60b735 JR |
44 | /* A list of preallocated protection domains */ |
45 | static LIST_HEAD(iommu_pd_list); | |
46 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
47 | ||
0feae533 JR |
48 | /* |
49 | * Domain for untranslated devices - only allocated | |
50 | * if iommu=pt passed on kernel cmd line. | |
51 | */ | |
52 | static struct protection_domain *pt_domain; | |
53 | ||
26961efe | 54 | static struct iommu_ops amd_iommu_ops; |
26961efe | 55 | |
431b2a20 JR |
56 | /* |
57 | * general struct to manage commands send to an IOMMU | |
58 | */ | |
d6449536 | 59 | struct iommu_cmd { |
b6c02715 JR |
60 | u32 data[4]; |
61 | }; | |
62 | ||
04bfdd84 | 63 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 64 | |
15898bbc JR |
65 | /**************************************************************************** |
66 | * | |
67 | * Helper functions | |
68 | * | |
69 | ****************************************************************************/ | |
70 | ||
71 | static inline u16 get_device_id(struct device *dev) | |
72 | { | |
73 | struct pci_dev *pdev = to_pci_dev(dev); | |
74 | ||
75 | return calc_devid(pdev->bus->number, pdev->devfn); | |
76 | } | |
77 | ||
657cbb6b JR |
78 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
79 | { | |
80 | return dev->archdata.iommu; | |
81 | } | |
82 | ||
71c70984 JR |
83 | /* |
84 | * In this function the list of preallocated protection domains is traversed to | |
85 | * find the domain for a specific device | |
86 | */ | |
87 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
88 | { | |
89 | struct dma_ops_domain *entry, *ret = NULL; | |
90 | unsigned long flags; | |
91 | u16 alias = amd_iommu_alias_table[devid]; | |
92 | ||
93 | if (list_empty(&iommu_pd_list)) | |
94 | return NULL; | |
95 | ||
96 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
97 | ||
98 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
99 | if (entry->target_dev == devid || | |
100 | entry->target_dev == alias) { | |
101 | ret = entry; | |
102 | break; | |
103 | } | |
104 | } | |
105 | ||
106 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
107 | ||
108 | return ret; | |
109 | } | |
110 | ||
98fc5a69 JR |
111 | /* |
112 | * This function checks if the driver got a valid device from the caller to | |
113 | * avoid dereferencing invalid pointers. | |
114 | */ | |
115 | static bool check_device(struct device *dev) | |
116 | { | |
117 | u16 devid; | |
118 | ||
119 | if (!dev || !dev->dma_mask) | |
120 | return false; | |
121 | ||
122 | /* No device or no PCI device */ | |
339d3261 | 123 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
124 | return false; |
125 | ||
126 | devid = get_device_id(dev); | |
127 | ||
128 | /* Out of our scope? */ | |
129 | if (devid > amd_iommu_last_bdf) | |
130 | return false; | |
131 | ||
132 | if (amd_iommu_rlookup_table[devid] == NULL) | |
133 | return false; | |
134 | ||
135 | return true; | |
136 | } | |
137 | ||
657cbb6b JR |
138 | static int iommu_init_device(struct device *dev) |
139 | { | |
140 | struct iommu_dev_data *dev_data; | |
141 | struct pci_dev *pdev; | |
142 | u16 devid, alias; | |
143 | ||
144 | if (dev->archdata.iommu) | |
145 | return 0; | |
146 | ||
147 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
148 | if (!dev_data) | |
149 | return -ENOMEM; | |
150 | ||
b00d3bcf JR |
151 | dev_data->dev = dev; |
152 | ||
657cbb6b JR |
153 | devid = get_device_id(dev); |
154 | alias = amd_iommu_alias_table[devid]; | |
155 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
156 | if (pdev) | |
157 | dev_data->alias = &pdev->dev; | |
158 | ||
24100055 JR |
159 | atomic_set(&dev_data->bind, 0); |
160 | ||
657cbb6b JR |
161 | dev->archdata.iommu = dev_data; |
162 | ||
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static void iommu_uninit_device(struct device *dev) | |
168 | { | |
169 | kfree(dev->archdata.iommu); | |
170 | } | |
b7cc9554 JR |
171 | |
172 | void __init amd_iommu_uninit_devices(void) | |
173 | { | |
174 | struct pci_dev *pdev = NULL; | |
175 | ||
176 | for_each_pci_dev(pdev) { | |
177 | ||
178 | if (!check_device(&pdev->dev)) | |
179 | continue; | |
180 | ||
181 | iommu_uninit_device(&pdev->dev); | |
182 | } | |
183 | } | |
184 | ||
185 | int __init amd_iommu_init_devices(void) | |
186 | { | |
187 | struct pci_dev *pdev = NULL; | |
188 | int ret = 0; | |
189 | ||
190 | for_each_pci_dev(pdev) { | |
191 | ||
192 | if (!check_device(&pdev->dev)) | |
193 | continue; | |
194 | ||
195 | ret = iommu_init_device(&pdev->dev); | |
196 | if (ret) | |
197 | goto out_free; | |
198 | } | |
199 | ||
200 | return 0; | |
201 | ||
202 | out_free: | |
203 | ||
204 | amd_iommu_uninit_devices(); | |
205 | ||
206 | return ret; | |
207 | } | |
7f26508b JR |
208 | #ifdef CONFIG_AMD_IOMMU_STATS |
209 | ||
210 | /* | |
211 | * Initialization code for statistics collection | |
212 | */ | |
213 | ||
da49f6df | 214 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 215 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 216 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 217 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 218 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 219 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 220 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 221 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 222 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 223 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 224 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 225 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 226 | |
7f26508b | 227 | static struct dentry *stats_dir; |
7f26508b JR |
228 | static struct dentry *de_fflush; |
229 | ||
230 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
231 | { | |
232 | if (stats_dir == NULL) | |
233 | return; | |
234 | ||
235 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
236 | &cnt->value); | |
237 | } | |
238 | ||
239 | static void amd_iommu_stats_init(void) | |
240 | { | |
241 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
242 | if (stats_dir == NULL) | |
243 | return; | |
244 | ||
7f26508b JR |
245 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
246 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
247 | |
248 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 249 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 250 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 251 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 252 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 253 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 254 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 255 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 256 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 257 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 258 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 259 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
260 | } |
261 | ||
262 | #endif | |
263 | ||
a80dc3e0 JR |
264 | /**************************************************************************** |
265 | * | |
266 | * Interrupt handling functions | |
267 | * | |
268 | ****************************************************************************/ | |
269 | ||
e3e59876 JR |
270 | static void dump_dte_entry(u16 devid) |
271 | { | |
272 | int i; | |
273 | ||
274 | for (i = 0; i < 8; ++i) | |
275 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
276 | amd_iommu_dev_table[devid].data[i]); | |
277 | } | |
278 | ||
945b4ac4 JR |
279 | static void dump_command(unsigned long phys_addr) |
280 | { | |
281 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
282 | int i; | |
283 | ||
284 | for (i = 0; i < 4; ++i) | |
285 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
286 | } | |
287 | ||
a345b23b | 288 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
289 | { |
290 | u32 *event = __evt; | |
291 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
292 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
293 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
294 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
295 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
296 | ||
4c6f40d4 | 297 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
298 | |
299 | switch (type) { | |
300 | case EVENT_TYPE_ILL_DEV: | |
301 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
302 | "address=0x%016llx flags=0x%04x]\n", | |
303 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
304 | address, flags); | |
e3e59876 | 305 | dump_dte_entry(devid); |
90008ee4 JR |
306 | break; |
307 | case EVENT_TYPE_IO_FAULT: | |
308 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
309 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
310 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
311 | domid, address, flags); | |
312 | break; | |
313 | case EVENT_TYPE_DEV_TAB_ERR: | |
314 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
315 | "address=0x%016llx flags=0x%04x]\n", | |
316 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
317 | address, flags); | |
318 | break; | |
319 | case EVENT_TYPE_PAGE_TAB_ERR: | |
320 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
321 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
322 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
323 | domid, address, flags); | |
324 | break; | |
325 | case EVENT_TYPE_ILL_CMD: | |
326 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 327 | dump_command(address); |
90008ee4 JR |
328 | break; |
329 | case EVENT_TYPE_CMD_HARD_ERR: | |
330 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
331 | "flags=0x%04x]\n", address, flags); | |
332 | break; | |
333 | case EVENT_TYPE_IOTLB_INV_TO: | |
334 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
335 | "address=0x%016llx]\n", | |
336 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
337 | address); | |
338 | break; | |
339 | case EVENT_TYPE_INV_DEV_REQ: | |
340 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
341 | "address=0x%016llx flags=0x%04x]\n", | |
342 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
343 | address, flags); | |
344 | break; | |
345 | default: | |
346 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
347 | } | |
348 | } | |
349 | ||
350 | static void iommu_poll_events(struct amd_iommu *iommu) | |
351 | { | |
352 | u32 head, tail; | |
353 | unsigned long flags; | |
354 | ||
355 | spin_lock_irqsave(&iommu->lock, flags); | |
356 | ||
357 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
358 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
359 | ||
360 | while (head != tail) { | |
a345b23b | 361 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
362 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
363 | } | |
364 | ||
365 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
366 | ||
367 | spin_unlock_irqrestore(&iommu->lock, flags); | |
368 | } | |
369 | ||
72fe00f0 | 370 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 371 | { |
90008ee4 JR |
372 | struct amd_iommu *iommu; |
373 | ||
3bd22172 | 374 | for_each_iommu(iommu) |
90008ee4 JR |
375 | iommu_poll_events(iommu); |
376 | ||
377 | return IRQ_HANDLED; | |
a80dc3e0 JR |
378 | } |
379 | ||
72fe00f0 JR |
380 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
381 | { | |
382 | return IRQ_WAKE_THREAD; | |
383 | } | |
384 | ||
431b2a20 JR |
385 | /**************************************************************************** |
386 | * | |
387 | * IOMMU command queuing functions | |
388 | * | |
389 | ****************************************************************************/ | |
390 | ||
ac0ea6e9 JR |
391 | static int wait_on_sem(volatile u64 *sem) |
392 | { | |
393 | int i = 0; | |
394 | ||
395 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
396 | udelay(1); | |
397 | i += 1; | |
398 | } | |
399 | ||
400 | if (i == LOOP_TIMEOUT) { | |
401 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
402 | return -EIO; | |
403 | } | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
409 | struct iommu_cmd *cmd, | |
410 | u32 tail) | |
a19ae1ec | 411 | { |
a19ae1ec JR |
412 | u8 *target; |
413 | ||
8a7c5ef3 | 414 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
415 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
416 | ||
417 | /* Copy command to buffer */ | |
418 | memcpy(target, cmd, sizeof(*cmd)); | |
419 | ||
420 | /* Tell the IOMMU about it */ | |
a19ae1ec | 421 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 422 | } |
a19ae1ec | 423 | |
815b33fd | 424 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 425 | { |
815b33fd JR |
426 | WARN_ON(address & 0x7ULL); |
427 | ||
ded46737 | 428 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
429 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
430 | cmd->data[1] = upper_32_bits(__pa(address)); | |
431 | cmd->data[2] = 1; | |
ded46737 JR |
432 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
433 | } | |
434 | ||
94fe79e2 JR |
435 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
436 | { | |
437 | memset(cmd, 0, sizeof(*cmd)); | |
438 | cmd->data[0] = devid; | |
439 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
440 | } | |
441 | ||
11b6402c JR |
442 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
443 | size_t size, u16 domid, int pde) | |
444 | { | |
445 | u64 pages; | |
446 | int s; | |
447 | ||
448 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
449 | s = 0; | |
450 | ||
451 | if (pages > 1) { | |
452 | /* | |
453 | * If we have to flush more than one page, flush all | |
454 | * TLB entries for this domain | |
455 | */ | |
456 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
457 | s = 1; | |
458 | } | |
459 | ||
460 | address &= PAGE_MASK; | |
461 | ||
462 | memset(cmd, 0, sizeof(*cmd)); | |
463 | cmd->data[1] |= domid; | |
464 | cmd->data[2] = lower_32_bits(address); | |
465 | cmd->data[3] = upper_32_bits(address); | |
466 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
467 | if (s) /* size bit - we flush more than one 4kb page */ | |
468 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
469 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
470 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
471 | } | |
472 | ||
cb41ed85 JR |
473 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
474 | u64 address, size_t size) | |
475 | { | |
476 | u64 pages; | |
477 | int s; | |
478 | ||
479 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
480 | s = 0; | |
481 | ||
482 | if (pages > 1) { | |
483 | /* | |
484 | * If we have to flush more than one page, flush all | |
485 | * TLB entries for this domain | |
486 | */ | |
487 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
488 | s = 1; | |
489 | } | |
490 | ||
491 | address &= PAGE_MASK; | |
492 | ||
493 | memset(cmd, 0, sizeof(*cmd)); | |
494 | cmd->data[0] = devid; | |
495 | cmd->data[0] |= (qdep & 0xff) << 24; | |
496 | cmd->data[1] = devid; | |
497 | cmd->data[2] = lower_32_bits(address); | |
498 | cmd->data[3] = upper_32_bits(address); | |
499 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
500 | if (s) | |
501 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
502 | } | |
503 | ||
58fc7f14 JR |
504 | static void build_inv_all(struct iommu_cmd *cmd) |
505 | { | |
506 | memset(cmd, 0, sizeof(*cmd)); | |
507 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
508 | } |
509 | ||
431b2a20 | 510 | /* |
431b2a20 | 511 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 512 | * hardware about the new command. |
431b2a20 | 513 | */ |
d6449536 | 514 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 515 | { |
ac0ea6e9 | 516 | u32 left, tail, head, next_tail; |
a19ae1ec | 517 | unsigned long flags; |
a19ae1ec | 518 | |
549c90dc | 519 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
520 | |
521 | again: | |
a19ae1ec | 522 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 523 | |
ac0ea6e9 JR |
524 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
525 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
526 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
527 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 528 | |
ac0ea6e9 JR |
529 | if (left <= 2) { |
530 | struct iommu_cmd sync_cmd; | |
531 | volatile u64 sem = 0; | |
532 | int ret; | |
8d201968 | 533 | |
ac0ea6e9 JR |
534 | build_completion_wait(&sync_cmd, (u64)&sem); |
535 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 536 | |
ac0ea6e9 JR |
537 | spin_unlock_irqrestore(&iommu->lock, flags); |
538 | ||
539 | if ((ret = wait_on_sem(&sem)) != 0) | |
540 | return ret; | |
541 | ||
542 | goto again; | |
8d201968 JR |
543 | } |
544 | ||
ac0ea6e9 JR |
545 | copy_cmd_to_buffer(iommu, cmd, tail); |
546 | ||
547 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 548 | iommu->need_sync = true; |
ac0ea6e9 | 549 | |
a19ae1ec | 550 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 551 | |
815b33fd | 552 | return 0; |
8d201968 JR |
553 | } |
554 | ||
555 | /* | |
556 | * This function queues a completion wait command into the command | |
557 | * buffer of an IOMMU | |
558 | */ | |
a19ae1ec | 559 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
560 | { |
561 | struct iommu_cmd cmd; | |
815b33fd | 562 | volatile u64 sem = 0; |
ac0ea6e9 | 563 | int ret; |
8d201968 | 564 | |
09ee17eb | 565 | if (!iommu->need_sync) |
815b33fd | 566 | return 0; |
09ee17eb | 567 | |
815b33fd | 568 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 569 | |
815b33fd | 570 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 571 | if (ret) |
815b33fd | 572 | return ret; |
8d201968 | 573 | |
ac0ea6e9 | 574 | return wait_on_sem(&sem); |
8d201968 JR |
575 | } |
576 | ||
d8c13085 | 577 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 578 | { |
d8c13085 | 579 | struct iommu_cmd cmd; |
a19ae1ec | 580 | |
d8c13085 | 581 | build_inv_dte(&cmd, devid); |
7e4f88da | 582 | |
d8c13085 JR |
583 | return iommu_queue_command(iommu, &cmd); |
584 | } | |
09ee17eb | 585 | |
7d0c5cc5 JR |
586 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
587 | { | |
588 | u32 devid; | |
09ee17eb | 589 | |
7d0c5cc5 JR |
590 | for (devid = 0; devid <= 0xffff; ++devid) |
591 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 592 | |
7d0c5cc5 JR |
593 | iommu_completion_wait(iommu); |
594 | } | |
84df8175 | 595 | |
7d0c5cc5 JR |
596 | /* |
597 | * This function uses heavy locking and may disable irqs for some time. But | |
598 | * this is no issue because it is only called during resume. | |
599 | */ | |
600 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
601 | { | |
602 | u32 dom_id; | |
a19ae1ec | 603 | |
7d0c5cc5 JR |
604 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
605 | struct iommu_cmd cmd; | |
606 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
607 | dom_id, 1); | |
608 | iommu_queue_command(iommu, &cmd); | |
609 | } | |
8eed9833 | 610 | |
7d0c5cc5 | 611 | iommu_completion_wait(iommu); |
a19ae1ec JR |
612 | } |
613 | ||
58fc7f14 | 614 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 615 | { |
58fc7f14 | 616 | struct iommu_cmd cmd; |
0518a3a4 | 617 | |
58fc7f14 | 618 | build_inv_all(&cmd); |
0518a3a4 | 619 | |
58fc7f14 JR |
620 | iommu_queue_command(iommu, &cmd); |
621 | iommu_completion_wait(iommu); | |
622 | } | |
623 | ||
7d0c5cc5 JR |
624 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
625 | { | |
58fc7f14 JR |
626 | if (iommu_feature(iommu, FEATURE_IA)) { |
627 | iommu_flush_all(iommu); | |
628 | } else { | |
629 | iommu_flush_dte_all(iommu); | |
630 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
631 | } |
632 | } | |
633 | ||
431b2a20 | 634 | /* |
cb41ed85 | 635 | * Command send function for flushing on-device TLB |
431b2a20 | 636 | */ |
cb41ed85 | 637 | static int device_flush_iotlb(struct device *dev, u64 address, size_t size) |
3fa43655 | 638 | { |
cb41ed85 | 639 | struct pci_dev *pdev = to_pci_dev(dev); |
3fa43655 | 640 | struct amd_iommu *iommu; |
b00d3bcf | 641 | struct iommu_cmd cmd; |
3fa43655 | 642 | u16 devid; |
cb41ed85 | 643 | int qdep; |
3fa43655 | 644 | |
cb41ed85 | 645 | qdep = pci_ats_queue_depth(pdev); |
3fa43655 JR |
646 | devid = get_device_id(dev); |
647 | iommu = amd_iommu_rlookup_table[devid]; | |
648 | ||
cb41ed85 | 649 | build_inv_iotlb_pages(&cmd, devid, qdep, address, size); |
b00d3bcf JR |
650 | |
651 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
652 | } |
653 | ||
431b2a20 | 654 | /* |
431b2a20 | 655 | * Command send function for invalidating a device table entry |
431b2a20 | 656 | */ |
d8c13085 | 657 | static int device_flush_dte(struct device *dev) |
a19ae1ec | 658 | { |
3fa43655 | 659 | struct amd_iommu *iommu; |
cb41ed85 | 660 | struct pci_dev *pdev; |
3fa43655 | 661 | u16 devid; |
ee2fa743 | 662 | int ret; |
a19ae1ec | 663 | |
cb41ed85 | 664 | pdev = to_pci_dev(dev); |
3fa43655 JR |
665 | devid = get_device_id(dev); |
666 | iommu = amd_iommu_rlookup_table[devid]; | |
a19ae1ec | 667 | |
cb41ed85 JR |
668 | ret = iommu_flush_dte(iommu, devid); |
669 | if (ret) | |
670 | return ret; | |
671 | ||
672 | if (pci_ats_enabled(pdev)) | |
673 | ret = device_flush_iotlb(dev, 0, ~0UL); | |
ee2fa743 | 674 | |
ee2fa743 | 675 | return ret; |
a19ae1ec JR |
676 | } |
677 | ||
431b2a20 JR |
678 | /* |
679 | * TLB invalidation function which is called from the mapping functions. | |
680 | * It invalidates a single PTE if the range to flush is within a single | |
681 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
682 | */ | |
17b124bf JR |
683 | static void __domain_flush_pages(struct protection_domain *domain, |
684 | u64 address, size_t size, int pde) | |
a19ae1ec | 685 | { |
cb41ed85 | 686 | struct iommu_dev_data *dev_data; |
11b6402c JR |
687 | struct iommu_cmd cmd; |
688 | int ret = 0, i; | |
a19ae1ec | 689 | |
11b6402c | 690 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 691 | |
6de8ad9b JR |
692 | for (i = 0; i < amd_iommus_present; ++i) { |
693 | if (!domain->dev_iommu[i]) | |
694 | continue; | |
695 | ||
696 | /* | |
697 | * Devices of this domain are behind this IOMMU | |
698 | * We need a TLB flush | |
699 | */ | |
11b6402c | 700 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
701 | } |
702 | ||
cb41ed85 JR |
703 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
704 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); | |
705 | ||
706 | if (!pci_ats_enabled(pdev)) | |
707 | continue; | |
708 | ||
709 | ret |= device_flush_iotlb(dev_data->dev, address, size); | |
710 | } | |
711 | ||
11b6402c | 712 | WARN_ON(ret); |
6de8ad9b JR |
713 | } |
714 | ||
17b124bf JR |
715 | static void domain_flush_pages(struct protection_domain *domain, |
716 | u64 address, size_t size) | |
6de8ad9b | 717 | { |
17b124bf | 718 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 719 | } |
b6c02715 | 720 | |
1c655773 | 721 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 722 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 723 | { |
17b124bf | 724 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
725 | } |
726 | ||
42a49f96 | 727 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 728 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 729 | { |
17b124bf | 730 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
731 | } |
732 | ||
17b124bf | 733 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 734 | { |
17b124bf | 735 | int i; |
18811f55 | 736 | |
17b124bf JR |
737 | for (i = 0; i < amd_iommus_present; ++i) { |
738 | if (!domain->dev_iommu[i]) | |
739 | continue; | |
bfd1be18 | 740 | |
17b124bf JR |
741 | /* |
742 | * Devices of this domain are behind this IOMMU | |
743 | * We need to wait for completion of all commands. | |
744 | */ | |
745 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 746 | } |
e394d72a JR |
747 | } |
748 | ||
b00d3bcf | 749 | |
09b42804 | 750 | /* |
b00d3bcf | 751 | * This function flushes the DTEs for all devices in domain |
09b42804 | 752 | */ |
17b124bf | 753 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 754 | { |
b00d3bcf | 755 | struct iommu_dev_data *dev_data; |
09b42804 JR |
756 | unsigned long flags; |
757 | ||
b00d3bcf | 758 | spin_lock_irqsave(&domain->lock, flags); |
b26e81b8 | 759 | |
b00d3bcf | 760 | list_for_each_entry(dev_data, &domain->dev_list, list) |
d8c13085 | 761 | device_flush_dte(dev_data->dev); |
b26e81b8 | 762 | |
b00d3bcf | 763 | spin_unlock_irqrestore(&domain->lock, flags); |
a345b23b JR |
764 | } |
765 | ||
431b2a20 JR |
766 | /**************************************************************************** |
767 | * | |
768 | * The functions below are used the create the page table mappings for | |
769 | * unity mapped regions. | |
770 | * | |
771 | ****************************************************************************/ | |
772 | ||
308973d3 JR |
773 | /* |
774 | * This function is used to add another level to an IO page table. Adding | |
775 | * another level increases the size of the address space by 9 bits to a size up | |
776 | * to 64 bits. | |
777 | */ | |
778 | static bool increase_address_space(struct protection_domain *domain, | |
779 | gfp_t gfp) | |
780 | { | |
781 | u64 *pte; | |
782 | ||
783 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
784 | /* address space already 64 bit large */ | |
785 | return false; | |
786 | ||
787 | pte = (void *)get_zeroed_page(gfp); | |
788 | if (!pte) | |
789 | return false; | |
790 | ||
791 | *pte = PM_LEVEL_PDE(domain->mode, | |
792 | virt_to_phys(domain->pt_root)); | |
793 | domain->pt_root = pte; | |
794 | domain->mode += 1; | |
795 | domain->updated = true; | |
796 | ||
797 | return true; | |
798 | } | |
799 | ||
800 | static u64 *alloc_pte(struct protection_domain *domain, | |
801 | unsigned long address, | |
cbb9d729 | 802 | unsigned long page_size, |
308973d3 JR |
803 | u64 **pte_page, |
804 | gfp_t gfp) | |
805 | { | |
cbb9d729 | 806 | int level, end_lvl; |
308973d3 | 807 | u64 *pte, *page; |
cbb9d729 JR |
808 | |
809 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
810 | |
811 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
812 | increase_address_space(domain, gfp); | |
813 | ||
cbb9d729 JR |
814 | level = domain->mode - 1; |
815 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
816 | address = PAGE_SIZE_ALIGN(address, page_size); | |
817 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
818 | |
819 | while (level > end_lvl) { | |
820 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
821 | page = (u64 *)get_zeroed_page(gfp); | |
822 | if (!page) | |
823 | return NULL; | |
824 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
825 | } | |
826 | ||
cbb9d729 JR |
827 | /* No level skipping support yet */ |
828 | if (PM_PTE_LEVEL(*pte) != level) | |
829 | return NULL; | |
830 | ||
308973d3 JR |
831 | level -= 1; |
832 | ||
833 | pte = IOMMU_PTE_PAGE(*pte); | |
834 | ||
835 | if (pte_page && level == end_lvl) | |
836 | *pte_page = pte; | |
837 | ||
838 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
839 | } | |
840 | ||
841 | return pte; | |
842 | } | |
843 | ||
844 | /* | |
845 | * This function checks if there is a PTE for a given dma address. If | |
846 | * there is one, it returns the pointer to it. | |
847 | */ | |
24cd7723 | 848 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
849 | { |
850 | int level; | |
851 | u64 *pte; | |
852 | ||
24cd7723 JR |
853 | if (address > PM_LEVEL_SIZE(domain->mode)) |
854 | return NULL; | |
855 | ||
856 | level = domain->mode - 1; | |
857 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 858 | |
24cd7723 JR |
859 | while (level > 0) { |
860 | ||
861 | /* Not Present */ | |
308973d3 JR |
862 | if (!IOMMU_PTE_PRESENT(*pte)) |
863 | return NULL; | |
864 | ||
24cd7723 JR |
865 | /* Large PTE */ |
866 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
867 | unsigned long pte_mask, __pte; | |
868 | ||
869 | /* | |
870 | * If we have a series of large PTEs, make | |
871 | * sure to return a pointer to the first one. | |
872 | */ | |
873 | pte_mask = PTE_PAGE_SIZE(*pte); | |
874 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
875 | __pte = ((unsigned long)pte) & pte_mask; | |
876 | ||
877 | return (u64 *)__pte; | |
878 | } | |
879 | ||
880 | /* No level skipping support yet */ | |
881 | if (PM_PTE_LEVEL(*pte) != level) | |
882 | return NULL; | |
883 | ||
308973d3 JR |
884 | level -= 1; |
885 | ||
24cd7723 | 886 | /* Walk to the next level */ |
308973d3 JR |
887 | pte = IOMMU_PTE_PAGE(*pte); |
888 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
889 | } |
890 | ||
891 | return pte; | |
892 | } | |
893 | ||
431b2a20 JR |
894 | /* |
895 | * Generic mapping functions. It maps a physical address into a DMA | |
896 | * address space. It allocates the page table pages if necessary. | |
897 | * In the future it can be extended to a generic mapping function | |
898 | * supporting all features of AMD IOMMU page tables like level skipping | |
899 | * and full 64 bit address spaces. | |
900 | */ | |
38e817fe JR |
901 | static int iommu_map_page(struct protection_domain *dom, |
902 | unsigned long bus_addr, | |
903 | unsigned long phys_addr, | |
abdc5eb3 | 904 | int prot, |
cbb9d729 | 905 | unsigned long page_size) |
bd0e5211 | 906 | { |
8bda3092 | 907 | u64 __pte, *pte; |
cbb9d729 | 908 | int i, count; |
abdc5eb3 | 909 | |
bad1cac2 | 910 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
911 | return -EINVAL; |
912 | ||
cbb9d729 JR |
913 | bus_addr = PAGE_ALIGN(bus_addr); |
914 | phys_addr = PAGE_ALIGN(phys_addr); | |
915 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
916 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
917 | ||
918 | for (i = 0; i < count; ++i) | |
919 | if (IOMMU_PTE_PRESENT(pte[i])) | |
920 | return -EBUSY; | |
bd0e5211 | 921 | |
cbb9d729 JR |
922 | if (page_size > PAGE_SIZE) { |
923 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
924 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
925 | } else | |
926 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 927 | |
bd0e5211 JR |
928 | if (prot & IOMMU_PROT_IR) |
929 | __pte |= IOMMU_PTE_IR; | |
930 | if (prot & IOMMU_PROT_IW) | |
931 | __pte |= IOMMU_PTE_IW; | |
932 | ||
cbb9d729 JR |
933 | for (i = 0; i < count; ++i) |
934 | pte[i] = __pte; | |
bd0e5211 | 935 | |
04bfdd84 JR |
936 | update_domain(dom); |
937 | ||
bd0e5211 JR |
938 | return 0; |
939 | } | |
940 | ||
24cd7723 JR |
941 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
942 | unsigned long bus_addr, | |
943 | unsigned long page_size) | |
eb74ff6c | 944 | { |
24cd7723 JR |
945 | unsigned long long unmap_size, unmapped; |
946 | u64 *pte; | |
947 | ||
948 | BUG_ON(!is_power_of_2(page_size)); | |
949 | ||
950 | unmapped = 0; | |
eb74ff6c | 951 | |
24cd7723 JR |
952 | while (unmapped < page_size) { |
953 | ||
954 | pte = fetch_pte(dom, bus_addr); | |
955 | ||
956 | if (!pte) { | |
957 | /* | |
958 | * No PTE for this address | |
959 | * move forward in 4kb steps | |
960 | */ | |
961 | unmap_size = PAGE_SIZE; | |
962 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
963 | /* 4kb PTE found for this address */ | |
964 | unmap_size = PAGE_SIZE; | |
965 | *pte = 0ULL; | |
966 | } else { | |
967 | int count, i; | |
968 | ||
969 | /* Large PTE found which maps this address */ | |
970 | unmap_size = PTE_PAGE_SIZE(*pte); | |
971 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
972 | for (i = 0; i < count; i++) | |
973 | pte[i] = 0ULL; | |
974 | } | |
975 | ||
976 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
977 | unmapped += unmap_size; | |
978 | } | |
979 | ||
980 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 981 | |
24cd7723 | 982 | return unmapped; |
eb74ff6c | 983 | } |
eb74ff6c | 984 | |
431b2a20 JR |
985 | /* |
986 | * This function checks if a specific unity mapping entry is needed for | |
987 | * this specific IOMMU. | |
988 | */ | |
bd0e5211 JR |
989 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
990 | struct unity_map_entry *entry) | |
991 | { | |
992 | u16 bdf, i; | |
993 | ||
994 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
995 | bdf = amd_iommu_alias_table[i]; | |
996 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
997 | return 1; | |
998 | } | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
431b2a20 JR |
1003 | /* |
1004 | * This function actually applies the mapping to the page table of the | |
1005 | * dma_ops domain. | |
1006 | */ | |
bd0e5211 JR |
1007 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1008 | struct unity_map_entry *e) | |
1009 | { | |
1010 | u64 addr; | |
1011 | int ret; | |
1012 | ||
1013 | for (addr = e->address_start; addr < e->address_end; | |
1014 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1015 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1016 | PAGE_SIZE); |
bd0e5211 JR |
1017 | if (ret) |
1018 | return ret; | |
1019 | /* | |
1020 | * if unity mapping is in aperture range mark the page | |
1021 | * as allocated in the aperture | |
1022 | */ | |
1023 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1024 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1025 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1026 | } |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
171e7b37 JR |
1031 | /* |
1032 | * Init the unity mappings for a specific IOMMU in the system | |
1033 | * | |
1034 | * Basically iterates over all unity mapping entries and applies them to | |
1035 | * the default domain DMA of that IOMMU if necessary. | |
1036 | */ | |
1037 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1038 | { | |
1039 | struct unity_map_entry *entry; | |
1040 | int ret; | |
1041 | ||
1042 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1043 | if (!iommu_for_unity_map(iommu, entry)) | |
1044 | continue; | |
1045 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1046 | if (ret) | |
1047 | return ret; | |
1048 | } | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
431b2a20 JR |
1053 | /* |
1054 | * Inits the unity mappings required for a specific device | |
1055 | */ | |
bd0e5211 JR |
1056 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1057 | u16 devid) | |
1058 | { | |
1059 | struct unity_map_entry *e; | |
1060 | int ret; | |
1061 | ||
1062 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1063 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1064 | continue; | |
1065 | ret = dma_ops_unity_map(dma_dom, e); | |
1066 | if (ret) | |
1067 | return ret; | |
1068 | } | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
431b2a20 JR |
1073 | /**************************************************************************** |
1074 | * | |
1075 | * The next functions belong to the address allocator for the dma_ops | |
1076 | * interface functions. They work like the allocators in the other IOMMU | |
1077 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1078 | * the aperture. Maybe it could be enhanced in the future to a more | |
1079 | * efficient allocator. | |
1080 | * | |
1081 | ****************************************************************************/ | |
d3086444 | 1082 | |
431b2a20 | 1083 | /* |
384de729 | 1084 | * The address allocator core functions. |
431b2a20 JR |
1085 | * |
1086 | * called with domain->lock held | |
1087 | */ | |
384de729 | 1088 | |
171e7b37 JR |
1089 | /* |
1090 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1091 | * ranges. | |
1092 | */ | |
1093 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1094 | unsigned long start_page, | |
1095 | unsigned int pages) | |
1096 | { | |
1097 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1098 | ||
1099 | if (start_page + pages > last_page) | |
1100 | pages = last_page - start_page; | |
1101 | ||
1102 | for (i = start_page; i < start_page + pages; ++i) { | |
1103 | int index = i / APERTURE_RANGE_PAGES; | |
1104 | int page = i % APERTURE_RANGE_PAGES; | |
1105 | __set_bit(page, dom->aperture[index]->bitmap); | |
1106 | } | |
1107 | } | |
1108 | ||
9cabe89b JR |
1109 | /* |
1110 | * This function is used to add a new aperture range to an existing | |
1111 | * aperture in case of dma_ops domain allocation or address allocation | |
1112 | * failure. | |
1113 | */ | |
576175c2 | 1114 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1115 | bool populate, gfp_t gfp) |
1116 | { | |
1117 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1118 | struct amd_iommu *iommu; |
d91afd15 | 1119 | unsigned long i; |
9cabe89b | 1120 | |
f5e9705c JR |
1121 | #ifdef CONFIG_IOMMU_STRESS |
1122 | populate = false; | |
1123 | #endif | |
1124 | ||
9cabe89b JR |
1125 | if (index >= APERTURE_MAX_RANGES) |
1126 | return -ENOMEM; | |
1127 | ||
1128 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1129 | if (!dma_dom->aperture[index]) | |
1130 | return -ENOMEM; | |
1131 | ||
1132 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1133 | if (!dma_dom->aperture[index]->bitmap) | |
1134 | goto out_free; | |
1135 | ||
1136 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1137 | ||
1138 | if (populate) { | |
1139 | unsigned long address = dma_dom->aperture_size; | |
1140 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1141 | u64 *pte, *pte_page; | |
1142 | ||
1143 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1144 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1145 | &pte_page, gfp); |
1146 | if (!pte) | |
1147 | goto out_free; | |
1148 | ||
1149 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1150 | ||
1151 | address += APERTURE_RANGE_SIZE / 64; | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1156 | ||
b595076a | 1157 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1158 | for_each_iommu(iommu) { |
1159 | if (iommu->exclusion_start && | |
1160 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1161 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1162 | unsigned long startpage; | |
1163 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1164 | iommu->exclusion_length, | |
1165 | PAGE_SIZE); | |
1166 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1167 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1168 | } | |
00cd122a JR |
1169 | } |
1170 | ||
1171 | /* | |
1172 | * Check for areas already mapped as present in the new aperture | |
1173 | * range and mark those pages as reserved in the allocator. Such | |
1174 | * mappings may already exist as a result of requested unity | |
1175 | * mappings for devices. | |
1176 | */ | |
1177 | for (i = dma_dom->aperture[index]->offset; | |
1178 | i < dma_dom->aperture_size; | |
1179 | i += PAGE_SIZE) { | |
24cd7723 | 1180 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1181 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1182 | continue; | |
1183 | ||
1184 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1185 | } | |
1186 | ||
04bfdd84 JR |
1187 | update_domain(&dma_dom->domain); |
1188 | ||
9cabe89b JR |
1189 | return 0; |
1190 | ||
1191 | out_free: | |
04bfdd84 JR |
1192 | update_domain(&dma_dom->domain); |
1193 | ||
9cabe89b JR |
1194 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1195 | ||
1196 | kfree(dma_dom->aperture[index]); | |
1197 | dma_dom->aperture[index] = NULL; | |
1198 | ||
1199 | return -ENOMEM; | |
1200 | } | |
1201 | ||
384de729 JR |
1202 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1203 | struct dma_ops_domain *dom, | |
1204 | unsigned int pages, | |
1205 | unsigned long align_mask, | |
1206 | u64 dma_mask, | |
1207 | unsigned long start) | |
1208 | { | |
803b8cb4 | 1209 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1210 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1211 | int i = start >> APERTURE_RANGE_SHIFT; | |
1212 | unsigned long boundary_size; | |
1213 | unsigned long address = -1; | |
1214 | unsigned long limit; | |
1215 | ||
803b8cb4 JR |
1216 | next_bit >>= PAGE_SHIFT; |
1217 | ||
384de729 JR |
1218 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1219 | PAGE_SIZE) >> PAGE_SHIFT; | |
1220 | ||
1221 | for (;i < max_index; ++i) { | |
1222 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1223 | ||
1224 | if (dom->aperture[i]->offset >= dma_mask) | |
1225 | break; | |
1226 | ||
1227 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1228 | dma_mask >> PAGE_SHIFT); | |
1229 | ||
1230 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1231 | limit, next_bit, pages, 0, | |
1232 | boundary_size, align_mask); | |
1233 | if (address != -1) { | |
1234 | address = dom->aperture[i]->offset + | |
1235 | (address << PAGE_SHIFT); | |
803b8cb4 | 1236 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1237 | break; |
1238 | } | |
1239 | ||
1240 | next_bit = 0; | |
1241 | } | |
1242 | ||
1243 | return address; | |
1244 | } | |
1245 | ||
d3086444 JR |
1246 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1247 | struct dma_ops_domain *dom, | |
6d4f343f | 1248 | unsigned int pages, |
832a90c3 JR |
1249 | unsigned long align_mask, |
1250 | u64 dma_mask) | |
d3086444 | 1251 | { |
d3086444 | 1252 | unsigned long address; |
d3086444 | 1253 | |
fe16f088 JR |
1254 | #ifdef CONFIG_IOMMU_STRESS |
1255 | dom->next_address = 0; | |
1256 | dom->need_flush = true; | |
1257 | #endif | |
d3086444 | 1258 | |
384de729 | 1259 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1260 | dma_mask, dom->next_address); |
d3086444 | 1261 | |
1c655773 | 1262 | if (address == -1) { |
803b8cb4 | 1263 | dom->next_address = 0; |
384de729 JR |
1264 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1265 | dma_mask, 0); | |
1c655773 JR |
1266 | dom->need_flush = true; |
1267 | } | |
d3086444 | 1268 | |
384de729 | 1269 | if (unlikely(address == -1)) |
8fd524b3 | 1270 | address = DMA_ERROR_CODE; |
d3086444 JR |
1271 | |
1272 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1273 | ||
1274 | return address; | |
1275 | } | |
1276 | ||
431b2a20 JR |
1277 | /* |
1278 | * The address free function. | |
1279 | * | |
1280 | * called with domain->lock held | |
1281 | */ | |
d3086444 JR |
1282 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1283 | unsigned long address, | |
1284 | unsigned int pages) | |
1285 | { | |
384de729 JR |
1286 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1287 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1288 | |
384de729 JR |
1289 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1290 | ||
47bccd6b JR |
1291 | #ifdef CONFIG_IOMMU_STRESS |
1292 | if (i < 4) | |
1293 | return; | |
1294 | #endif | |
80be308d | 1295 | |
803b8cb4 | 1296 | if (address >= dom->next_address) |
80be308d | 1297 | dom->need_flush = true; |
384de729 JR |
1298 | |
1299 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1300 | |
a66022c4 | 1301 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1302 | |
d3086444 JR |
1303 | } |
1304 | ||
431b2a20 JR |
1305 | /**************************************************************************** |
1306 | * | |
1307 | * The next functions belong to the domain allocation. A domain is | |
1308 | * allocated for every IOMMU as the default domain. If device isolation | |
1309 | * is enabled, every device get its own domain. The most important thing | |
1310 | * about domains is the page table mapping the DMA address space they | |
1311 | * contain. | |
1312 | * | |
1313 | ****************************************************************************/ | |
1314 | ||
aeb26f55 JR |
1315 | /* |
1316 | * This function adds a protection domain to the global protection domain list | |
1317 | */ | |
1318 | static void add_domain_to_list(struct protection_domain *domain) | |
1319 | { | |
1320 | unsigned long flags; | |
1321 | ||
1322 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1323 | list_add(&domain->list, &amd_iommu_pd_list); | |
1324 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1325 | } | |
1326 | ||
1327 | /* | |
1328 | * This function removes a protection domain to the global | |
1329 | * protection domain list | |
1330 | */ | |
1331 | static void del_domain_from_list(struct protection_domain *domain) | |
1332 | { | |
1333 | unsigned long flags; | |
1334 | ||
1335 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1336 | list_del(&domain->list); | |
1337 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1338 | } | |
1339 | ||
ec487d1a JR |
1340 | static u16 domain_id_alloc(void) |
1341 | { | |
1342 | unsigned long flags; | |
1343 | int id; | |
1344 | ||
1345 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1346 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1347 | BUG_ON(id == 0); | |
1348 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1349 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1350 | else | |
1351 | id = 0; | |
1352 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1353 | ||
1354 | return id; | |
1355 | } | |
1356 | ||
a2acfb75 JR |
1357 | static void domain_id_free(int id) |
1358 | { | |
1359 | unsigned long flags; | |
1360 | ||
1361 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1362 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1363 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1364 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1365 | } | |
a2acfb75 | 1366 | |
86db2e5d | 1367 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1368 | { |
1369 | int i, j; | |
1370 | u64 *p1, *p2, *p3; | |
1371 | ||
86db2e5d | 1372 | p1 = domain->pt_root; |
ec487d1a JR |
1373 | |
1374 | if (!p1) | |
1375 | return; | |
1376 | ||
1377 | for (i = 0; i < 512; ++i) { | |
1378 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1379 | continue; | |
1380 | ||
1381 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1382 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1383 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1384 | continue; | |
1385 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1386 | free_page((unsigned long)p3); | |
1387 | } | |
1388 | ||
1389 | free_page((unsigned long)p2); | |
1390 | } | |
1391 | ||
1392 | free_page((unsigned long)p1); | |
86db2e5d JR |
1393 | |
1394 | domain->pt_root = NULL; | |
ec487d1a JR |
1395 | } |
1396 | ||
431b2a20 JR |
1397 | /* |
1398 | * Free a domain, only used if something went wrong in the | |
1399 | * allocation path and we need to free an already allocated page table | |
1400 | */ | |
ec487d1a JR |
1401 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1402 | { | |
384de729 JR |
1403 | int i; |
1404 | ||
ec487d1a JR |
1405 | if (!dom) |
1406 | return; | |
1407 | ||
aeb26f55 JR |
1408 | del_domain_from_list(&dom->domain); |
1409 | ||
86db2e5d | 1410 | free_pagetable(&dom->domain); |
ec487d1a | 1411 | |
384de729 JR |
1412 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1413 | if (!dom->aperture[i]) | |
1414 | continue; | |
1415 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1416 | kfree(dom->aperture[i]); | |
1417 | } | |
ec487d1a JR |
1418 | |
1419 | kfree(dom); | |
1420 | } | |
1421 | ||
431b2a20 JR |
1422 | /* |
1423 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1424 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1425 | * structures required for the dma_ops interface |
1426 | */ | |
87a64d52 | 1427 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1428 | { |
1429 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1430 | |
1431 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1432 | if (!dma_dom) | |
1433 | return NULL; | |
1434 | ||
1435 | spin_lock_init(&dma_dom->domain.lock); | |
1436 | ||
1437 | dma_dom->domain.id = domain_id_alloc(); | |
1438 | if (dma_dom->domain.id == 0) | |
1439 | goto free_dma_dom; | |
7c392cbe | 1440 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1441 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1442 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1443 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1444 | dma_dom->domain.priv = dma_dom; |
1445 | if (!dma_dom->domain.pt_root) | |
1446 | goto free_dma_dom; | |
ec487d1a | 1447 | |
1c655773 | 1448 | dma_dom->need_flush = false; |
bd60b735 | 1449 | dma_dom->target_dev = 0xffff; |
1c655773 | 1450 | |
aeb26f55 JR |
1451 | add_domain_to_list(&dma_dom->domain); |
1452 | ||
576175c2 | 1453 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1454 | goto free_dma_dom; |
ec487d1a | 1455 | |
431b2a20 | 1456 | /* |
ec487d1a JR |
1457 | * mark the first page as allocated so we never return 0 as |
1458 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1459 | */ |
384de729 | 1460 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1461 | dma_dom->next_address = 0; |
ec487d1a | 1462 | |
ec487d1a JR |
1463 | |
1464 | return dma_dom; | |
1465 | ||
1466 | free_dma_dom: | |
1467 | dma_ops_domain_free(dma_dom); | |
1468 | ||
1469 | return NULL; | |
1470 | } | |
1471 | ||
5b28df6f JR |
1472 | /* |
1473 | * little helper function to check whether a given protection domain is a | |
1474 | * dma_ops domain | |
1475 | */ | |
1476 | static bool dma_ops_domain(struct protection_domain *domain) | |
1477 | { | |
1478 | return domain->flags & PD_DMA_OPS_MASK; | |
1479 | } | |
1480 | ||
fd7b5535 | 1481 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1482 | { |
b20ac0d4 | 1483 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1484 | u32 flags = 0; |
863c74eb | 1485 | |
38ddf41b JR |
1486 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1487 | << DEV_ENTRY_MODE_SHIFT; | |
1488 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1489 | |
fd7b5535 JR |
1490 | if (ats) |
1491 | flags |= DTE_FLAG_IOTLB; | |
1492 | ||
1493 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1494 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1495 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1496 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1497 | } |
1498 | ||
1499 | static void clear_dte_entry(u16 devid) | |
1500 | { | |
15898bbc JR |
1501 | /* remove entry from the device table seen by the hardware */ |
1502 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1503 | amd_iommu_dev_table[devid].data[1] = 0; | |
1504 | amd_iommu_dev_table[devid].data[2] = 0; | |
1505 | ||
1506 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1507 | } |
1508 | ||
1509 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1510 | { | |
1511 | struct iommu_dev_data *dev_data; | |
1512 | struct amd_iommu *iommu; | |
fd7b5535 JR |
1513 | struct pci_dev *pdev; |
1514 | bool ats = false; | |
7f760ddd JR |
1515 | u16 devid; |
1516 | ||
1517 | devid = get_device_id(dev); | |
1518 | iommu = amd_iommu_rlookup_table[devid]; | |
1519 | dev_data = get_dev_data(dev); | |
fd7b5535 JR |
1520 | pdev = to_pci_dev(dev); |
1521 | ||
1522 | if (amd_iommu_iotlb_sup) | |
1523 | ats = pci_ats_enabled(pdev); | |
7f760ddd JR |
1524 | |
1525 | /* Update data structures */ | |
1526 | dev_data->domain = domain; | |
1527 | list_add(&dev_data->list, &domain->dev_list); | |
fd7b5535 | 1528 | set_dte_entry(devid, domain, ats); |
7f760ddd JR |
1529 | |
1530 | /* Do reference counting */ | |
1531 | domain->dev_iommu[iommu->index] += 1; | |
1532 | domain->dev_cnt += 1; | |
1533 | ||
1534 | /* Flush the DTE entry */ | |
d8c13085 | 1535 | device_flush_dte(dev); |
7f760ddd JR |
1536 | } |
1537 | ||
1538 | static void do_detach(struct device *dev) | |
1539 | { | |
1540 | struct iommu_dev_data *dev_data; | |
1541 | struct amd_iommu *iommu; | |
1542 | u16 devid; | |
1543 | ||
1544 | devid = get_device_id(dev); | |
1545 | iommu = amd_iommu_rlookup_table[devid]; | |
1546 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1547 | |
1548 | /* decrease reference counters */ | |
7f760ddd JR |
1549 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1550 | dev_data->domain->dev_cnt -= 1; | |
1551 | ||
1552 | /* Update data structures */ | |
1553 | dev_data->domain = NULL; | |
1554 | list_del(&dev_data->list); | |
1555 | clear_dte_entry(devid); | |
15898bbc | 1556 | |
7f760ddd | 1557 | /* Flush the DTE entry */ |
d8c13085 | 1558 | device_flush_dte(dev); |
2b681faf JR |
1559 | } |
1560 | ||
1561 | /* | |
1562 | * If a device is not yet associated with a domain, this function does | |
1563 | * assigns it visible for the hardware | |
1564 | */ | |
15898bbc JR |
1565 | static int __attach_device(struct device *dev, |
1566 | struct protection_domain *domain) | |
2b681faf | 1567 | { |
657cbb6b | 1568 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1569 | int ret; |
657cbb6b | 1570 | |
657cbb6b JR |
1571 | dev_data = get_dev_data(dev); |
1572 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1573 | |
657cbb6b JR |
1574 | if (!alias_data) |
1575 | return -EINVAL; | |
15898bbc | 1576 | |
2b681faf JR |
1577 | /* lock domain */ |
1578 | spin_lock(&domain->lock); | |
1579 | ||
15898bbc | 1580 | /* Some sanity checks */ |
84fe6c19 | 1581 | ret = -EBUSY; |
657cbb6b JR |
1582 | if (alias_data->domain != NULL && |
1583 | alias_data->domain != domain) | |
84fe6c19 | 1584 | goto out_unlock; |
eba6ac60 | 1585 | |
657cbb6b JR |
1586 | if (dev_data->domain != NULL && |
1587 | dev_data->domain != domain) | |
84fe6c19 | 1588 | goto out_unlock; |
15898bbc JR |
1589 | |
1590 | /* Do real assignment */ | |
7f760ddd JR |
1591 | if (dev_data->alias != dev) { |
1592 | alias_data = get_dev_data(dev_data->alias); | |
1593 | if (alias_data->domain == NULL) | |
1594 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1595 | |
1596 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1597 | } |
15898bbc | 1598 | |
7f760ddd JR |
1599 | if (dev_data->domain == NULL) |
1600 | do_attach(dev, domain); | |
eba6ac60 | 1601 | |
24100055 JR |
1602 | atomic_inc(&dev_data->bind); |
1603 | ||
84fe6c19 JL |
1604 | ret = 0; |
1605 | ||
1606 | out_unlock: | |
1607 | ||
eba6ac60 JR |
1608 | /* ready */ |
1609 | spin_unlock(&domain->lock); | |
15898bbc | 1610 | |
84fe6c19 | 1611 | return ret; |
0feae533 | 1612 | } |
b20ac0d4 | 1613 | |
407d733e JR |
1614 | /* |
1615 | * If a device is not yet associated with a domain, this function does | |
1616 | * assigns it visible for the hardware | |
1617 | */ | |
15898bbc JR |
1618 | static int attach_device(struct device *dev, |
1619 | struct protection_domain *domain) | |
0feae533 | 1620 | { |
fd7b5535 | 1621 | struct pci_dev *pdev = to_pci_dev(dev); |
eba6ac60 | 1622 | unsigned long flags; |
15898bbc | 1623 | int ret; |
eba6ac60 | 1624 | |
fd7b5535 JR |
1625 | if (amd_iommu_iotlb_sup) |
1626 | pci_enable_ats(pdev, PAGE_SHIFT); | |
1627 | ||
eba6ac60 | 1628 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
15898bbc | 1629 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1630 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1631 | ||
0feae533 JR |
1632 | /* |
1633 | * We might boot into a crash-kernel here. The crashed kernel | |
1634 | * left the caches in the IOMMU dirty. So we have to flush | |
1635 | * here to evict all dirty stuff. | |
1636 | */ | |
17b124bf | 1637 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1638 | |
1639 | return ret; | |
b20ac0d4 JR |
1640 | } |
1641 | ||
355bf553 JR |
1642 | /* |
1643 | * Removes a device from a protection domain (unlocked) | |
1644 | */ | |
15898bbc | 1645 | static void __detach_device(struct device *dev) |
355bf553 | 1646 | { |
657cbb6b | 1647 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1648 | struct iommu_dev_data *alias_data; |
2ca76279 | 1649 | struct protection_domain *domain; |
7c392cbe | 1650 | unsigned long flags; |
c4596114 | 1651 | |
7f760ddd | 1652 | BUG_ON(!dev_data->domain); |
355bf553 | 1653 | |
2ca76279 JR |
1654 | domain = dev_data->domain; |
1655 | ||
1656 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1657 | |
7f760ddd | 1658 | if (dev_data->alias != dev) { |
24100055 | 1659 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1660 | if (atomic_dec_and_test(&alias_data->bind)) |
1661 | do_detach(dev_data->alias); | |
24100055 JR |
1662 | } |
1663 | ||
7f760ddd JR |
1664 | if (atomic_dec_and_test(&dev_data->bind)) |
1665 | do_detach(dev); | |
1666 | ||
2ca76279 | 1667 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1668 | |
1669 | /* | |
1670 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1671 | * passthrough domain if it is detached from any other domain. |
1672 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1673 | */ |
d3ad9373 JR |
1674 | if (iommu_pass_through && |
1675 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1676 | __attach_device(dev, pt_domain); |
355bf553 JR |
1677 | } |
1678 | ||
1679 | /* | |
1680 | * Removes a device from a protection domain (with devtable_lock held) | |
1681 | */ | |
15898bbc | 1682 | static void detach_device(struct device *dev) |
355bf553 | 1683 | { |
fd7b5535 | 1684 | struct pci_dev *pdev = to_pci_dev(dev); |
355bf553 JR |
1685 | unsigned long flags; |
1686 | ||
1687 | /* lock device table */ | |
1688 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1689 | __detach_device(dev); |
355bf553 | 1690 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 JR |
1691 | |
1692 | if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev)) | |
1693 | pci_disable_ats(pdev); | |
355bf553 | 1694 | } |
e275a2a0 | 1695 | |
15898bbc JR |
1696 | /* |
1697 | * Find out the protection domain structure for a given PCI device. This | |
1698 | * will give us the pointer to the page table root for example. | |
1699 | */ | |
1700 | static struct protection_domain *domain_for_device(struct device *dev) | |
1701 | { | |
1702 | struct protection_domain *dom; | |
657cbb6b | 1703 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc | 1704 | unsigned long flags; |
6ec5ff4b | 1705 | u16 devid; |
15898bbc | 1706 | |
657cbb6b | 1707 | devid = get_device_id(dev); |
657cbb6b JR |
1708 | dev_data = get_dev_data(dev); |
1709 | alias_data = get_dev_data(dev_data->alias); | |
1710 | if (!alias_data) | |
1711 | return NULL; | |
15898bbc JR |
1712 | |
1713 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1714 | dom = dev_data->domain; |
15898bbc | 1715 | if (dom == NULL && |
657cbb6b JR |
1716 | alias_data->domain != NULL) { |
1717 | __attach_device(dev, alias_data->domain); | |
1718 | dom = alias_data->domain; | |
15898bbc JR |
1719 | } |
1720 | ||
1721 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1722 | ||
1723 | return dom; | |
1724 | } | |
1725 | ||
e275a2a0 JR |
1726 | static int device_change_notifier(struct notifier_block *nb, |
1727 | unsigned long action, void *data) | |
1728 | { | |
1729 | struct device *dev = data; | |
98fc5a69 | 1730 | u16 devid; |
e275a2a0 JR |
1731 | struct protection_domain *domain; |
1732 | struct dma_ops_domain *dma_domain; | |
1733 | struct amd_iommu *iommu; | |
1ac4cbbc | 1734 | unsigned long flags; |
e275a2a0 | 1735 | |
98fc5a69 JR |
1736 | if (!check_device(dev)) |
1737 | return 0; | |
e275a2a0 | 1738 | |
98fc5a69 JR |
1739 | devid = get_device_id(dev); |
1740 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1741 | |
1742 | switch (action) { | |
c1eee67b | 1743 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1744 | |
1745 | domain = domain_for_device(dev); | |
1746 | ||
e275a2a0 JR |
1747 | if (!domain) |
1748 | goto out; | |
a1ca331c JR |
1749 | if (iommu_pass_through) |
1750 | break; | |
15898bbc | 1751 | detach_device(dev); |
1ac4cbbc JR |
1752 | break; |
1753 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1754 | |
1755 | iommu_init_device(dev); | |
1756 | ||
1757 | domain = domain_for_device(dev); | |
1758 | ||
1ac4cbbc JR |
1759 | /* allocate a protection domain if a device is added */ |
1760 | dma_domain = find_protection_domain(devid); | |
1761 | if (dma_domain) | |
1762 | goto out; | |
87a64d52 | 1763 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1764 | if (!dma_domain) |
1765 | goto out; | |
1766 | dma_domain->target_dev = devid; | |
1767 | ||
1768 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1769 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1770 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1771 | ||
e275a2a0 | 1772 | break; |
657cbb6b JR |
1773 | case BUS_NOTIFY_DEL_DEVICE: |
1774 | ||
1775 | iommu_uninit_device(dev); | |
1776 | ||
e275a2a0 JR |
1777 | default: |
1778 | goto out; | |
1779 | } | |
1780 | ||
d8c13085 | 1781 | device_flush_dte(dev); |
e275a2a0 JR |
1782 | iommu_completion_wait(iommu); |
1783 | ||
1784 | out: | |
1785 | return 0; | |
1786 | } | |
1787 | ||
b25ae679 | 1788 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1789 | .notifier_call = device_change_notifier, |
1790 | }; | |
355bf553 | 1791 | |
8638c491 JR |
1792 | void amd_iommu_init_notifier(void) |
1793 | { | |
1794 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1795 | } | |
1796 | ||
431b2a20 JR |
1797 | /***************************************************************************** |
1798 | * | |
1799 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1800 | * | |
1801 | *****************************************************************************/ | |
1802 | ||
1803 | /* | |
1804 | * In the dma_ops path we only have the struct device. This function | |
1805 | * finds the corresponding IOMMU, the protection domain and the | |
1806 | * requestor id for a given device. | |
1807 | * If the device is not yet associated with a domain this is also done | |
1808 | * in this function. | |
1809 | */ | |
94f6d190 | 1810 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1811 | { |
94f6d190 | 1812 | struct protection_domain *domain; |
b20ac0d4 | 1813 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1814 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1815 | |
f99c0f1c | 1816 | if (!check_device(dev)) |
94f6d190 | 1817 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1818 | |
94f6d190 JR |
1819 | domain = domain_for_device(dev); |
1820 | if (domain != NULL && !dma_ops_domain(domain)) | |
1821 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1822 | |
94f6d190 JR |
1823 | if (domain != NULL) |
1824 | return domain; | |
b20ac0d4 | 1825 | |
15898bbc | 1826 | /* Device not bount yet - bind it */ |
94f6d190 | 1827 | dma_dom = find_protection_domain(devid); |
15898bbc | 1828 | if (!dma_dom) |
94f6d190 JR |
1829 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1830 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1831 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1832 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1833 | |
94f6d190 | 1834 | return &dma_dom->domain; |
b20ac0d4 JR |
1835 | } |
1836 | ||
04bfdd84 JR |
1837 | static void update_device_table(struct protection_domain *domain) |
1838 | { | |
492667da | 1839 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1840 | |
492667da | 1841 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
fd7b5535 | 1842 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); |
492667da | 1843 | u16 devid = get_device_id(dev_data->dev); |
fd7b5535 | 1844 | set_dte_entry(devid, domain, pci_ats_enabled(pdev)); |
04bfdd84 JR |
1845 | } |
1846 | } | |
1847 | ||
1848 | static void update_domain(struct protection_domain *domain) | |
1849 | { | |
1850 | if (!domain->updated) | |
1851 | return; | |
1852 | ||
1853 | update_device_table(domain); | |
17b124bf JR |
1854 | |
1855 | domain_flush_devices(domain); | |
1856 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1857 | |
1858 | domain->updated = false; | |
1859 | } | |
1860 | ||
8bda3092 JR |
1861 | /* |
1862 | * This function fetches the PTE for a given address in the aperture | |
1863 | */ | |
1864 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1865 | unsigned long address) | |
1866 | { | |
384de729 | 1867 | struct aperture_range *aperture; |
8bda3092 JR |
1868 | u64 *pte, *pte_page; |
1869 | ||
384de729 JR |
1870 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1871 | if (!aperture) | |
1872 | return NULL; | |
1873 | ||
1874 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1875 | if (!pte) { |
cbb9d729 | 1876 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1877 | GFP_ATOMIC); |
384de729 JR |
1878 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1879 | } else | |
8c8c143c | 1880 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1881 | |
04bfdd84 | 1882 | update_domain(&dom->domain); |
8bda3092 JR |
1883 | |
1884 | return pte; | |
1885 | } | |
1886 | ||
431b2a20 JR |
1887 | /* |
1888 | * This is the generic map function. It maps one 4kb page at paddr to | |
1889 | * the given address in the DMA address space for the domain. | |
1890 | */ | |
680525e0 | 1891 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1892 | unsigned long address, |
1893 | phys_addr_t paddr, | |
1894 | int direction) | |
1895 | { | |
1896 | u64 *pte, __pte; | |
1897 | ||
1898 | WARN_ON(address > dom->aperture_size); | |
1899 | ||
1900 | paddr &= PAGE_MASK; | |
1901 | ||
8bda3092 | 1902 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1903 | if (!pte) |
8fd524b3 | 1904 | return DMA_ERROR_CODE; |
cb76c322 JR |
1905 | |
1906 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1907 | ||
1908 | if (direction == DMA_TO_DEVICE) | |
1909 | __pte |= IOMMU_PTE_IR; | |
1910 | else if (direction == DMA_FROM_DEVICE) | |
1911 | __pte |= IOMMU_PTE_IW; | |
1912 | else if (direction == DMA_BIDIRECTIONAL) | |
1913 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1914 | ||
1915 | WARN_ON(*pte); | |
1916 | ||
1917 | *pte = __pte; | |
1918 | ||
1919 | return (dma_addr_t)address; | |
1920 | } | |
1921 | ||
431b2a20 JR |
1922 | /* |
1923 | * The generic unmapping function for on page in the DMA address space. | |
1924 | */ | |
680525e0 | 1925 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1926 | unsigned long address) |
1927 | { | |
384de729 | 1928 | struct aperture_range *aperture; |
cb76c322 JR |
1929 | u64 *pte; |
1930 | ||
1931 | if (address >= dom->aperture_size) | |
1932 | return; | |
1933 | ||
384de729 JR |
1934 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1935 | if (!aperture) | |
1936 | return; | |
1937 | ||
1938 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1939 | if (!pte) | |
1940 | return; | |
cb76c322 | 1941 | |
8c8c143c | 1942 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1943 | |
1944 | WARN_ON(!*pte); | |
1945 | ||
1946 | *pte = 0ULL; | |
1947 | } | |
1948 | ||
431b2a20 JR |
1949 | /* |
1950 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1951 | * contiguous memory region into DMA address space. It is used by all |
1952 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1953 | * Must be called with the domain lock held. |
1954 | */ | |
cb76c322 | 1955 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1956 | struct dma_ops_domain *dma_dom, |
1957 | phys_addr_t paddr, | |
1958 | size_t size, | |
6d4f343f | 1959 | int dir, |
832a90c3 JR |
1960 | bool align, |
1961 | u64 dma_mask) | |
cb76c322 JR |
1962 | { |
1963 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1964 | dma_addr_t address, start, ret; |
cb76c322 | 1965 | unsigned int pages; |
6d4f343f | 1966 | unsigned long align_mask = 0; |
cb76c322 JR |
1967 | int i; |
1968 | ||
e3c449f5 | 1969 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1970 | paddr &= PAGE_MASK; |
1971 | ||
8ecaf8f1 JR |
1972 | INC_STATS_COUNTER(total_map_requests); |
1973 | ||
c1858976 JR |
1974 | if (pages > 1) |
1975 | INC_STATS_COUNTER(cross_page); | |
1976 | ||
6d4f343f JR |
1977 | if (align) |
1978 | align_mask = (1UL << get_order(size)) - 1; | |
1979 | ||
11b83888 | 1980 | retry: |
832a90c3 JR |
1981 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1982 | dma_mask); | |
8fd524b3 | 1983 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1984 | /* |
1985 | * setting next_address here will let the address | |
1986 | * allocator only scan the new allocated range in the | |
1987 | * first run. This is a small optimization. | |
1988 | */ | |
1989 | dma_dom->next_address = dma_dom->aperture_size; | |
1990 | ||
576175c2 | 1991 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1992 | goto out; |
1993 | ||
1994 | /* | |
af901ca1 | 1995 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1996 | * allocation again |
1997 | */ | |
1998 | goto retry; | |
1999 | } | |
cb76c322 JR |
2000 | |
2001 | start = address; | |
2002 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2003 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2004 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2005 | goto out_unmap; |
2006 | ||
cb76c322 JR |
2007 | paddr += PAGE_SIZE; |
2008 | start += PAGE_SIZE; | |
2009 | } | |
2010 | address += offset; | |
2011 | ||
5774f7c5 JR |
2012 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2013 | ||
afa9fdc2 | 2014 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2015 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2016 | dma_dom->need_flush = false; |
318afd41 | 2017 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2018 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2019 | |
cb76c322 JR |
2020 | out: |
2021 | return address; | |
53812c11 JR |
2022 | |
2023 | out_unmap: | |
2024 | ||
2025 | for (--i; i >= 0; --i) { | |
2026 | start -= PAGE_SIZE; | |
680525e0 | 2027 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2028 | } |
2029 | ||
2030 | dma_ops_free_addresses(dma_dom, address, pages); | |
2031 | ||
8fd524b3 | 2032 | return DMA_ERROR_CODE; |
cb76c322 JR |
2033 | } |
2034 | ||
431b2a20 JR |
2035 | /* |
2036 | * Does the reverse of the __map_single function. Must be called with | |
2037 | * the domain lock held too | |
2038 | */ | |
cd8c82e8 | 2039 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2040 | dma_addr_t dma_addr, |
2041 | size_t size, | |
2042 | int dir) | |
2043 | { | |
04e0463e | 2044 | dma_addr_t flush_addr; |
cb76c322 JR |
2045 | dma_addr_t i, start; |
2046 | unsigned int pages; | |
2047 | ||
8fd524b3 | 2048 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2049 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2050 | return; |
2051 | ||
04e0463e | 2052 | flush_addr = dma_addr; |
e3c449f5 | 2053 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2054 | dma_addr &= PAGE_MASK; |
2055 | start = dma_addr; | |
2056 | ||
2057 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2058 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2059 | start += PAGE_SIZE; |
2060 | } | |
2061 | ||
5774f7c5 JR |
2062 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2063 | ||
cb76c322 | 2064 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2065 | |
80be308d | 2066 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2067 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2068 | dma_dom->need_flush = false; |
2069 | } | |
cb76c322 JR |
2070 | } |
2071 | ||
431b2a20 JR |
2072 | /* |
2073 | * The exported map_single function for dma_ops. | |
2074 | */ | |
51491367 FT |
2075 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2076 | unsigned long offset, size_t size, | |
2077 | enum dma_data_direction dir, | |
2078 | struct dma_attrs *attrs) | |
4da70b9e JR |
2079 | { |
2080 | unsigned long flags; | |
4da70b9e | 2081 | struct protection_domain *domain; |
4da70b9e | 2082 | dma_addr_t addr; |
832a90c3 | 2083 | u64 dma_mask; |
51491367 | 2084 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2085 | |
0f2a86f2 JR |
2086 | INC_STATS_COUNTER(cnt_map_single); |
2087 | ||
94f6d190 JR |
2088 | domain = get_domain(dev); |
2089 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2090 | return (dma_addr_t)paddr; |
94f6d190 JR |
2091 | else if (IS_ERR(domain)) |
2092 | return DMA_ERROR_CODE; | |
4da70b9e | 2093 | |
f99c0f1c JR |
2094 | dma_mask = *dev->dma_mask; |
2095 | ||
4da70b9e | 2096 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2097 | |
cd8c82e8 | 2098 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2099 | dma_mask); |
8fd524b3 | 2100 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2101 | goto out; |
2102 | ||
17b124bf | 2103 | domain_flush_complete(domain); |
4da70b9e JR |
2104 | |
2105 | out: | |
2106 | spin_unlock_irqrestore(&domain->lock, flags); | |
2107 | ||
2108 | return addr; | |
2109 | } | |
2110 | ||
431b2a20 JR |
2111 | /* |
2112 | * The exported unmap_single function for dma_ops. | |
2113 | */ | |
51491367 FT |
2114 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2115 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2116 | { |
2117 | unsigned long flags; | |
4da70b9e | 2118 | struct protection_domain *domain; |
4da70b9e | 2119 | |
146a6917 JR |
2120 | INC_STATS_COUNTER(cnt_unmap_single); |
2121 | ||
94f6d190 JR |
2122 | domain = get_domain(dev); |
2123 | if (IS_ERR(domain)) | |
5b28df6f JR |
2124 | return; |
2125 | ||
4da70b9e JR |
2126 | spin_lock_irqsave(&domain->lock, flags); |
2127 | ||
cd8c82e8 | 2128 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2129 | |
17b124bf | 2130 | domain_flush_complete(domain); |
4da70b9e JR |
2131 | |
2132 | spin_unlock_irqrestore(&domain->lock, flags); | |
2133 | } | |
2134 | ||
431b2a20 JR |
2135 | /* |
2136 | * This is a special map_sg function which is used if we should map a | |
2137 | * device which is not handled by an AMD IOMMU in the system. | |
2138 | */ | |
65b050ad JR |
2139 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2140 | int nelems, int dir) | |
2141 | { | |
2142 | struct scatterlist *s; | |
2143 | int i; | |
2144 | ||
2145 | for_each_sg(sglist, s, nelems, i) { | |
2146 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2147 | s->dma_length = s->length; | |
2148 | } | |
2149 | ||
2150 | return nelems; | |
2151 | } | |
2152 | ||
431b2a20 JR |
2153 | /* |
2154 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2155 | * lists). | |
2156 | */ | |
65b050ad | 2157 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2158 | int nelems, enum dma_data_direction dir, |
2159 | struct dma_attrs *attrs) | |
65b050ad JR |
2160 | { |
2161 | unsigned long flags; | |
65b050ad | 2162 | struct protection_domain *domain; |
65b050ad JR |
2163 | int i; |
2164 | struct scatterlist *s; | |
2165 | phys_addr_t paddr; | |
2166 | int mapped_elems = 0; | |
832a90c3 | 2167 | u64 dma_mask; |
65b050ad | 2168 | |
d03f067a JR |
2169 | INC_STATS_COUNTER(cnt_map_sg); |
2170 | ||
94f6d190 JR |
2171 | domain = get_domain(dev); |
2172 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2173 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2174 | else if (IS_ERR(domain)) |
2175 | return 0; | |
dbcc112e | 2176 | |
832a90c3 | 2177 | dma_mask = *dev->dma_mask; |
65b050ad | 2178 | |
65b050ad JR |
2179 | spin_lock_irqsave(&domain->lock, flags); |
2180 | ||
2181 | for_each_sg(sglist, s, nelems, i) { | |
2182 | paddr = sg_phys(s); | |
2183 | ||
cd8c82e8 | 2184 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2185 | paddr, s->length, dir, false, |
2186 | dma_mask); | |
65b050ad JR |
2187 | |
2188 | if (s->dma_address) { | |
2189 | s->dma_length = s->length; | |
2190 | mapped_elems++; | |
2191 | } else | |
2192 | goto unmap; | |
65b050ad JR |
2193 | } |
2194 | ||
17b124bf | 2195 | domain_flush_complete(domain); |
65b050ad JR |
2196 | |
2197 | out: | |
2198 | spin_unlock_irqrestore(&domain->lock, flags); | |
2199 | ||
2200 | return mapped_elems; | |
2201 | unmap: | |
2202 | for_each_sg(sglist, s, mapped_elems, i) { | |
2203 | if (s->dma_address) | |
cd8c82e8 | 2204 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2205 | s->dma_length, dir); |
2206 | s->dma_address = s->dma_length = 0; | |
2207 | } | |
2208 | ||
2209 | mapped_elems = 0; | |
2210 | ||
2211 | goto out; | |
2212 | } | |
2213 | ||
431b2a20 JR |
2214 | /* |
2215 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2216 | * lists). | |
2217 | */ | |
65b050ad | 2218 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2219 | int nelems, enum dma_data_direction dir, |
2220 | struct dma_attrs *attrs) | |
65b050ad JR |
2221 | { |
2222 | unsigned long flags; | |
65b050ad JR |
2223 | struct protection_domain *domain; |
2224 | struct scatterlist *s; | |
65b050ad JR |
2225 | int i; |
2226 | ||
55877a6b JR |
2227 | INC_STATS_COUNTER(cnt_unmap_sg); |
2228 | ||
94f6d190 JR |
2229 | domain = get_domain(dev); |
2230 | if (IS_ERR(domain)) | |
5b28df6f JR |
2231 | return; |
2232 | ||
65b050ad JR |
2233 | spin_lock_irqsave(&domain->lock, flags); |
2234 | ||
2235 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2236 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2237 | s->dma_length, dir); |
65b050ad JR |
2238 | s->dma_address = s->dma_length = 0; |
2239 | } | |
2240 | ||
17b124bf | 2241 | domain_flush_complete(domain); |
65b050ad JR |
2242 | |
2243 | spin_unlock_irqrestore(&domain->lock, flags); | |
2244 | } | |
2245 | ||
431b2a20 JR |
2246 | /* |
2247 | * The exported alloc_coherent function for dma_ops. | |
2248 | */ | |
5d8b53cf JR |
2249 | static void *alloc_coherent(struct device *dev, size_t size, |
2250 | dma_addr_t *dma_addr, gfp_t flag) | |
2251 | { | |
2252 | unsigned long flags; | |
2253 | void *virt_addr; | |
5d8b53cf | 2254 | struct protection_domain *domain; |
5d8b53cf | 2255 | phys_addr_t paddr; |
832a90c3 | 2256 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2257 | |
c8f0fb36 JR |
2258 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2259 | ||
94f6d190 JR |
2260 | domain = get_domain(dev); |
2261 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2262 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2263 | *dma_addr = __pa(virt_addr); | |
2264 | return virt_addr; | |
94f6d190 JR |
2265 | } else if (IS_ERR(domain)) |
2266 | return NULL; | |
5d8b53cf | 2267 | |
f99c0f1c JR |
2268 | dma_mask = dev->coherent_dma_mask; |
2269 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2270 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2271 | |
2272 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2273 | if (!virt_addr) | |
b25ae679 | 2274 | return NULL; |
5d8b53cf | 2275 | |
5d8b53cf JR |
2276 | paddr = virt_to_phys(virt_addr); |
2277 | ||
832a90c3 JR |
2278 | if (!dma_mask) |
2279 | dma_mask = *dev->dma_mask; | |
2280 | ||
5d8b53cf JR |
2281 | spin_lock_irqsave(&domain->lock, flags); |
2282 | ||
cd8c82e8 | 2283 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2284 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2285 | |
8fd524b3 | 2286 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2287 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2288 | goto out_free; |
367d04c4 | 2289 | } |
5d8b53cf | 2290 | |
17b124bf | 2291 | domain_flush_complete(domain); |
5d8b53cf | 2292 | |
5d8b53cf JR |
2293 | spin_unlock_irqrestore(&domain->lock, flags); |
2294 | ||
2295 | return virt_addr; | |
5b28df6f JR |
2296 | |
2297 | out_free: | |
2298 | ||
2299 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2300 | ||
2301 | return NULL; | |
5d8b53cf JR |
2302 | } |
2303 | ||
431b2a20 JR |
2304 | /* |
2305 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2306 | */ |
5d8b53cf JR |
2307 | static void free_coherent(struct device *dev, size_t size, |
2308 | void *virt_addr, dma_addr_t dma_addr) | |
2309 | { | |
2310 | unsigned long flags; | |
5d8b53cf | 2311 | struct protection_domain *domain; |
5d8b53cf | 2312 | |
5d31ee7e JR |
2313 | INC_STATS_COUNTER(cnt_free_coherent); |
2314 | ||
94f6d190 JR |
2315 | domain = get_domain(dev); |
2316 | if (IS_ERR(domain)) | |
5b28df6f JR |
2317 | goto free_mem; |
2318 | ||
5d8b53cf JR |
2319 | spin_lock_irqsave(&domain->lock, flags); |
2320 | ||
cd8c82e8 | 2321 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2322 | |
17b124bf | 2323 | domain_flush_complete(domain); |
5d8b53cf JR |
2324 | |
2325 | spin_unlock_irqrestore(&domain->lock, flags); | |
2326 | ||
2327 | free_mem: | |
2328 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2329 | } | |
2330 | ||
b39ba6ad JR |
2331 | /* |
2332 | * This function is called by the DMA layer to find out if we can handle a | |
2333 | * particular device. It is part of the dma_ops. | |
2334 | */ | |
2335 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2336 | { | |
420aef8a | 2337 | return check_device(dev); |
b39ba6ad JR |
2338 | } |
2339 | ||
c432f3df | 2340 | /* |
431b2a20 JR |
2341 | * The function for pre-allocating protection domains. |
2342 | * | |
c432f3df JR |
2343 | * If the driver core informs the DMA layer if a driver grabs a device |
2344 | * we don't need to preallocate the protection domains anymore. | |
2345 | * For now we have to. | |
2346 | */ | |
0e93dd88 | 2347 | static void prealloc_protection_domains(void) |
c432f3df JR |
2348 | { |
2349 | struct pci_dev *dev = NULL; | |
2350 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2351 | u16 devid; |
c432f3df | 2352 | |
d18c69d3 | 2353 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2354 | |
2355 | /* Do we handle this device? */ | |
2356 | if (!check_device(&dev->dev)) | |
c432f3df | 2357 | continue; |
98fc5a69 JR |
2358 | |
2359 | /* Is there already any domain for it? */ | |
15898bbc | 2360 | if (domain_for_device(&dev->dev)) |
c432f3df | 2361 | continue; |
98fc5a69 JR |
2362 | |
2363 | devid = get_device_id(&dev->dev); | |
2364 | ||
87a64d52 | 2365 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2366 | if (!dma_dom) |
2367 | continue; | |
2368 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2369 | dma_dom->target_dev = devid; |
2370 | ||
15898bbc | 2371 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2372 | |
bd60b735 | 2373 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2374 | } |
2375 | } | |
2376 | ||
160c1d8e | 2377 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2378 | .alloc_coherent = alloc_coherent, |
2379 | .free_coherent = free_coherent, | |
51491367 FT |
2380 | .map_page = map_page, |
2381 | .unmap_page = unmap_page, | |
6631ee9d JR |
2382 | .map_sg = map_sg, |
2383 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2384 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2385 | }; |
2386 | ||
27c2127a JR |
2387 | static unsigned device_dma_ops_init(void) |
2388 | { | |
2389 | struct pci_dev *pdev = NULL; | |
2390 | unsigned unhandled = 0; | |
2391 | ||
2392 | for_each_pci_dev(pdev) { | |
2393 | if (!check_device(&pdev->dev)) { | |
2394 | unhandled += 1; | |
2395 | continue; | |
2396 | } | |
2397 | ||
2398 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2399 | } | |
2400 | ||
2401 | return unhandled; | |
2402 | } | |
2403 | ||
431b2a20 JR |
2404 | /* |
2405 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2406 | */ | |
f5325094 JR |
2407 | |
2408 | void __init amd_iommu_init_api(void) | |
2409 | { | |
2410 | register_iommu(&amd_iommu_ops); | |
2411 | } | |
2412 | ||
6631ee9d JR |
2413 | int __init amd_iommu_init_dma_ops(void) |
2414 | { | |
2415 | struct amd_iommu *iommu; | |
27c2127a | 2416 | int ret, unhandled; |
6631ee9d | 2417 | |
431b2a20 JR |
2418 | /* |
2419 | * first allocate a default protection domain for every IOMMU we | |
2420 | * found in the system. Devices not assigned to any other | |
2421 | * protection domain will be assigned to the default one. | |
2422 | */ | |
3bd22172 | 2423 | for_each_iommu(iommu) { |
87a64d52 | 2424 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2425 | if (iommu->default_dom == NULL) |
2426 | return -ENOMEM; | |
e2dc14a2 | 2427 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2428 | ret = iommu_init_unity_mappings(iommu); |
2429 | if (ret) | |
2430 | goto free_domains; | |
2431 | } | |
2432 | ||
431b2a20 | 2433 | /* |
8793abeb | 2434 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2435 | */ |
8793abeb | 2436 | prealloc_protection_domains(); |
6631ee9d JR |
2437 | |
2438 | iommu_detected = 1; | |
75f1cdf1 | 2439 | swiotlb = 0; |
6631ee9d | 2440 | |
431b2a20 | 2441 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2442 | unhandled = device_dma_ops_init(); |
2443 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2444 | /* There are unhandled devices - initialize swiotlb for them */ | |
2445 | swiotlb = 1; | |
2446 | } | |
6631ee9d | 2447 | |
7f26508b JR |
2448 | amd_iommu_stats_init(); |
2449 | ||
6631ee9d JR |
2450 | return 0; |
2451 | ||
2452 | free_domains: | |
2453 | ||
3bd22172 | 2454 | for_each_iommu(iommu) { |
6631ee9d JR |
2455 | if (iommu->default_dom) |
2456 | dma_ops_domain_free(iommu->default_dom); | |
2457 | } | |
2458 | ||
2459 | return ret; | |
2460 | } | |
6d98cd80 JR |
2461 | |
2462 | /***************************************************************************** | |
2463 | * | |
2464 | * The following functions belong to the exported interface of AMD IOMMU | |
2465 | * | |
2466 | * This interface allows access to lower level functions of the IOMMU | |
2467 | * like protection domain handling and assignement of devices to domains | |
2468 | * which is not possible with the dma_ops interface. | |
2469 | * | |
2470 | *****************************************************************************/ | |
2471 | ||
6d98cd80 JR |
2472 | static void cleanup_domain(struct protection_domain *domain) |
2473 | { | |
492667da | 2474 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2475 | unsigned long flags; |
6d98cd80 JR |
2476 | |
2477 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2478 | ||
492667da JR |
2479 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2480 | struct device *dev = dev_data->dev; | |
2481 | ||
04e856c0 | 2482 | __detach_device(dev); |
492667da JR |
2483 | atomic_set(&dev_data->bind, 0); |
2484 | } | |
6d98cd80 JR |
2485 | |
2486 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2487 | } | |
2488 | ||
2650815f JR |
2489 | static void protection_domain_free(struct protection_domain *domain) |
2490 | { | |
2491 | if (!domain) | |
2492 | return; | |
2493 | ||
aeb26f55 JR |
2494 | del_domain_from_list(domain); |
2495 | ||
2650815f JR |
2496 | if (domain->id) |
2497 | domain_id_free(domain->id); | |
2498 | ||
2499 | kfree(domain); | |
2500 | } | |
2501 | ||
2502 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2503 | { |
2504 | struct protection_domain *domain; | |
2505 | ||
2506 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2507 | if (!domain) | |
2650815f | 2508 | return NULL; |
c156e347 JR |
2509 | |
2510 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2511 | mutex_init(&domain->api_lock); |
c156e347 JR |
2512 | domain->id = domain_id_alloc(); |
2513 | if (!domain->id) | |
2650815f | 2514 | goto out_err; |
7c392cbe | 2515 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2516 | |
aeb26f55 JR |
2517 | add_domain_to_list(domain); |
2518 | ||
2650815f JR |
2519 | return domain; |
2520 | ||
2521 | out_err: | |
2522 | kfree(domain); | |
2523 | ||
2524 | return NULL; | |
2525 | } | |
2526 | ||
2527 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2528 | { | |
2529 | struct protection_domain *domain; | |
2530 | ||
2531 | domain = protection_domain_alloc(); | |
2532 | if (!domain) | |
c156e347 | 2533 | goto out_free; |
2650815f JR |
2534 | |
2535 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2536 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2537 | if (!domain->pt_root) | |
2538 | goto out_free; | |
2539 | ||
2540 | dom->priv = domain; | |
2541 | ||
2542 | return 0; | |
2543 | ||
2544 | out_free: | |
2650815f | 2545 | protection_domain_free(domain); |
c156e347 JR |
2546 | |
2547 | return -ENOMEM; | |
2548 | } | |
2549 | ||
98383fc3 JR |
2550 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2551 | { | |
2552 | struct protection_domain *domain = dom->priv; | |
2553 | ||
2554 | if (!domain) | |
2555 | return; | |
2556 | ||
2557 | if (domain->dev_cnt > 0) | |
2558 | cleanup_domain(domain); | |
2559 | ||
2560 | BUG_ON(domain->dev_cnt != 0); | |
2561 | ||
2562 | free_pagetable(domain); | |
2563 | ||
8b408fe4 | 2564 | protection_domain_free(domain); |
98383fc3 JR |
2565 | |
2566 | dom->priv = NULL; | |
2567 | } | |
2568 | ||
684f2888 JR |
2569 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2570 | struct device *dev) | |
2571 | { | |
657cbb6b | 2572 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2573 | struct amd_iommu *iommu; |
684f2888 JR |
2574 | u16 devid; |
2575 | ||
98fc5a69 | 2576 | if (!check_device(dev)) |
684f2888 JR |
2577 | return; |
2578 | ||
98fc5a69 | 2579 | devid = get_device_id(dev); |
684f2888 | 2580 | |
657cbb6b | 2581 | if (dev_data->domain != NULL) |
15898bbc | 2582 | detach_device(dev); |
684f2888 JR |
2583 | |
2584 | iommu = amd_iommu_rlookup_table[devid]; | |
2585 | if (!iommu) | |
2586 | return; | |
2587 | ||
d8c13085 | 2588 | device_flush_dte(dev); |
684f2888 JR |
2589 | iommu_completion_wait(iommu); |
2590 | } | |
2591 | ||
01106066 JR |
2592 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2593 | struct device *dev) | |
2594 | { | |
2595 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2596 | struct iommu_dev_data *dev_data; |
01106066 | 2597 | struct amd_iommu *iommu; |
15898bbc | 2598 | int ret; |
01106066 JR |
2599 | u16 devid; |
2600 | ||
98fc5a69 | 2601 | if (!check_device(dev)) |
01106066 JR |
2602 | return -EINVAL; |
2603 | ||
657cbb6b JR |
2604 | dev_data = dev->archdata.iommu; |
2605 | ||
98fc5a69 | 2606 | devid = get_device_id(dev); |
01106066 JR |
2607 | |
2608 | iommu = amd_iommu_rlookup_table[devid]; | |
2609 | if (!iommu) | |
2610 | return -EINVAL; | |
2611 | ||
657cbb6b | 2612 | if (dev_data->domain) |
15898bbc | 2613 | detach_device(dev); |
01106066 | 2614 | |
15898bbc | 2615 | ret = attach_device(dev, domain); |
01106066 JR |
2616 | |
2617 | iommu_completion_wait(iommu); | |
2618 | ||
15898bbc | 2619 | return ret; |
01106066 JR |
2620 | } |
2621 | ||
468e2366 JR |
2622 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2623 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2624 | { |
468e2366 | 2625 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2626 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2627 | int prot = 0; |
2628 | int ret; | |
2629 | ||
2630 | if (iommu_prot & IOMMU_READ) | |
2631 | prot |= IOMMU_PROT_IR; | |
2632 | if (iommu_prot & IOMMU_WRITE) | |
2633 | prot |= IOMMU_PROT_IW; | |
2634 | ||
5d214fe6 | 2635 | mutex_lock(&domain->api_lock); |
795e74f7 | 2636 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2637 | mutex_unlock(&domain->api_lock); |
2638 | ||
795e74f7 | 2639 | return ret; |
c6229ca6 JR |
2640 | } |
2641 | ||
468e2366 JR |
2642 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2643 | int gfp_order) | |
eb74ff6c | 2644 | { |
eb74ff6c | 2645 | struct protection_domain *domain = dom->priv; |
468e2366 | 2646 | unsigned long page_size, unmap_size; |
eb74ff6c | 2647 | |
468e2366 | 2648 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2649 | |
5d214fe6 | 2650 | mutex_lock(&domain->api_lock); |
468e2366 | 2651 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2652 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2653 | |
17b124bf | 2654 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2655 | |
468e2366 | 2656 | return get_order(unmap_size); |
eb74ff6c JR |
2657 | } |
2658 | ||
645c4c8d JR |
2659 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2660 | unsigned long iova) | |
2661 | { | |
2662 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2663 | unsigned long offset_mask; |
645c4c8d | 2664 | phys_addr_t paddr; |
f03152bb | 2665 | u64 *pte, __pte; |
645c4c8d | 2666 | |
24cd7723 | 2667 | pte = fetch_pte(domain, iova); |
645c4c8d | 2668 | |
a6d41a40 | 2669 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2670 | return 0; |
2671 | ||
f03152bb JR |
2672 | if (PM_PTE_LEVEL(*pte) == 0) |
2673 | offset_mask = PAGE_SIZE - 1; | |
2674 | else | |
2675 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2676 | ||
2677 | __pte = *pte & PM_ADDR_MASK; | |
2678 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2679 | |
2680 | return paddr; | |
2681 | } | |
2682 | ||
dbb9fd86 SY |
2683 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2684 | unsigned long cap) | |
2685 | { | |
80a506b8 JR |
2686 | switch (cap) { |
2687 | case IOMMU_CAP_CACHE_COHERENCY: | |
2688 | return 1; | |
2689 | } | |
2690 | ||
dbb9fd86 SY |
2691 | return 0; |
2692 | } | |
2693 | ||
26961efe JR |
2694 | static struct iommu_ops amd_iommu_ops = { |
2695 | .domain_init = amd_iommu_domain_init, | |
2696 | .domain_destroy = amd_iommu_domain_destroy, | |
2697 | .attach_dev = amd_iommu_attach_device, | |
2698 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2699 | .map = amd_iommu_map, |
2700 | .unmap = amd_iommu_unmap, | |
26961efe | 2701 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2702 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2703 | }; |
2704 | ||
0feae533 JR |
2705 | /***************************************************************************** |
2706 | * | |
2707 | * The next functions do a basic initialization of IOMMU for pass through | |
2708 | * mode | |
2709 | * | |
2710 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2711 | * DMA-API translation. | |
2712 | * | |
2713 | *****************************************************************************/ | |
2714 | ||
2715 | int __init amd_iommu_init_passthrough(void) | |
2716 | { | |
15898bbc | 2717 | struct amd_iommu *iommu; |
0feae533 | 2718 | struct pci_dev *dev = NULL; |
15898bbc | 2719 | u16 devid; |
0feae533 | 2720 | |
af901ca1 | 2721 | /* allocate passthrough domain */ |
0feae533 JR |
2722 | pt_domain = protection_domain_alloc(); |
2723 | if (!pt_domain) | |
2724 | return -ENOMEM; | |
2725 | ||
2726 | pt_domain->mode |= PAGE_MODE_NONE; | |
2727 | ||
6c54aabd | 2728 | for_each_pci_dev(dev) { |
98fc5a69 | 2729 | if (!check_device(&dev->dev)) |
0feae533 JR |
2730 | continue; |
2731 | ||
98fc5a69 JR |
2732 | devid = get_device_id(&dev->dev); |
2733 | ||
15898bbc | 2734 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2735 | if (!iommu) |
2736 | continue; | |
2737 | ||
15898bbc | 2738 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2739 | } |
2740 | ||
2741 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2742 | ||
2743 | return 0; | |
2744 | } |