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Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
9355a081 JR |
64 | static u64 *fetch_pte(struct protection_domain *domain, |
65 | unsigned long address); | |
bd0e5211 | 66 | |
c1eee67b CW |
67 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
68 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
69 | #endif | |
70 | ||
7f26508b JR |
71 | #ifdef CONFIG_AMD_IOMMU_STATS |
72 | ||
73 | /* | |
74 | * Initialization code for statistics collection | |
75 | */ | |
76 | ||
da49f6df | 77 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 78 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 79 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 80 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 81 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 82 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 83 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 84 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 85 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 86 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 87 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 88 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 89 | |
7f26508b JR |
90 | static struct dentry *stats_dir; |
91 | static struct dentry *de_isolate; | |
92 | static struct dentry *de_fflush; | |
93 | ||
94 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
95 | { | |
96 | if (stats_dir == NULL) | |
97 | return; | |
98 | ||
99 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
100 | &cnt->value); | |
101 | } | |
102 | ||
103 | static void amd_iommu_stats_init(void) | |
104 | { | |
105 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
106 | if (stats_dir == NULL) | |
107 | return; | |
108 | ||
109 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
110 | (u32 *)&amd_iommu_isolate); | |
111 | ||
112 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
113 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
114 | |
115 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 116 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 117 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 118 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 119 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 120 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 121 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 122 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 123 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 124 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 125 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 126 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
127 | } |
128 | ||
129 | #endif | |
130 | ||
431b2a20 | 131 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
132 | static int iommu_has_npcache(struct amd_iommu *iommu) |
133 | { | |
ae9b9403 | 134 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
135 | } |
136 | ||
a80dc3e0 JR |
137 | /**************************************************************************** |
138 | * | |
139 | * Interrupt handling functions | |
140 | * | |
141 | ****************************************************************************/ | |
142 | ||
90008ee4 JR |
143 | static void iommu_print_event(void *__evt) |
144 | { | |
145 | u32 *event = __evt; | |
146 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
147 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
148 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
149 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
150 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
151 | ||
152 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
153 | ||
154 | switch (type) { | |
155 | case EVENT_TYPE_ILL_DEV: | |
156 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
157 | "address=0x%016llx flags=0x%04x]\n", | |
158 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
159 | address, flags); | |
160 | break; | |
161 | case EVENT_TYPE_IO_FAULT: | |
162 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
163 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
164 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
165 | domid, address, flags); | |
166 | break; | |
167 | case EVENT_TYPE_DEV_TAB_ERR: | |
168 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
169 | "address=0x%016llx flags=0x%04x]\n", | |
170 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
171 | address, flags); | |
172 | break; | |
173 | case EVENT_TYPE_PAGE_TAB_ERR: | |
174 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
175 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
176 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
177 | domid, address, flags); | |
178 | break; | |
179 | case EVENT_TYPE_ILL_CMD: | |
180 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
181 | break; | |
182 | case EVENT_TYPE_CMD_HARD_ERR: | |
183 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
184 | "flags=0x%04x]\n", address, flags); | |
185 | break; | |
186 | case EVENT_TYPE_IOTLB_INV_TO: | |
187 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
188 | "address=0x%016llx]\n", | |
189 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
190 | address); | |
191 | break; | |
192 | case EVENT_TYPE_INV_DEV_REQ: | |
193 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
194 | "address=0x%016llx flags=0x%04x]\n", | |
195 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
196 | address, flags); | |
197 | break; | |
198 | default: | |
199 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
200 | } | |
201 | } | |
202 | ||
203 | static void iommu_poll_events(struct amd_iommu *iommu) | |
204 | { | |
205 | u32 head, tail; | |
206 | unsigned long flags; | |
207 | ||
208 | spin_lock_irqsave(&iommu->lock, flags); | |
209 | ||
210 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
211 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
212 | ||
213 | while (head != tail) { | |
214 | iommu_print_event(iommu->evt_buf + head); | |
215 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
216 | } | |
217 | ||
218 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
219 | ||
220 | spin_unlock_irqrestore(&iommu->lock, flags); | |
221 | } | |
222 | ||
a80dc3e0 JR |
223 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
224 | { | |
90008ee4 JR |
225 | struct amd_iommu *iommu; |
226 | ||
3bd22172 | 227 | for_each_iommu(iommu) |
90008ee4 JR |
228 | iommu_poll_events(iommu); |
229 | ||
230 | return IRQ_HANDLED; | |
a80dc3e0 JR |
231 | } |
232 | ||
431b2a20 JR |
233 | /**************************************************************************** |
234 | * | |
235 | * IOMMU command queuing functions | |
236 | * | |
237 | ****************************************************************************/ | |
238 | ||
239 | /* | |
240 | * Writes the command to the IOMMUs command buffer and informs the | |
241 | * hardware about the new command. Must be called with iommu->lock held. | |
242 | */ | |
d6449536 | 243 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
244 | { |
245 | u32 tail, head; | |
246 | u8 *target; | |
247 | ||
248 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 249 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
250 | memcpy_toio(target, cmd, sizeof(*cmd)); |
251 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
252 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
253 | if (tail == head) | |
254 | return -ENOMEM; | |
255 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
431b2a20 JR |
260 | /* |
261 | * General queuing function for commands. Takes iommu->lock and calls | |
262 | * __iommu_queue_command(). | |
263 | */ | |
d6449536 | 264 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
265 | { |
266 | unsigned long flags; | |
267 | int ret; | |
268 | ||
269 | spin_lock_irqsave(&iommu->lock, flags); | |
270 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 271 | if (!ret) |
0cfd7aa9 | 272 | iommu->need_sync = true; |
a19ae1ec JR |
273 | spin_unlock_irqrestore(&iommu->lock, flags); |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
8d201968 JR |
278 | /* |
279 | * This function waits until an IOMMU has completed a completion | |
280 | * wait command | |
281 | */ | |
282 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
283 | { | |
284 | int ready = 0; | |
285 | unsigned status = 0; | |
286 | unsigned long i = 0; | |
287 | ||
da49f6df JR |
288 | INC_STATS_COUNTER(compl_wait); |
289 | ||
8d201968 JR |
290 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
291 | ++i; | |
292 | /* wait for the bit to become one */ | |
293 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
294 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
295 | } | |
296 | ||
297 | /* set bit back to zero */ | |
298 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
299 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
300 | ||
301 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
302 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
303 | } | |
304 | ||
305 | /* | |
306 | * This function queues a completion wait command into the command | |
307 | * buffer of an IOMMU | |
308 | */ | |
309 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
310 | { | |
311 | struct iommu_cmd cmd; | |
312 | ||
313 | memset(&cmd, 0, sizeof(cmd)); | |
314 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
315 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
316 | ||
317 | return __iommu_queue_command(iommu, &cmd); | |
318 | } | |
319 | ||
431b2a20 JR |
320 | /* |
321 | * This function is called whenever we need to ensure that the IOMMU has | |
322 | * completed execution of all commands we sent. It sends a | |
323 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
324 | * us about that by writing a value to a physical address we pass with | |
325 | * the command. | |
326 | */ | |
a19ae1ec JR |
327 | static int iommu_completion_wait(struct amd_iommu *iommu) |
328 | { | |
8d201968 JR |
329 | int ret = 0; |
330 | unsigned long flags; | |
a19ae1ec | 331 | |
7e4f88da JR |
332 | spin_lock_irqsave(&iommu->lock, flags); |
333 | ||
09ee17eb JR |
334 | if (!iommu->need_sync) |
335 | goto out; | |
336 | ||
8d201968 | 337 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 338 | |
0cfd7aa9 | 339 | iommu->need_sync = false; |
a19ae1ec JR |
340 | |
341 | if (ret) | |
7e4f88da | 342 | goto out; |
a19ae1ec | 343 | |
8d201968 | 344 | __iommu_wait_for_completion(iommu); |
84df8175 | 345 | |
7e4f88da JR |
346 | out: |
347 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
348 | |
349 | return 0; | |
350 | } | |
351 | ||
431b2a20 JR |
352 | /* |
353 | * Command send function for invalidating a device table entry | |
354 | */ | |
a19ae1ec JR |
355 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
356 | { | |
d6449536 | 357 | struct iommu_cmd cmd; |
ee2fa743 | 358 | int ret; |
a19ae1ec JR |
359 | |
360 | BUG_ON(iommu == NULL); | |
361 | ||
362 | memset(&cmd, 0, sizeof(cmd)); | |
363 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
364 | cmd.data[0] = devid; | |
365 | ||
ee2fa743 JR |
366 | ret = iommu_queue_command(iommu, &cmd); |
367 | ||
ee2fa743 | 368 | return ret; |
a19ae1ec JR |
369 | } |
370 | ||
237b6f33 JR |
371 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
372 | u16 domid, int pde, int s) | |
373 | { | |
374 | memset(cmd, 0, sizeof(*cmd)); | |
375 | address &= PAGE_MASK; | |
376 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
377 | cmd->data[1] |= domid; | |
378 | cmd->data[2] = lower_32_bits(address); | |
379 | cmd->data[3] = upper_32_bits(address); | |
380 | if (s) /* size bit - we flush more than one 4kb page */ | |
381 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
382 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
383 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
384 | } | |
385 | ||
431b2a20 JR |
386 | /* |
387 | * Generic command send function for invalidaing TLB entries | |
388 | */ | |
a19ae1ec JR |
389 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
390 | u64 address, u16 domid, int pde, int s) | |
391 | { | |
d6449536 | 392 | struct iommu_cmd cmd; |
ee2fa743 | 393 | int ret; |
a19ae1ec | 394 | |
237b6f33 | 395 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 396 | |
ee2fa743 JR |
397 | ret = iommu_queue_command(iommu, &cmd); |
398 | ||
ee2fa743 | 399 | return ret; |
a19ae1ec JR |
400 | } |
401 | ||
431b2a20 JR |
402 | /* |
403 | * TLB invalidation function which is called from the mapping functions. | |
404 | * It invalidates a single PTE if the range to flush is within a single | |
405 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
406 | */ | |
a19ae1ec JR |
407 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
408 | u64 address, size_t size) | |
409 | { | |
999ba417 | 410 | int s = 0; |
e3c449f5 | 411 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
412 | |
413 | address &= PAGE_MASK; | |
414 | ||
999ba417 JR |
415 | if (pages > 1) { |
416 | /* | |
417 | * If we have to flush more than one page, flush all | |
418 | * TLB entries for this domain | |
419 | */ | |
420 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
421 | s = 1; | |
a19ae1ec JR |
422 | } |
423 | ||
999ba417 JR |
424 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
425 | ||
a19ae1ec JR |
426 | return 0; |
427 | } | |
b6c02715 | 428 | |
1c655773 JR |
429 | /* Flush the whole IO/TLB for a given protection domain */ |
430 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
431 | { | |
432 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
433 | ||
f57d98ae JR |
434 | INC_STATS_COUNTER(domain_flush_single); |
435 | ||
1c655773 JR |
436 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
437 | } | |
438 | ||
42a49f96 CW |
439 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
440 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
441 | { | |
442 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
443 | ||
444 | INC_STATS_COUNTER(domain_flush_single); | |
445 | ||
446 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
447 | } | |
448 | ||
43f49609 JR |
449 | /* |
450 | * This function is used to flush the IO/TLB for a given protection domain | |
451 | * on every IOMMU in the system | |
452 | */ | |
453 | static void iommu_flush_domain(u16 domid) | |
454 | { | |
455 | unsigned long flags; | |
456 | struct amd_iommu *iommu; | |
457 | struct iommu_cmd cmd; | |
458 | ||
18811f55 JR |
459 | INC_STATS_COUNTER(domain_flush_all); |
460 | ||
43f49609 JR |
461 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
462 | domid, 1, 1); | |
463 | ||
3bd22172 | 464 | for_each_iommu(iommu) { |
43f49609 JR |
465 | spin_lock_irqsave(&iommu->lock, flags); |
466 | __iommu_queue_command(iommu, &cmd); | |
467 | __iommu_completion_wait(iommu); | |
468 | __iommu_wait_for_completion(iommu); | |
469 | spin_unlock_irqrestore(&iommu->lock, flags); | |
470 | } | |
471 | } | |
43f49609 | 472 | |
bfd1be18 JR |
473 | void amd_iommu_flush_all_domains(void) |
474 | { | |
475 | int i; | |
476 | ||
477 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
478 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
479 | continue; | |
480 | iommu_flush_domain(i); | |
481 | } | |
482 | } | |
483 | ||
7d7a110c JR |
484 | void amd_iommu_flush_all_devices(void) |
485 | { | |
486 | struct amd_iommu *iommu; | |
487 | int i; | |
488 | ||
489 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
490 | if (amd_iommu_pd_table[i] == NULL) | |
491 | continue; | |
492 | ||
493 | iommu = amd_iommu_rlookup_table[i]; | |
494 | if (!iommu) | |
495 | continue; | |
496 | ||
497 | iommu_queue_inv_dev_entry(iommu, i); | |
498 | iommu_completion_wait(iommu); | |
499 | } | |
500 | } | |
501 | ||
431b2a20 JR |
502 | /**************************************************************************** |
503 | * | |
504 | * The functions below are used the create the page table mappings for | |
505 | * unity mapped regions. | |
506 | * | |
507 | ****************************************************************************/ | |
508 | ||
509 | /* | |
510 | * Generic mapping functions. It maps a physical address into a DMA | |
511 | * address space. It allocates the page table pages if necessary. | |
512 | * In the future it can be extended to a generic mapping function | |
513 | * supporting all features of AMD IOMMU page tables like level skipping | |
514 | * and full 64 bit address spaces. | |
515 | */ | |
38e817fe JR |
516 | static int iommu_map_page(struct protection_domain *dom, |
517 | unsigned long bus_addr, | |
518 | unsigned long phys_addr, | |
519 | int prot) | |
bd0e5211 | 520 | { |
8bda3092 | 521 | u64 __pte, *pte; |
bd0e5211 JR |
522 | |
523 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 524 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
525 | |
526 | /* only support 512GB address spaces for now */ | |
527 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
528 | return -EINVAL; | |
529 | ||
8bda3092 | 530 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
531 | |
532 | if (IOMMU_PTE_PRESENT(*pte)) | |
533 | return -EBUSY; | |
534 | ||
535 | __pte = phys_addr | IOMMU_PTE_P; | |
536 | if (prot & IOMMU_PROT_IR) | |
537 | __pte |= IOMMU_PTE_IR; | |
538 | if (prot & IOMMU_PROT_IW) | |
539 | __pte |= IOMMU_PTE_IW; | |
540 | ||
541 | *pte = __pte; | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
eb74ff6c JR |
546 | static void iommu_unmap_page(struct protection_domain *dom, |
547 | unsigned long bus_addr) | |
548 | { | |
38a76eee | 549 | u64 *pte = fetch_pte(dom, bus_addr); |
eb74ff6c | 550 | |
38a76eee JR |
551 | if (pte) |
552 | *pte = 0; | |
eb74ff6c | 553 | } |
eb74ff6c | 554 | |
431b2a20 JR |
555 | /* |
556 | * This function checks if a specific unity mapping entry is needed for | |
557 | * this specific IOMMU. | |
558 | */ | |
bd0e5211 JR |
559 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
560 | struct unity_map_entry *entry) | |
561 | { | |
562 | u16 bdf, i; | |
563 | ||
564 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
565 | bdf = amd_iommu_alias_table[i]; | |
566 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
567 | return 1; | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
431b2a20 JR |
573 | /* |
574 | * Init the unity mappings for a specific IOMMU in the system | |
575 | * | |
576 | * Basically iterates over all unity mapping entries and applies them to | |
577 | * the default domain DMA of that IOMMU if necessary. | |
578 | */ | |
bd0e5211 JR |
579 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
580 | { | |
581 | struct unity_map_entry *entry; | |
582 | int ret; | |
583 | ||
584 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
585 | if (!iommu_for_unity_map(iommu, entry)) | |
586 | continue; | |
587 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
588 | if (ret) | |
589 | return ret; | |
590 | } | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
431b2a20 JR |
595 | /* |
596 | * This function actually applies the mapping to the page table of the | |
597 | * dma_ops domain. | |
598 | */ | |
bd0e5211 JR |
599 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
600 | struct unity_map_entry *e) | |
601 | { | |
602 | u64 addr; | |
603 | int ret; | |
604 | ||
605 | for (addr = e->address_start; addr < e->address_end; | |
606 | addr += PAGE_SIZE) { | |
38e817fe | 607 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
608 | if (ret) |
609 | return ret; | |
610 | /* | |
611 | * if unity mapping is in aperture range mark the page | |
612 | * as allocated in the aperture | |
613 | */ | |
614 | if (addr < dma_dom->aperture_size) | |
c3239567 | 615 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 616 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
617 | } |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
431b2a20 JR |
622 | /* |
623 | * Inits the unity mappings required for a specific device | |
624 | */ | |
bd0e5211 JR |
625 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
626 | u16 devid) | |
627 | { | |
628 | struct unity_map_entry *e; | |
629 | int ret; | |
630 | ||
631 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
632 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
633 | continue; | |
634 | ret = dma_ops_unity_map(dma_dom, e); | |
635 | if (ret) | |
636 | return ret; | |
637 | } | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
431b2a20 JR |
642 | /**************************************************************************** |
643 | * | |
644 | * The next functions belong to the address allocator for the dma_ops | |
645 | * interface functions. They work like the allocators in the other IOMMU | |
646 | * drivers. Its basically a bitmap which marks the allocated pages in | |
647 | * the aperture. Maybe it could be enhanced in the future to a more | |
648 | * efficient allocator. | |
649 | * | |
650 | ****************************************************************************/ | |
d3086444 | 651 | |
431b2a20 | 652 | /* |
384de729 | 653 | * The address allocator core functions. |
431b2a20 JR |
654 | * |
655 | * called with domain->lock held | |
656 | */ | |
384de729 | 657 | |
00cd122a JR |
658 | /* |
659 | * This function checks if there is a PTE for a given dma address. If | |
660 | * there is one, it returns the pointer to it. | |
661 | */ | |
9355a081 | 662 | static u64 *fetch_pte(struct protection_domain *domain, |
00cd122a JR |
663 | unsigned long address) |
664 | { | |
9355a081 | 665 | int level; |
00cd122a JR |
666 | u64 *pte; |
667 | ||
9355a081 JR |
668 | level = domain->mode - 1; |
669 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 670 | |
9355a081 JR |
671 | while (level > 0) { |
672 | if (!IOMMU_PTE_PRESENT(*pte)) | |
673 | return NULL; | |
00cd122a | 674 | |
9355a081 | 675 | level -= 1; |
00cd122a | 676 | |
9355a081 JR |
677 | pte = IOMMU_PTE_PAGE(*pte); |
678 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
679 | } | |
00cd122a JR |
680 | |
681 | return pte; | |
682 | } | |
683 | ||
9cabe89b JR |
684 | /* |
685 | * This function is used to add a new aperture range to an existing | |
686 | * aperture in case of dma_ops domain allocation or address allocation | |
687 | * failure. | |
688 | */ | |
00cd122a JR |
689 | static int alloc_new_range(struct amd_iommu *iommu, |
690 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
691 | bool populate, gfp_t gfp) |
692 | { | |
693 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 694 | int i; |
9cabe89b | 695 | |
f5e9705c JR |
696 | #ifdef CONFIG_IOMMU_STRESS |
697 | populate = false; | |
698 | #endif | |
699 | ||
9cabe89b JR |
700 | if (index >= APERTURE_MAX_RANGES) |
701 | return -ENOMEM; | |
702 | ||
703 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
704 | if (!dma_dom->aperture[index]) | |
705 | return -ENOMEM; | |
706 | ||
707 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
708 | if (!dma_dom->aperture[index]->bitmap) | |
709 | goto out_free; | |
710 | ||
711 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
712 | ||
713 | if (populate) { | |
714 | unsigned long address = dma_dom->aperture_size; | |
715 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
716 | u64 *pte, *pte_page; | |
717 | ||
718 | for (i = 0; i < num_ptes; ++i) { | |
719 | pte = alloc_pte(&dma_dom->domain, address, | |
720 | &pte_page, gfp); | |
721 | if (!pte) | |
722 | goto out_free; | |
723 | ||
724 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
725 | ||
726 | address += APERTURE_RANGE_SIZE / 64; | |
727 | } | |
728 | } | |
729 | ||
730 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
731 | ||
00cd122a JR |
732 | /* Intialize the exclusion range if necessary */ |
733 | if (iommu->exclusion_start && | |
734 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
735 | iommu->exclusion_start < dma_dom->aperture_size) { | |
736 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
737 | int pages = iommu_num_pages(iommu->exclusion_start, | |
738 | iommu->exclusion_length, | |
739 | PAGE_SIZE); | |
740 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
741 | } | |
742 | ||
743 | /* | |
744 | * Check for areas already mapped as present in the new aperture | |
745 | * range and mark those pages as reserved in the allocator. Such | |
746 | * mappings may already exist as a result of requested unity | |
747 | * mappings for devices. | |
748 | */ | |
749 | for (i = dma_dom->aperture[index]->offset; | |
750 | i < dma_dom->aperture_size; | |
751 | i += PAGE_SIZE) { | |
752 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
753 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
754 | continue; | |
755 | ||
756 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
757 | } | |
758 | ||
9cabe89b JR |
759 | return 0; |
760 | ||
761 | out_free: | |
762 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
763 | ||
764 | kfree(dma_dom->aperture[index]); | |
765 | dma_dom->aperture[index] = NULL; | |
766 | ||
767 | return -ENOMEM; | |
768 | } | |
769 | ||
384de729 JR |
770 | static unsigned long dma_ops_area_alloc(struct device *dev, |
771 | struct dma_ops_domain *dom, | |
772 | unsigned int pages, | |
773 | unsigned long align_mask, | |
774 | u64 dma_mask, | |
775 | unsigned long start) | |
776 | { | |
803b8cb4 | 777 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
778 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
779 | int i = start >> APERTURE_RANGE_SHIFT; | |
780 | unsigned long boundary_size; | |
781 | unsigned long address = -1; | |
782 | unsigned long limit; | |
783 | ||
803b8cb4 JR |
784 | next_bit >>= PAGE_SHIFT; |
785 | ||
384de729 JR |
786 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
787 | PAGE_SIZE) >> PAGE_SHIFT; | |
788 | ||
789 | for (;i < max_index; ++i) { | |
790 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
791 | ||
792 | if (dom->aperture[i]->offset >= dma_mask) | |
793 | break; | |
794 | ||
795 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
796 | dma_mask >> PAGE_SHIFT); | |
797 | ||
798 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
799 | limit, next_bit, pages, 0, | |
800 | boundary_size, align_mask); | |
801 | if (address != -1) { | |
802 | address = dom->aperture[i]->offset + | |
803 | (address << PAGE_SHIFT); | |
803b8cb4 | 804 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
805 | break; |
806 | } | |
807 | ||
808 | next_bit = 0; | |
809 | } | |
810 | ||
811 | return address; | |
812 | } | |
813 | ||
d3086444 JR |
814 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
815 | struct dma_ops_domain *dom, | |
6d4f343f | 816 | unsigned int pages, |
832a90c3 JR |
817 | unsigned long align_mask, |
818 | u64 dma_mask) | |
d3086444 | 819 | { |
d3086444 | 820 | unsigned long address; |
d3086444 | 821 | |
fe16f088 JR |
822 | #ifdef CONFIG_IOMMU_STRESS |
823 | dom->next_address = 0; | |
824 | dom->need_flush = true; | |
825 | #endif | |
d3086444 | 826 | |
384de729 | 827 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 828 | dma_mask, dom->next_address); |
d3086444 | 829 | |
1c655773 | 830 | if (address == -1) { |
803b8cb4 | 831 | dom->next_address = 0; |
384de729 JR |
832 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
833 | dma_mask, 0); | |
1c655773 JR |
834 | dom->need_flush = true; |
835 | } | |
d3086444 | 836 | |
384de729 | 837 | if (unlikely(address == -1)) |
d3086444 JR |
838 | address = bad_dma_address; |
839 | ||
840 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
841 | ||
842 | return address; | |
843 | } | |
844 | ||
431b2a20 JR |
845 | /* |
846 | * The address free function. | |
847 | * | |
848 | * called with domain->lock held | |
849 | */ | |
d3086444 JR |
850 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
851 | unsigned long address, | |
852 | unsigned int pages) | |
853 | { | |
384de729 JR |
854 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
855 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 856 | |
384de729 JR |
857 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
858 | ||
47bccd6b JR |
859 | #ifdef CONFIG_IOMMU_STRESS |
860 | if (i < 4) | |
861 | return; | |
862 | #endif | |
80be308d | 863 | |
803b8cb4 | 864 | if (address >= dom->next_address) |
80be308d | 865 | dom->need_flush = true; |
384de729 JR |
866 | |
867 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 868 | |
384de729 JR |
869 | iommu_area_free(range->bitmap, address, pages); |
870 | ||
d3086444 JR |
871 | } |
872 | ||
431b2a20 JR |
873 | /**************************************************************************** |
874 | * | |
875 | * The next functions belong to the domain allocation. A domain is | |
876 | * allocated for every IOMMU as the default domain. If device isolation | |
877 | * is enabled, every device get its own domain. The most important thing | |
878 | * about domains is the page table mapping the DMA address space they | |
879 | * contain. | |
880 | * | |
881 | ****************************************************************************/ | |
882 | ||
ec487d1a JR |
883 | static u16 domain_id_alloc(void) |
884 | { | |
885 | unsigned long flags; | |
886 | int id; | |
887 | ||
888 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
889 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
890 | BUG_ON(id == 0); | |
891 | if (id > 0 && id < MAX_DOMAIN_ID) | |
892 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
893 | else | |
894 | id = 0; | |
895 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
896 | ||
897 | return id; | |
898 | } | |
899 | ||
a2acfb75 JR |
900 | static void domain_id_free(int id) |
901 | { | |
902 | unsigned long flags; | |
903 | ||
904 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
905 | if (id > 0 && id < MAX_DOMAIN_ID) | |
906 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
907 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
908 | } | |
a2acfb75 | 909 | |
431b2a20 JR |
910 | /* |
911 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
912 | * ranges. | |
913 | */ | |
ec487d1a JR |
914 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
915 | unsigned long start_page, | |
916 | unsigned int pages) | |
917 | { | |
384de729 | 918 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
919 | |
920 | if (start_page + pages > last_page) | |
921 | pages = last_page - start_page; | |
922 | ||
384de729 JR |
923 | for (i = start_page; i < start_page + pages; ++i) { |
924 | int index = i / APERTURE_RANGE_PAGES; | |
925 | int page = i % APERTURE_RANGE_PAGES; | |
926 | __set_bit(page, dom->aperture[index]->bitmap); | |
927 | } | |
ec487d1a JR |
928 | } |
929 | ||
86db2e5d | 930 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
931 | { |
932 | int i, j; | |
933 | u64 *p1, *p2, *p3; | |
934 | ||
86db2e5d | 935 | p1 = domain->pt_root; |
ec487d1a JR |
936 | |
937 | if (!p1) | |
938 | return; | |
939 | ||
940 | for (i = 0; i < 512; ++i) { | |
941 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
942 | continue; | |
943 | ||
944 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 945 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
946 | if (!IOMMU_PTE_PRESENT(p2[j])) |
947 | continue; | |
948 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
949 | free_page((unsigned long)p3); | |
950 | } | |
951 | ||
952 | free_page((unsigned long)p2); | |
953 | } | |
954 | ||
955 | free_page((unsigned long)p1); | |
86db2e5d JR |
956 | |
957 | domain->pt_root = NULL; | |
ec487d1a JR |
958 | } |
959 | ||
431b2a20 JR |
960 | /* |
961 | * Free a domain, only used if something went wrong in the | |
962 | * allocation path and we need to free an already allocated page table | |
963 | */ | |
ec487d1a JR |
964 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
965 | { | |
384de729 JR |
966 | int i; |
967 | ||
ec487d1a JR |
968 | if (!dom) |
969 | return; | |
970 | ||
86db2e5d | 971 | free_pagetable(&dom->domain); |
ec487d1a | 972 | |
384de729 JR |
973 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
974 | if (!dom->aperture[i]) | |
975 | continue; | |
976 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
977 | kfree(dom->aperture[i]); | |
978 | } | |
ec487d1a JR |
979 | |
980 | kfree(dom); | |
981 | } | |
982 | ||
431b2a20 JR |
983 | /* |
984 | * Allocates a new protection domain usable for the dma_ops functions. | |
985 | * It also intializes the page table and the address allocator data | |
986 | * structures required for the dma_ops interface | |
987 | */ | |
d9cfed92 | 988 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
989 | { |
990 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
991 | |
992 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
993 | if (!dma_dom) | |
994 | return NULL; | |
995 | ||
996 | spin_lock_init(&dma_dom->domain.lock); | |
997 | ||
998 | dma_dom->domain.id = domain_id_alloc(); | |
999 | if (dma_dom->domain.id == 0) | |
1000 | goto free_dma_dom; | |
1001 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1002 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1003 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1004 | dma_dom->domain.priv = dma_dom; |
1005 | if (!dma_dom->domain.pt_root) | |
1006 | goto free_dma_dom; | |
ec487d1a | 1007 | |
1c655773 | 1008 | dma_dom->need_flush = false; |
bd60b735 | 1009 | dma_dom->target_dev = 0xffff; |
1c655773 | 1010 | |
00cd122a | 1011 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1012 | goto free_dma_dom; |
ec487d1a | 1013 | |
431b2a20 | 1014 | /* |
ec487d1a JR |
1015 | * mark the first page as allocated so we never return 0 as |
1016 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1017 | */ |
384de729 | 1018 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1019 | dma_dom->next_address = 0; |
ec487d1a | 1020 | |
ec487d1a JR |
1021 | |
1022 | return dma_dom; | |
1023 | ||
1024 | free_dma_dom: | |
1025 | dma_ops_domain_free(dma_dom); | |
1026 | ||
1027 | return NULL; | |
1028 | } | |
1029 | ||
5b28df6f JR |
1030 | /* |
1031 | * little helper function to check whether a given protection domain is a | |
1032 | * dma_ops domain | |
1033 | */ | |
1034 | static bool dma_ops_domain(struct protection_domain *domain) | |
1035 | { | |
1036 | return domain->flags & PD_DMA_OPS_MASK; | |
1037 | } | |
1038 | ||
431b2a20 JR |
1039 | /* |
1040 | * Find out the protection domain structure for a given PCI device. This | |
1041 | * will give us the pointer to the page table root for example. | |
1042 | */ | |
b20ac0d4 JR |
1043 | static struct protection_domain *domain_for_device(u16 devid) |
1044 | { | |
1045 | struct protection_domain *dom; | |
1046 | unsigned long flags; | |
1047 | ||
1048 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1049 | dom = amd_iommu_pd_table[devid]; | |
1050 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1051 | ||
1052 | return dom; | |
1053 | } | |
1054 | ||
431b2a20 JR |
1055 | /* |
1056 | * If a device is not yet associated with a domain, this function does | |
1057 | * assigns it visible for the hardware | |
1058 | */ | |
f1179dc0 JR |
1059 | static void attach_device(struct amd_iommu *iommu, |
1060 | struct protection_domain *domain, | |
1061 | u16 devid) | |
b20ac0d4 JR |
1062 | { |
1063 | unsigned long flags; | |
b20ac0d4 JR |
1064 | u64 pte_root = virt_to_phys(domain->pt_root); |
1065 | ||
863c74eb JR |
1066 | domain->dev_cnt += 1; |
1067 | ||
38ddf41b JR |
1068 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1069 | << DEV_ENTRY_MODE_SHIFT; | |
1070 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1071 | |
1072 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1073 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1074 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1075 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1076 | ||
1077 | amd_iommu_pd_table[devid] = domain; | |
1078 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1079 | ||
42a49f96 CW |
1080 | /* |
1081 | * We might boot into a crash-kernel here. The crashed kernel | |
1082 | * left the caches in the IOMMU dirty. So we have to flush | |
1083 | * here to evict all dirty stuff. | |
1084 | */ | |
b20ac0d4 | 1085 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1086 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1087 | } |
1088 | ||
355bf553 JR |
1089 | /* |
1090 | * Removes a device from a protection domain (unlocked) | |
1091 | */ | |
1092 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1093 | { | |
1094 | ||
1095 | /* lock domain */ | |
1096 | spin_lock(&domain->lock); | |
1097 | ||
1098 | /* remove domain from the lookup table */ | |
1099 | amd_iommu_pd_table[devid] = NULL; | |
1100 | ||
1101 | /* remove entry from the device table seen by the hardware */ | |
1102 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1103 | amd_iommu_dev_table[devid].data[1] = 0; | |
1104 | amd_iommu_dev_table[devid].data[2] = 0; | |
1105 | ||
1106 | /* decrease reference counter */ | |
1107 | domain->dev_cnt -= 1; | |
1108 | ||
1109 | /* ready */ | |
1110 | spin_unlock(&domain->lock); | |
1111 | } | |
1112 | ||
1113 | /* | |
1114 | * Removes a device from a protection domain (with devtable_lock held) | |
1115 | */ | |
1116 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1117 | { | |
1118 | unsigned long flags; | |
1119 | ||
1120 | /* lock device table */ | |
1121 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1122 | __detach_device(domain, devid); | |
1123 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1124 | } | |
e275a2a0 JR |
1125 | |
1126 | static int device_change_notifier(struct notifier_block *nb, | |
1127 | unsigned long action, void *data) | |
1128 | { | |
1129 | struct device *dev = data; | |
1130 | struct pci_dev *pdev = to_pci_dev(dev); | |
1131 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1132 | struct protection_domain *domain; | |
1133 | struct dma_ops_domain *dma_domain; | |
1134 | struct amd_iommu *iommu; | |
1ac4cbbc | 1135 | unsigned long flags; |
e275a2a0 JR |
1136 | |
1137 | if (devid > amd_iommu_last_bdf) | |
1138 | goto out; | |
1139 | ||
1140 | devid = amd_iommu_alias_table[devid]; | |
1141 | ||
1142 | iommu = amd_iommu_rlookup_table[devid]; | |
1143 | if (iommu == NULL) | |
1144 | goto out; | |
1145 | ||
1146 | domain = domain_for_device(devid); | |
1147 | ||
1148 | if (domain && !dma_ops_domain(domain)) | |
1149 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1150 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1151 | ||
1152 | switch (action) { | |
c1eee67b | 1153 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1154 | if (!domain) |
1155 | goto out; | |
1156 | detach_device(domain, devid); | |
1ac4cbbc JR |
1157 | break; |
1158 | case BUS_NOTIFY_ADD_DEVICE: | |
1159 | /* allocate a protection domain if a device is added */ | |
1160 | dma_domain = find_protection_domain(devid); | |
1161 | if (dma_domain) | |
1162 | goto out; | |
d9cfed92 | 1163 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1164 | if (!dma_domain) |
1165 | goto out; | |
1166 | dma_domain->target_dev = devid; | |
1167 | ||
1168 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1169 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1170 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1171 | ||
e275a2a0 JR |
1172 | break; |
1173 | default: | |
1174 | goto out; | |
1175 | } | |
1176 | ||
1177 | iommu_queue_inv_dev_entry(iommu, devid); | |
1178 | iommu_completion_wait(iommu); | |
1179 | ||
1180 | out: | |
1181 | return 0; | |
1182 | } | |
1183 | ||
b25ae679 | 1184 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1185 | .notifier_call = device_change_notifier, |
1186 | }; | |
355bf553 | 1187 | |
431b2a20 JR |
1188 | /***************************************************************************** |
1189 | * | |
1190 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1191 | * | |
1192 | *****************************************************************************/ | |
1193 | ||
dbcc112e JR |
1194 | /* |
1195 | * This function checks if the driver got a valid device from the caller to | |
1196 | * avoid dereferencing invalid pointers. | |
1197 | */ | |
1198 | static bool check_device(struct device *dev) | |
1199 | { | |
1200 | if (!dev || !dev->dma_mask) | |
1201 | return false; | |
1202 | ||
1203 | return true; | |
1204 | } | |
1205 | ||
bd60b735 JR |
1206 | /* |
1207 | * In this function the list of preallocated protection domains is traversed to | |
1208 | * find the domain for a specific device | |
1209 | */ | |
1210 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1211 | { | |
1212 | struct dma_ops_domain *entry, *ret = NULL; | |
1213 | unsigned long flags; | |
1214 | ||
1215 | if (list_empty(&iommu_pd_list)) | |
1216 | return NULL; | |
1217 | ||
1218 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1219 | ||
1220 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1221 | if (entry->target_dev == devid) { | |
1222 | ret = entry; | |
bd60b735 JR |
1223 | break; |
1224 | } | |
1225 | } | |
1226 | ||
1227 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1228 | ||
1229 | return ret; | |
1230 | } | |
1231 | ||
431b2a20 JR |
1232 | /* |
1233 | * In the dma_ops path we only have the struct device. This function | |
1234 | * finds the corresponding IOMMU, the protection domain and the | |
1235 | * requestor id for a given device. | |
1236 | * If the device is not yet associated with a domain this is also done | |
1237 | * in this function. | |
1238 | */ | |
b20ac0d4 JR |
1239 | static int get_device_resources(struct device *dev, |
1240 | struct amd_iommu **iommu, | |
1241 | struct protection_domain **domain, | |
1242 | u16 *bdf) | |
1243 | { | |
1244 | struct dma_ops_domain *dma_dom; | |
1245 | struct pci_dev *pcidev; | |
1246 | u16 _bdf; | |
1247 | ||
dbcc112e JR |
1248 | *iommu = NULL; |
1249 | *domain = NULL; | |
1250 | *bdf = 0xffff; | |
1251 | ||
1252 | if (dev->bus != &pci_bus_type) | |
1253 | return 0; | |
b20ac0d4 JR |
1254 | |
1255 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1256 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1257 | |
431b2a20 | 1258 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1259 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1260 | return 0; |
b20ac0d4 JR |
1261 | |
1262 | *bdf = amd_iommu_alias_table[_bdf]; | |
1263 | ||
1264 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1265 | if (*iommu == NULL) | |
1266 | return 0; | |
b20ac0d4 JR |
1267 | *domain = domain_for_device(*bdf); |
1268 | if (*domain == NULL) { | |
bd60b735 JR |
1269 | dma_dom = find_protection_domain(*bdf); |
1270 | if (!dma_dom) | |
1271 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1272 | *domain = &dma_dom->domain; |
f1179dc0 | 1273 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1274 | DUMP_printk("Using protection domain %d for device %s\n", |
1275 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1276 | } |
1277 | ||
f91ba190 | 1278 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1279 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1280 | |
b20ac0d4 JR |
1281 | return 1; |
1282 | } | |
1283 | ||
8bda3092 JR |
1284 | /* |
1285 | * If the pte_page is not yet allocated this function is called | |
1286 | */ | |
1287 | static u64* alloc_pte(struct protection_domain *dom, | |
1288 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1289 | { | |
1290 | u64 *pte, *page; | |
1291 | ||
1292 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1293 | ||
1294 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1295 | page = (u64 *)get_zeroed_page(gfp); | |
1296 | if (!page) | |
1297 | return NULL; | |
1298 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1299 | } | |
1300 | ||
1301 | pte = IOMMU_PTE_PAGE(*pte); | |
1302 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1303 | ||
1304 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1305 | page = (u64 *)get_zeroed_page(gfp); | |
1306 | if (!page) | |
1307 | return NULL; | |
1308 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1309 | } | |
1310 | ||
1311 | pte = IOMMU_PTE_PAGE(*pte); | |
1312 | ||
1313 | if (pte_page) | |
1314 | *pte_page = pte; | |
1315 | ||
1316 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1317 | ||
1318 | return pte; | |
1319 | } | |
1320 | ||
1321 | /* | |
1322 | * This function fetches the PTE for a given address in the aperture | |
1323 | */ | |
1324 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1325 | unsigned long address) | |
1326 | { | |
384de729 | 1327 | struct aperture_range *aperture; |
8bda3092 JR |
1328 | u64 *pte, *pte_page; |
1329 | ||
384de729 JR |
1330 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1331 | if (!aperture) | |
1332 | return NULL; | |
1333 | ||
1334 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1335 | if (!pte) { |
1336 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1337 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1338 | } else | |
1339 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1340 | |
1341 | return pte; | |
1342 | } | |
1343 | ||
431b2a20 JR |
1344 | /* |
1345 | * This is the generic map function. It maps one 4kb page at paddr to | |
1346 | * the given address in the DMA address space for the domain. | |
1347 | */ | |
cb76c322 JR |
1348 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1349 | struct dma_ops_domain *dom, | |
1350 | unsigned long address, | |
1351 | phys_addr_t paddr, | |
1352 | int direction) | |
1353 | { | |
1354 | u64 *pte, __pte; | |
1355 | ||
1356 | WARN_ON(address > dom->aperture_size); | |
1357 | ||
1358 | paddr &= PAGE_MASK; | |
1359 | ||
8bda3092 | 1360 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1361 | if (!pte) |
1362 | return bad_dma_address; | |
cb76c322 JR |
1363 | |
1364 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1365 | ||
1366 | if (direction == DMA_TO_DEVICE) | |
1367 | __pte |= IOMMU_PTE_IR; | |
1368 | else if (direction == DMA_FROM_DEVICE) | |
1369 | __pte |= IOMMU_PTE_IW; | |
1370 | else if (direction == DMA_BIDIRECTIONAL) | |
1371 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1372 | ||
1373 | WARN_ON(*pte); | |
1374 | ||
1375 | *pte = __pte; | |
1376 | ||
1377 | return (dma_addr_t)address; | |
1378 | } | |
1379 | ||
431b2a20 JR |
1380 | /* |
1381 | * The generic unmapping function for on page in the DMA address space. | |
1382 | */ | |
cb76c322 JR |
1383 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1384 | struct dma_ops_domain *dom, | |
1385 | unsigned long address) | |
1386 | { | |
384de729 | 1387 | struct aperture_range *aperture; |
cb76c322 JR |
1388 | u64 *pte; |
1389 | ||
1390 | if (address >= dom->aperture_size) | |
1391 | return; | |
1392 | ||
384de729 JR |
1393 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1394 | if (!aperture) | |
1395 | return; | |
1396 | ||
1397 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1398 | if (!pte) | |
1399 | return; | |
cb76c322 | 1400 | |
cb76c322 JR |
1401 | pte += IOMMU_PTE_L0_INDEX(address); |
1402 | ||
1403 | WARN_ON(!*pte); | |
1404 | ||
1405 | *pte = 0ULL; | |
1406 | } | |
1407 | ||
431b2a20 JR |
1408 | /* |
1409 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1410 | * contiguous memory region into DMA address space. It is used by all |
1411 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1412 | * Must be called with the domain lock held. |
1413 | */ | |
cb76c322 JR |
1414 | static dma_addr_t __map_single(struct device *dev, |
1415 | struct amd_iommu *iommu, | |
1416 | struct dma_ops_domain *dma_dom, | |
1417 | phys_addr_t paddr, | |
1418 | size_t size, | |
6d4f343f | 1419 | int dir, |
832a90c3 JR |
1420 | bool align, |
1421 | u64 dma_mask) | |
cb76c322 JR |
1422 | { |
1423 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1424 | dma_addr_t address, start, ret; |
cb76c322 | 1425 | unsigned int pages; |
6d4f343f | 1426 | unsigned long align_mask = 0; |
cb76c322 JR |
1427 | int i; |
1428 | ||
e3c449f5 | 1429 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1430 | paddr &= PAGE_MASK; |
1431 | ||
8ecaf8f1 JR |
1432 | INC_STATS_COUNTER(total_map_requests); |
1433 | ||
c1858976 JR |
1434 | if (pages > 1) |
1435 | INC_STATS_COUNTER(cross_page); | |
1436 | ||
6d4f343f JR |
1437 | if (align) |
1438 | align_mask = (1UL << get_order(size)) - 1; | |
1439 | ||
11b83888 | 1440 | retry: |
832a90c3 JR |
1441 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1442 | dma_mask); | |
11b83888 JR |
1443 | if (unlikely(address == bad_dma_address)) { |
1444 | /* | |
1445 | * setting next_address here will let the address | |
1446 | * allocator only scan the new allocated range in the | |
1447 | * first run. This is a small optimization. | |
1448 | */ | |
1449 | dma_dom->next_address = dma_dom->aperture_size; | |
1450 | ||
1451 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1452 | goto out; | |
1453 | ||
1454 | /* | |
1455 | * aperture was sucessfully enlarged by 128 MB, try | |
1456 | * allocation again | |
1457 | */ | |
1458 | goto retry; | |
1459 | } | |
cb76c322 JR |
1460 | |
1461 | start = address; | |
1462 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1463 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1464 | if (ret == bad_dma_address) | |
1465 | goto out_unmap; | |
1466 | ||
cb76c322 JR |
1467 | paddr += PAGE_SIZE; |
1468 | start += PAGE_SIZE; | |
1469 | } | |
1470 | address += offset; | |
1471 | ||
5774f7c5 JR |
1472 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1473 | ||
afa9fdc2 | 1474 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1475 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1476 | dma_dom->need_flush = false; | |
1477 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1478 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1479 | ||
cb76c322 JR |
1480 | out: |
1481 | return address; | |
53812c11 JR |
1482 | |
1483 | out_unmap: | |
1484 | ||
1485 | for (--i; i >= 0; --i) { | |
1486 | start -= PAGE_SIZE; | |
1487 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1488 | } | |
1489 | ||
1490 | dma_ops_free_addresses(dma_dom, address, pages); | |
1491 | ||
1492 | return bad_dma_address; | |
cb76c322 JR |
1493 | } |
1494 | ||
431b2a20 JR |
1495 | /* |
1496 | * Does the reverse of the __map_single function. Must be called with | |
1497 | * the domain lock held too | |
1498 | */ | |
cb76c322 JR |
1499 | static void __unmap_single(struct amd_iommu *iommu, |
1500 | struct dma_ops_domain *dma_dom, | |
1501 | dma_addr_t dma_addr, | |
1502 | size_t size, | |
1503 | int dir) | |
1504 | { | |
1505 | dma_addr_t i, start; | |
1506 | unsigned int pages; | |
1507 | ||
b8d9905d JR |
1508 | if ((dma_addr == bad_dma_address) || |
1509 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1510 | return; |
1511 | ||
e3c449f5 | 1512 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1513 | dma_addr &= PAGE_MASK; |
1514 | start = dma_addr; | |
1515 | ||
1516 | for (i = 0; i < pages; ++i) { | |
1517 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1518 | start += PAGE_SIZE; | |
1519 | } | |
1520 | ||
5774f7c5 JR |
1521 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1522 | ||
cb76c322 | 1523 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1524 | |
80be308d | 1525 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1526 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1527 | dma_dom->need_flush = false; |
1528 | } | |
cb76c322 JR |
1529 | } |
1530 | ||
431b2a20 JR |
1531 | /* |
1532 | * The exported map_single function for dma_ops. | |
1533 | */ | |
51491367 FT |
1534 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1535 | unsigned long offset, size_t size, | |
1536 | enum dma_data_direction dir, | |
1537 | struct dma_attrs *attrs) | |
4da70b9e JR |
1538 | { |
1539 | unsigned long flags; | |
1540 | struct amd_iommu *iommu; | |
1541 | struct protection_domain *domain; | |
1542 | u16 devid; | |
1543 | dma_addr_t addr; | |
832a90c3 | 1544 | u64 dma_mask; |
51491367 | 1545 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1546 | |
0f2a86f2 JR |
1547 | INC_STATS_COUNTER(cnt_map_single); |
1548 | ||
dbcc112e JR |
1549 | if (!check_device(dev)) |
1550 | return bad_dma_address; | |
1551 | ||
832a90c3 | 1552 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1553 | |
1554 | get_device_resources(dev, &iommu, &domain, &devid); | |
1555 | ||
1556 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1557 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1558 | return (dma_addr_t)paddr; |
1559 | ||
5b28df6f JR |
1560 | if (!dma_ops_domain(domain)) |
1561 | return bad_dma_address; | |
1562 | ||
4da70b9e | 1563 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1564 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1565 | dma_mask); | |
4da70b9e JR |
1566 | if (addr == bad_dma_address) |
1567 | goto out; | |
1568 | ||
09ee17eb | 1569 | iommu_completion_wait(iommu); |
4da70b9e JR |
1570 | |
1571 | out: | |
1572 | spin_unlock_irqrestore(&domain->lock, flags); | |
1573 | ||
1574 | return addr; | |
1575 | } | |
1576 | ||
431b2a20 JR |
1577 | /* |
1578 | * The exported unmap_single function for dma_ops. | |
1579 | */ | |
51491367 FT |
1580 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1581 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1582 | { |
1583 | unsigned long flags; | |
1584 | struct amd_iommu *iommu; | |
1585 | struct protection_domain *domain; | |
1586 | u16 devid; | |
1587 | ||
146a6917 JR |
1588 | INC_STATS_COUNTER(cnt_unmap_single); |
1589 | ||
dbcc112e JR |
1590 | if (!check_device(dev) || |
1591 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1592 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1593 | return; |
1594 | ||
5b28df6f JR |
1595 | if (!dma_ops_domain(domain)) |
1596 | return; | |
1597 | ||
4da70b9e JR |
1598 | spin_lock_irqsave(&domain->lock, flags); |
1599 | ||
1600 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1601 | ||
09ee17eb | 1602 | iommu_completion_wait(iommu); |
4da70b9e JR |
1603 | |
1604 | spin_unlock_irqrestore(&domain->lock, flags); | |
1605 | } | |
1606 | ||
431b2a20 JR |
1607 | /* |
1608 | * This is a special map_sg function which is used if we should map a | |
1609 | * device which is not handled by an AMD IOMMU in the system. | |
1610 | */ | |
65b050ad JR |
1611 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1612 | int nelems, int dir) | |
1613 | { | |
1614 | struct scatterlist *s; | |
1615 | int i; | |
1616 | ||
1617 | for_each_sg(sglist, s, nelems, i) { | |
1618 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1619 | s->dma_length = s->length; | |
1620 | } | |
1621 | ||
1622 | return nelems; | |
1623 | } | |
1624 | ||
431b2a20 JR |
1625 | /* |
1626 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1627 | * lists). | |
1628 | */ | |
65b050ad | 1629 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1630 | int nelems, enum dma_data_direction dir, |
1631 | struct dma_attrs *attrs) | |
65b050ad JR |
1632 | { |
1633 | unsigned long flags; | |
1634 | struct amd_iommu *iommu; | |
1635 | struct protection_domain *domain; | |
1636 | u16 devid; | |
1637 | int i; | |
1638 | struct scatterlist *s; | |
1639 | phys_addr_t paddr; | |
1640 | int mapped_elems = 0; | |
832a90c3 | 1641 | u64 dma_mask; |
65b050ad | 1642 | |
d03f067a JR |
1643 | INC_STATS_COUNTER(cnt_map_sg); |
1644 | ||
dbcc112e JR |
1645 | if (!check_device(dev)) |
1646 | return 0; | |
1647 | ||
832a90c3 | 1648 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1649 | |
1650 | get_device_resources(dev, &iommu, &domain, &devid); | |
1651 | ||
1652 | if (!iommu || !domain) | |
1653 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1654 | ||
5b28df6f JR |
1655 | if (!dma_ops_domain(domain)) |
1656 | return 0; | |
1657 | ||
65b050ad JR |
1658 | spin_lock_irqsave(&domain->lock, flags); |
1659 | ||
1660 | for_each_sg(sglist, s, nelems, i) { | |
1661 | paddr = sg_phys(s); | |
1662 | ||
1663 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1664 | paddr, s->length, dir, false, |
1665 | dma_mask); | |
65b050ad JR |
1666 | |
1667 | if (s->dma_address) { | |
1668 | s->dma_length = s->length; | |
1669 | mapped_elems++; | |
1670 | } else | |
1671 | goto unmap; | |
65b050ad JR |
1672 | } |
1673 | ||
09ee17eb | 1674 | iommu_completion_wait(iommu); |
65b050ad JR |
1675 | |
1676 | out: | |
1677 | spin_unlock_irqrestore(&domain->lock, flags); | |
1678 | ||
1679 | return mapped_elems; | |
1680 | unmap: | |
1681 | for_each_sg(sglist, s, mapped_elems, i) { | |
1682 | if (s->dma_address) | |
1683 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1684 | s->dma_length, dir); | |
1685 | s->dma_address = s->dma_length = 0; | |
1686 | } | |
1687 | ||
1688 | mapped_elems = 0; | |
1689 | ||
1690 | goto out; | |
1691 | } | |
1692 | ||
431b2a20 JR |
1693 | /* |
1694 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1695 | * lists). | |
1696 | */ | |
65b050ad | 1697 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1698 | int nelems, enum dma_data_direction dir, |
1699 | struct dma_attrs *attrs) | |
65b050ad JR |
1700 | { |
1701 | unsigned long flags; | |
1702 | struct amd_iommu *iommu; | |
1703 | struct protection_domain *domain; | |
1704 | struct scatterlist *s; | |
1705 | u16 devid; | |
1706 | int i; | |
1707 | ||
55877a6b JR |
1708 | INC_STATS_COUNTER(cnt_unmap_sg); |
1709 | ||
dbcc112e JR |
1710 | if (!check_device(dev) || |
1711 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1712 | return; |
1713 | ||
5b28df6f JR |
1714 | if (!dma_ops_domain(domain)) |
1715 | return; | |
1716 | ||
65b050ad JR |
1717 | spin_lock_irqsave(&domain->lock, flags); |
1718 | ||
1719 | for_each_sg(sglist, s, nelems, i) { | |
1720 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1721 | s->dma_length, dir); | |
65b050ad JR |
1722 | s->dma_address = s->dma_length = 0; |
1723 | } | |
1724 | ||
09ee17eb | 1725 | iommu_completion_wait(iommu); |
65b050ad JR |
1726 | |
1727 | spin_unlock_irqrestore(&domain->lock, flags); | |
1728 | } | |
1729 | ||
431b2a20 JR |
1730 | /* |
1731 | * The exported alloc_coherent function for dma_ops. | |
1732 | */ | |
5d8b53cf JR |
1733 | static void *alloc_coherent(struct device *dev, size_t size, |
1734 | dma_addr_t *dma_addr, gfp_t flag) | |
1735 | { | |
1736 | unsigned long flags; | |
1737 | void *virt_addr; | |
1738 | struct amd_iommu *iommu; | |
1739 | struct protection_domain *domain; | |
1740 | u16 devid; | |
1741 | phys_addr_t paddr; | |
832a90c3 | 1742 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1743 | |
c8f0fb36 JR |
1744 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1745 | ||
dbcc112e JR |
1746 | if (!check_device(dev)) |
1747 | return NULL; | |
5d8b53cf | 1748 | |
13d9fead FT |
1749 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1750 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1751 | |
c97ac535 | 1752 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1753 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1754 | if (!virt_addr) | |
b25ae679 | 1755 | return NULL; |
5d8b53cf | 1756 | |
5d8b53cf JR |
1757 | paddr = virt_to_phys(virt_addr); |
1758 | ||
5d8b53cf JR |
1759 | if (!iommu || !domain) { |
1760 | *dma_addr = (dma_addr_t)paddr; | |
1761 | return virt_addr; | |
1762 | } | |
1763 | ||
5b28df6f JR |
1764 | if (!dma_ops_domain(domain)) |
1765 | goto out_free; | |
1766 | ||
832a90c3 JR |
1767 | if (!dma_mask) |
1768 | dma_mask = *dev->dma_mask; | |
1769 | ||
5d8b53cf JR |
1770 | spin_lock_irqsave(&domain->lock, flags); |
1771 | ||
1772 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1773 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1774 | |
367d04c4 JS |
1775 | if (*dma_addr == bad_dma_address) { |
1776 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1777 | goto out_free; |
367d04c4 | 1778 | } |
5d8b53cf | 1779 | |
09ee17eb | 1780 | iommu_completion_wait(iommu); |
5d8b53cf | 1781 | |
5d8b53cf JR |
1782 | spin_unlock_irqrestore(&domain->lock, flags); |
1783 | ||
1784 | return virt_addr; | |
5b28df6f JR |
1785 | |
1786 | out_free: | |
1787 | ||
1788 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1789 | ||
1790 | return NULL; | |
5d8b53cf JR |
1791 | } |
1792 | ||
431b2a20 JR |
1793 | /* |
1794 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1795 | */ |
5d8b53cf JR |
1796 | static void free_coherent(struct device *dev, size_t size, |
1797 | void *virt_addr, dma_addr_t dma_addr) | |
1798 | { | |
1799 | unsigned long flags; | |
1800 | struct amd_iommu *iommu; | |
1801 | struct protection_domain *domain; | |
1802 | u16 devid; | |
1803 | ||
5d31ee7e JR |
1804 | INC_STATS_COUNTER(cnt_free_coherent); |
1805 | ||
dbcc112e JR |
1806 | if (!check_device(dev)) |
1807 | return; | |
1808 | ||
5d8b53cf JR |
1809 | get_device_resources(dev, &iommu, &domain, &devid); |
1810 | ||
1811 | if (!iommu || !domain) | |
1812 | goto free_mem; | |
1813 | ||
5b28df6f JR |
1814 | if (!dma_ops_domain(domain)) |
1815 | goto free_mem; | |
1816 | ||
5d8b53cf JR |
1817 | spin_lock_irqsave(&domain->lock, flags); |
1818 | ||
1819 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1820 | |
09ee17eb | 1821 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1822 | |
1823 | spin_unlock_irqrestore(&domain->lock, flags); | |
1824 | ||
1825 | free_mem: | |
1826 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1827 | } | |
1828 | ||
b39ba6ad JR |
1829 | /* |
1830 | * This function is called by the DMA layer to find out if we can handle a | |
1831 | * particular device. It is part of the dma_ops. | |
1832 | */ | |
1833 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1834 | { | |
1835 | u16 bdf; | |
1836 | struct pci_dev *pcidev; | |
1837 | ||
1838 | /* No device or no PCI device */ | |
1839 | if (!dev || dev->bus != &pci_bus_type) | |
1840 | return 0; | |
1841 | ||
1842 | pcidev = to_pci_dev(dev); | |
1843 | ||
1844 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1845 | ||
1846 | /* Out of our scope? */ | |
1847 | if (bdf > amd_iommu_last_bdf) | |
1848 | return 0; | |
1849 | ||
1850 | return 1; | |
1851 | } | |
1852 | ||
c432f3df | 1853 | /* |
431b2a20 JR |
1854 | * The function for pre-allocating protection domains. |
1855 | * | |
c432f3df JR |
1856 | * If the driver core informs the DMA layer if a driver grabs a device |
1857 | * we don't need to preallocate the protection domains anymore. | |
1858 | * For now we have to. | |
1859 | */ | |
0e93dd88 | 1860 | static void prealloc_protection_domains(void) |
c432f3df JR |
1861 | { |
1862 | struct pci_dev *dev = NULL; | |
1863 | struct dma_ops_domain *dma_dom; | |
1864 | struct amd_iommu *iommu; | |
c432f3df JR |
1865 | u16 devid; |
1866 | ||
1867 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1868 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1869 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1870 | continue; |
1871 | devid = amd_iommu_alias_table[devid]; | |
1872 | if (domain_for_device(devid)) | |
1873 | continue; | |
1874 | iommu = amd_iommu_rlookup_table[devid]; | |
1875 | if (!iommu) | |
1876 | continue; | |
d9cfed92 | 1877 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1878 | if (!dma_dom) |
1879 | continue; | |
1880 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1881 | dma_dom->target_dev = devid; |
1882 | ||
1883 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1884 | } |
1885 | } | |
1886 | ||
160c1d8e | 1887 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1888 | .alloc_coherent = alloc_coherent, |
1889 | .free_coherent = free_coherent, | |
51491367 FT |
1890 | .map_page = map_page, |
1891 | .unmap_page = unmap_page, | |
6631ee9d JR |
1892 | .map_sg = map_sg, |
1893 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1894 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1895 | }; |
1896 | ||
431b2a20 JR |
1897 | /* |
1898 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1899 | */ | |
6631ee9d JR |
1900 | int __init amd_iommu_init_dma_ops(void) |
1901 | { | |
1902 | struct amd_iommu *iommu; | |
6631ee9d JR |
1903 | int ret; |
1904 | ||
431b2a20 JR |
1905 | /* |
1906 | * first allocate a default protection domain for every IOMMU we | |
1907 | * found in the system. Devices not assigned to any other | |
1908 | * protection domain will be assigned to the default one. | |
1909 | */ | |
3bd22172 | 1910 | for_each_iommu(iommu) { |
d9cfed92 | 1911 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1912 | if (iommu->default_dom == NULL) |
1913 | return -ENOMEM; | |
e2dc14a2 | 1914 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1915 | ret = iommu_init_unity_mappings(iommu); |
1916 | if (ret) | |
1917 | goto free_domains; | |
1918 | } | |
1919 | ||
431b2a20 JR |
1920 | /* |
1921 | * If device isolation is enabled, pre-allocate the protection | |
1922 | * domains for each device. | |
1923 | */ | |
6631ee9d JR |
1924 | if (amd_iommu_isolate) |
1925 | prealloc_protection_domains(); | |
1926 | ||
1927 | iommu_detected = 1; | |
1928 | force_iommu = 1; | |
1929 | bad_dma_address = 0; | |
92af4e29 | 1930 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1931 | gart_iommu_aperture_disabled = 1; |
1932 | gart_iommu_aperture = 0; | |
92af4e29 | 1933 | #endif |
6631ee9d | 1934 | |
431b2a20 | 1935 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1936 | dma_ops = &amd_iommu_dma_ops; |
1937 | ||
26961efe | 1938 | register_iommu(&amd_iommu_ops); |
26961efe | 1939 | |
e275a2a0 JR |
1940 | bus_register_notifier(&pci_bus_type, &device_nb); |
1941 | ||
7f26508b JR |
1942 | amd_iommu_stats_init(); |
1943 | ||
6631ee9d JR |
1944 | return 0; |
1945 | ||
1946 | free_domains: | |
1947 | ||
3bd22172 | 1948 | for_each_iommu(iommu) { |
6631ee9d JR |
1949 | if (iommu->default_dom) |
1950 | dma_ops_domain_free(iommu->default_dom); | |
1951 | } | |
1952 | ||
1953 | return ret; | |
1954 | } | |
6d98cd80 JR |
1955 | |
1956 | /***************************************************************************** | |
1957 | * | |
1958 | * The following functions belong to the exported interface of AMD IOMMU | |
1959 | * | |
1960 | * This interface allows access to lower level functions of the IOMMU | |
1961 | * like protection domain handling and assignement of devices to domains | |
1962 | * which is not possible with the dma_ops interface. | |
1963 | * | |
1964 | *****************************************************************************/ | |
1965 | ||
6d98cd80 JR |
1966 | static void cleanup_domain(struct protection_domain *domain) |
1967 | { | |
1968 | unsigned long flags; | |
1969 | u16 devid; | |
1970 | ||
1971 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1972 | ||
1973 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1974 | if (amd_iommu_pd_table[devid] == domain) | |
1975 | __detach_device(domain, devid); | |
1976 | ||
1977 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1978 | } | |
1979 | ||
c156e347 JR |
1980 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1981 | { | |
1982 | struct protection_domain *domain; | |
1983 | ||
1984 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1985 | if (!domain) | |
1986 | return -ENOMEM; | |
1987 | ||
1988 | spin_lock_init(&domain->lock); | |
1989 | domain->mode = PAGE_MODE_3_LEVEL; | |
1990 | domain->id = domain_id_alloc(); | |
1991 | if (!domain->id) | |
1992 | goto out_free; | |
1993 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1994 | if (!domain->pt_root) | |
1995 | goto out_free; | |
1996 | ||
1997 | dom->priv = domain; | |
1998 | ||
1999 | return 0; | |
2000 | ||
2001 | out_free: | |
2002 | kfree(domain); | |
2003 | ||
2004 | return -ENOMEM; | |
2005 | } | |
2006 | ||
98383fc3 JR |
2007 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2008 | { | |
2009 | struct protection_domain *domain = dom->priv; | |
2010 | ||
2011 | if (!domain) | |
2012 | return; | |
2013 | ||
2014 | if (domain->dev_cnt > 0) | |
2015 | cleanup_domain(domain); | |
2016 | ||
2017 | BUG_ON(domain->dev_cnt != 0); | |
2018 | ||
2019 | free_pagetable(domain); | |
2020 | ||
2021 | domain_id_free(domain->id); | |
2022 | ||
2023 | kfree(domain); | |
2024 | ||
2025 | dom->priv = NULL; | |
2026 | } | |
2027 | ||
684f2888 JR |
2028 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2029 | struct device *dev) | |
2030 | { | |
2031 | struct protection_domain *domain = dom->priv; | |
2032 | struct amd_iommu *iommu; | |
2033 | struct pci_dev *pdev; | |
2034 | u16 devid; | |
2035 | ||
2036 | if (dev->bus != &pci_bus_type) | |
2037 | return; | |
2038 | ||
2039 | pdev = to_pci_dev(dev); | |
2040 | ||
2041 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2042 | ||
2043 | if (devid > 0) | |
2044 | detach_device(domain, devid); | |
2045 | ||
2046 | iommu = amd_iommu_rlookup_table[devid]; | |
2047 | if (!iommu) | |
2048 | return; | |
2049 | ||
2050 | iommu_queue_inv_dev_entry(iommu, devid); | |
2051 | iommu_completion_wait(iommu); | |
2052 | } | |
2053 | ||
01106066 JR |
2054 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2055 | struct device *dev) | |
2056 | { | |
2057 | struct protection_domain *domain = dom->priv; | |
2058 | struct protection_domain *old_domain; | |
2059 | struct amd_iommu *iommu; | |
2060 | struct pci_dev *pdev; | |
2061 | u16 devid; | |
2062 | ||
2063 | if (dev->bus != &pci_bus_type) | |
2064 | return -EINVAL; | |
2065 | ||
2066 | pdev = to_pci_dev(dev); | |
2067 | ||
2068 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2069 | ||
2070 | if (devid >= amd_iommu_last_bdf || | |
2071 | devid != amd_iommu_alias_table[devid]) | |
2072 | return -EINVAL; | |
2073 | ||
2074 | iommu = amd_iommu_rlookup_table[devid]; | |
2075 | if (!iommu) | |
2076 | return -EINVAL; | |
2077 | ||
2078 | old_domain = domain_for_device(devid); | |
2079 | if (old_domain) | |
71ff3bca | 2080 | detach_device(old_domain, devid); |
01106066 JR |
2081 | |
2082 | attach_device(iommu, domain, devid); | |
2083 | ||
2084 | iommu_completion_wait(iommu); | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
c6229ca6 JR |
2089 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2090 | unsigned long iova, phys_addr_t paddr, | |
2091 | size_t size, int iommu_prot) | |
2092 | { | |
2093 | struct protection_domain *domain = dom->priv; | |
2094 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2095 | int prot = 0; | |
2096 | int ret; | |
2097 | ||
2098 | if (iommu_prot & IOMMU_READ) | |
2099 | prot |= IOMMU_PROT_IR; | |
2100 | if (iommu_prot & IOMMU_WRITE) | |
2101 | prot |= IOMMU_PROT_IW; | |
2102 | ||
2103 | iova &= PAGE_MASK; | |
2104 | paddr &= PAGE_MASK; | |
2105 | ||
2106 | for (i = 0; i < npages; ++i) { | |
2107 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2108 | if (ret) | |
2109 | return ret; | |
2110 | ||
2111 | iova += PAGE_SIZE; | |
2112 | paddr += PAGE_SIZE; | |
2113 | } | |
2114 | ||
2115 | return 0; | |
2116 | } | |
2117 | ||
eb74ff6c JR |
2118 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2119 | unsigned long iova, size_t size) | |
2120 | { | |
2121 | ||
2122 | struct protection_domain *domain = dom->priv; | |
2123 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2124 | ||
2125 | iova &= PAGE_MASK; | |
2126 | ||
2127 | for (i = 0; i < npages; ++i) { | |
2128 | iommu_unmap_page(domain, iova); | |
2129 | iova += PAGE_SIZE; | |
2130 | } | |
2131 | ||
2132 | iommu_flush_domain(domain->id); | |
2133 | } | |
2134 | ||
645c4c8d JR |
2135 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2136 | unsigned long iova) | |
2137 | { | |
2138 | struct protection_domain *domain = dom->priv; | |
2139 | unsigned long offset = iova & ~PAGE_MASK; | |
2140 | phys_addr_t paddr; | |
2141 | u64 *pte; | |
2142 | ||
2143 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2144 | ||
2145 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2146 | return 0; | |
2147 | ||
2148 | pte = IOMMU_PTE_PAGE(*pte); | |
2149 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2150 | ||
2151 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2152 | return 0; | |
2153 | ||
2154 | pte = IOMMU_PTE_PAGE(*pte); | |
2155 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2156 | ||
2157 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2158 | return 0; | |
2159 | ||
2160 | paddr = *pte & IOMMU_PAGE_MASK; | |
2161 | paddr |= offset; | |
2162 | ||
2163 | return paddr; | |
2164 | } | |
2165 | ||
dbb9fd86 SY |
2166 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2167 | unsigned long cap) | |
2168 | { | |
2169 | return 0; | |
2170 | } | |
2171 | ||
26961efe JR |
2172 | static struct iommu_ops amd_iommu_ops = { |
2173 | .domain_init = amd_iommu_domain_init, | |
2174 | .domain_destroy = amd_iommu_domain_destroy, | |
2175 | .attach_dev = amd_iommu_attach_device, | |
2176 | .detach_dev = amd_iommu_detach_device, | |
2177 | .map = amd_iommu_map_range, | |
2178 | .unmap = amd_iommu_unmap_range, | |
2179 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2180 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2181 | }; |
2182 |