]>
Commit | Line | Data |
---|---|---|
b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 JR |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/iommu-helper.h> | |
c156e347 JR |
26 | #ifdef CONFIG_IOMMU_API |
27 | #include <linux/iommu.h> | |
28 | #endif | |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
26961efe JR |
45 | #ifdef CONFIG_IOMMU_API |
46 | static struct iommu_ops amd_iommu_ops; | |
47 | #endif | |
48 | ||
431b2a20 JR |
49 | /* |
50 | * general struct to manage commands send to an IOMMU | |
51 | */ | |
d6449536 | 52 | struct iommu_cmd { |
b6c02715 JR |
53 | u32 data[4]; |
54 | }; | |
55 | ||
bd0e5211 JR |
56 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
57 | struct unity_map_entry *e); | |
e275a2a0 JR |
58 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
59 | ||
bd0e5211 | 60 | |
7f26508b JR |
61 | #ifdef CONFIG_AMD_IOMMU_STATS |
62 | ||
63 | /* | |
64 | * Initialization code for statistics collection | |
65 | */ | |
66 | ||
da49f6df | 67 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 68 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 69 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 70 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 71 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 72 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 73 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 74 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 75 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 76 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 77 | DECLARE_STATS_COUNTER(alloced_io_mem); |
da49f6df | 78 | |
7f26508b JR |
79 | static struct dentry *stats_dir; |
80 | static struct dentry *de_isolate; | |
81 | static struct dentry *de_fflush; | |
82 | ||
83 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
84 | { | |
85 | if (stats_dir == NULL) | |
86 | return; | |
87 | ||
88 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
89 | &cnt->value); | |
90 | } | |
91 | ||
92 | static void amd_iommu_stats_init(void) | |
93 | { | |
94 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
95 | if (stats_dir == NULL) | |
96 | return; | |
97 | ||
98 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
99 | (u32 *)&amd_iommu_isolate); | |
100 | ||
101 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
102 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
103 | |
104 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 105 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 106 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 107 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 108 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 109 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 110 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 111 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 112 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 113 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 114 | amd_iommu_stats_add(&alloced_io_mem); |
7f26508b JR |
115 | } |
116 | ||
117 | #endif | |
118 | ||
431b2a20 | 119 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
120 | static int iommu_has_npcache(struct amd_iommu *iommu) |
121 | { | |
ae9b9403 | 122 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
123 | } |
124 | ||
a80dc3e0 JR |
125 | /**************************************************************************** |
126 | * | |
127 | * Interrupt handling functions | |
128 | * | |
129 | ****************************************************************************/ | |
130 | ||
90008ee4 JR |
131 | static void iommu_print_event(void *__evt) |
132 | { | |
133 | u32 *event = __evt; | |
134 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
135 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
136 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
137 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
138 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
139 | ||
140 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
141 | ||
142 | switch (type) { | |
143 | case EVENT_TYPE_ILL_DEV: | |
144 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
145 | "address=0x%016llx flags=0x%04x]\n", | |
146 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
147 | address, flags); | |
148 | break; | |
149 | case EVENT_TYPE_IO_FAULT: | |
150 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
151 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
152 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
153 | domid, address, flags); | |
154 | break; | |
155 | case EVENT_TYPE_DEV_TAB_ERR: | |
156 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
157 | "address=0x%016llx flags=0x%04x]\n", | |
158 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
159 | address, flags); | |
160 | break; | |
161 | case EVENT_TYPE_PAGE_TAB_ERR: | |
162 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
163 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
164 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
165 | domid, address, flags); | |
166 | break; | |
167 | case EVENT_TYPE_ILL_CMD: | |
168 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
169 | break; | |
170 | case EVENT_TYPE_CMD_HARD_ERR: | |
171 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
172 | "flags=0x%04x]\n", address, flags); | |
173 | break; | |
174 | case EVENT_TYPE_IOTLB_INV_TO: | |
175 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
176 | "address=0x%016llx]\n", | |
177 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
178 | address); | |
179 | break; | |
180 | case EVENT_TYPE_INV_DEV_REQ: | |
181 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
182 | "address=0x%016llx flags=0x%04x]\n", | |
183 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
184 | address, flags); | |
185 | break; | |
186 | default: | |
187 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
188 | } | |
189 | } | |
190 | ||
191 | static void iommu_poll_events(struct amd_iommu *iommu) | |
192 | { | |
193 | u32 head, tail; | |
194 | unsigned long flags; | |
195 | ||
196 | spin_lock_irqsave(&iommu->lock, flags); | |
197 | ||
198 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
199 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
200 | ||
201 | while (head != tail) { | |
202 | iommu_print_event(iommu->evt_buf + head); | |
203 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
204 | } | |
205 | ||
206 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
207 | ||
208 | spin_unlock_irqrestore(&iommu->lock, flags); | |
209 | } | |
210 | ||
a80dc3e0 JR |
211 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
212 | { | |
90008ee4 JR |
213 | struct amd_iommu *iommu; |
214 | ||
215 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
216 | iommu_poll_events(iommu); | |
217 | ||
218 | return IRQ_HANDLED; | |
a80dc3e0 JR |
219 | } |
220 | ||
431b2a20 JR |
221 | /**************************************************************************** |
222 | * | |
223 | * IOMMU command queuing functions | |
224 | * | |
225 | ****************************************************************************/ | |
226 | ||
227 | /* | |
228 | * Writes the command to the IOMMUs command buffer and informs the | |
229 | * hardware about the new command. Must be called with iommu->lock held. | |
230 | */ | |
d6449536 | 231 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
232 | { |
233 | u32 tail, head; | |
234 | u8 *target; | |
235 | ||
236 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 237 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
238 | memcpy_toio(target, cmd, sizeof(*cmd)); |
239 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
240 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
241 | if (tail == head) | |
242 | return -ENOMEM; | |
243 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
431b2a20 JR |
248 | /* |
249 | * General queuing function for commands. Takes iommu->lock and calls | |
250 | * __iommu_queue_command(). | |
251 | */ | |
d6449536 | 252 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
253 | { |
254 | unsigned long flags; | |
255 | int ret; | |
256 | ||
257 | spin_lock_irqsave(&iommu->lock, flags); | |
258 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 259 | if (!ret) |
0cfd7aa9 | 260 | iommu->need_sync = true; |
a19ae1ec JR |
261 | spin_unlock_irqrestore(&iommu->lock, flags); |
262 | ||
263 | return ret; | |
264 | } | |
265 | ||
8d201968 JR |
266 | /* |
267 | * This function waits until an IOMMU has completed a completion | |
268 | * wait command | |
269 | */ | |
270 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
271 | { | |
272 | int ready = 0; | |
273 | unsigned status = 0; | |
274 | unsigned long i = 0; | |
275 | ||
da49f6df JR |
276 | INC_STATS_COUNTER(compl_wait); |
277 | ||
8d201968 JR |
278 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
279 | ++i; | |
280 | /* wait for the bit to become one */ | |
281 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
282 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
283 | } | |
284 | ||
285 | /* set bit back to zero */ | |
286 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
287 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
288 | ||
289 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
290 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
291 | } | |
292 | ||
293 | /* | |
294 | * This function queues a completion wait command into the command | |
295 | * buffer of an IOMMU | |
296 | */ | |
297 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
298 | { | |
299 | struct iommu_cmd cmd; | |
300 | ||
301 | memset(&cmd, 0, sizeof(cmd)); | |
302 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
303 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
304 | ||
305 | return __iommu_queue_command(iommu, &cmd); | |
306 | } | |
307 | ||
431b2a20 JR |
308 | /* |
309 | * This function is called whenever we need to ensure that the IOMMU has | |
310 | * completed execution of all commands we sent. It sends a | |
311 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
312 | * us about that by writing a value to a physical address we pass with | |
313 | * the command. | |
314 | */ | |
a19ae1ec JR |
315 | static int iommu_completion_wait(struct amd_iommu *iommu) |
316 | { | |
8d201968 JR |
317 | int ret = 0; |
318 | unsigned long flags; | |
a19ae1ec | 319 | |
7e4f88da JR |
320 | spin_lock_irqsave(&iommu->lock, flags); |
321 | ||
09ee17eb JR |
322 | if (!iommu->need_sync) |
323 | goto out; | |
324 | ||
8d201968 | 325 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 326 | |
0cfd7aa9 | 327 | iommu->need_sync = false; |
a19ae1ec JR |
328 | |
329 | if (ret) | |
7e4f88da | 330 | goto out; |
a19ae1ec | 331 | |
8d201968 | 332 | __iommu_wait_for_completion(iommu); |
84df8175 | 333 | |
7e4f88da JR |
334 | out: |
335 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
336 | |
337 | return 0; | |
338 | } | |
339 | ||
431b2a20 JR |
340 | /* |
341 | * Command send function for invalidating a device table entry | |
342 | */ | |
a19ae1ec JR |
343 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
344 | { | |
d6449536 | 345 | struct iommu_cmd cmd; |
ee2fa743 | 346 | int ret; |
a19ae1ec JR |
347 | |
348 | BUG_ON(iommu == NULL); | |
349 | ||
350 | memset(&cmd, 0, sizeof(cmd)); | |
351 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
352 | cmd.data[0] = devid; | |
353 | ||
ee2fa743 JR |
354 | ret = iommu_queue_command(iommu, &cmd); |
355 | ||
ee2fa743 | 356 | return ret; |
a19ae1ec JR |
357 | } |
358 | ||
237b6f33 JR |
359 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
360 | u16 domid, int pde, int s) | |
361 | { | |
362 | memset(cmd, 0, sizeof(*cmd)); | |
363 | address &= PAGE_MASK; | |
364 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
365 | cmd->data[1] |= domid; | |
366 | cmd->data[2] = lower_32_bits(address); | |
367 | cmd->data[3] = upper_32_bits(address); | |
368 | if (s) /* size bit - we flush more than one 4kb page */ | |
369 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
370 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
371 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
372 | } | |
373 | ||
431b2a20 JR |
374 | /* |
375 | * Generic command send function for invalidaing TLB entries | |
376 | */ | |
a19ae1ec JR |
377 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
378 | u64 address, u16 domid, int pde, int s) | |
379 | { | |
d6449536 | 380 | struct iommu_cmd cmd; |
ee2fa743 | 381 | int ret; |
a19ae1ec | 382 | |
237b6f33 | 383 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 384 | |
ee2fa743 JR |
385 | ret = iommu_queue_command(iommu, &cmd); |
386 | ||
ee2fa743 | 387 | return ret; |
a19ae1ec JR |
388 | } |
389 | ||
431b2a20 JR |
390 | /* |
391 | * TLB invalidation function which is called from the mapping functions. | |
392 | * It invalidates a single PTE if the range to flush is within a single | |
393 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
394 | */ | |
a19ae1ec JR |
395 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
396 | u64 address, size_t size) | |
397 | { | |
999ba417 | 398 | int s = 0; |
e3c449f5 | 399 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
400 | |
401 | address &= PAGE_MASK; | |
402 | ||
999ba417 JR |
403 | if (pages > 1) { |
404 | /* | |
405 | * If we have to flush more than one page, flush all | |
406 | * TLB entries for this domain | |
407 | */ | |
408 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
409 | s = 1; | |
a19ae1ec JR |
410 | } |
411 | ||
999ba417 JR |
412 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
413 | ||
a19ae1ec JR |
414 | return 0; |
415 | } | |
b6c02715 | 416 | |
1c655773 JR |
417 | /* Flush the whole IO/TLB for a given protection domain */ |
418 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
419 | { | |
420 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
421 | ||
f57d98ae JR |
422 | INC_STATS_COUNTER(domain_flush_single); |
423 | ||
1c655773 JR |
424 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
425 | } | |
426 | ||
43f49609 JR |
427 | #ifdef CONFIG_IOMMU_API |
428 | /* | |
429 | * This function is used to flush the IO/TLB for a given protection domain | |
430 | * on every IOMMU in the system | |
431 | */ | |
432 | static void iommu_flush_domain(u16 domid) | |
433 | { | |
434 | unsigned long flags; | |
435 | struct amd_iommu *iommu; | |
436 | struct iommu_cmd cmd; | |
437 | ||
18811f55 JR |
438 | INC_STATS_COUNTER(domain_flush_all); |
439 | ||
43f49609 JR |
440 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
441 | domid, 1, 1); | |
442 | ||
443 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
444 | spin_lock_irqsave(&iommu->lock, flags); | |
445 | __iommu_queue_command(iommu, &cmd); | |
446 | __iommu_completion_wait(iommu); | |
447 | __iommu_wait_for_completion(iommu); | |
448 | spin_unlock_irqrestore(&iommu->lock, flags); | |
449 | } | |
450 | } | |
451 | #endif | |
452 | ||
431b2a20 JR |
453 | /**************************************************************************** |
454 | * | |
455 | * The functions below are used the create the page table mappings for | |
456 | * unity mapped regions. | |
457 | * | |
458 | ****************************************************************************/ | |
459 | ||
460 | /* | |
461 | * Generic mapping functions. It maps a physical address into a DMA | |
462 | * address space. It allocates the page table pages if necessary. | |
463 | * In the future it can be extended to a generic mapping function | |
464 | * supporting all features of AMD IOMMU page tables like level skipping | |
465 | * and full 64 bit address spaces. | |
466 | */ | |
38e817fe JR |
467 | static int iommu_map_page(struct protection_domain *dom, |
468 | unsigned long bus_addr, | |
469 | unsigned long phys_addr, | |
470 | int prot) | |
bd0e5211 JR |
471 | { |
472 | u64 __pte, *pte, *page; | |
473 | ||
474 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 475 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
476 | |
477 | /* only support 512GB address spaces for now */ | |
478 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
479 | return -EINVAL; | |
480 | ||
481 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
482 | ||
483 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
484 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
485 | if (!page) | |
486 | return -ENOMEM; | |
487 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
488 | } | |
489 | ||
490 | pte = IOMMU_PTE_PAGE(*pte); | |
491 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
492 | ||
493 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
494 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
495 | if (!page) | |
496 | return -ENOMEM; | |
497 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
498 | } | |
499 | ||
500 | pte = IOMMU_PTE_PAGE(*pte); | |
501 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
502 | ||
503 | if (IOMMU_PTE_PRESENT(*pte)) | |
504 | return -EBUSY; | |
505 | ||
506 | __pte = phys_addr | IOMMU_PTE_P; | |
507 | if (prot & IOMMU_PROT_IR) | |
508 | __pte |= IOMMU_PTE_IR; | |
509 | if (prot & IOMMU_PROT_IW) | |
510 | __pte |= IOMMU_PTE_IW; | |
511 | ||
512 | *pte = __pte; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
eb74ff6c JR |
517 | #ifdef CONFIG_IOMMU_API |
518 | static void iommu_unmap_page(struct protection_domain *dom, | |
519 | unsigned long bus_addr) | |
520 | { | |
521 | u64 *pte; | |
522 | ||
523 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
524 | ||
525 | if (!IOMMU_PTE_PRESENT(*pte)) | |
526 | return; | |
527 | ||
528 | pte = IOMMU_PTE_PAGE(*pte); | |
529 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
530 | ||
531 | if (!IOMMU_PTE_PRESENT(*pte)) | |
532 | return; | |
533 | ||
534 | pte = IOMMU_PTE_PAGE(*pte); | |
535 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
536 | ||
537 | *pte = 0; | |
538 | } | |
539 | #endif | |
540 | ||
431b2a20 JR |
541 | /* |
542 | * This function checks if a specific unity mapping entry is needed for | |
543 | * this specific IOMMU. | |
544 | */ | |
bd0e5211 JR |
545 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
546 | struct unity_map_entry *entry) | |
547 | { | |
548 | u16 bdf, i; | |
549 | ||
550 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
551 | bdf = amd_iommu_alias_table[i]; | |
552 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
553 | return 1; | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
431b2a20 JR |
559 | /* |
560 | * Init the unity mappings for a specific IOMMU in the system | |
561 | * | |
562 | * Basically iterates over all unity mapping entries and applies them to | |
563 | * the default domain DMA of that IOMMU if necessary. | |
564 | */ | |
bd0e5211 JR |
565 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
566 | { | |
567 | struct unity_map_entry *entry; | |
568 | int ret; | |
569 | ||
570 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
571 | if (!iommu_for_unity_map(iommu, entry)) | |
572 | continue; | |
573 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
574 | if (ret) | |
575 | return ret; | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
431b2a20 JR |
581 | /* |
582 | * This function actually applies the mapping to the page table of the | |
583 | * dma_ops domain. | |
584 | */ | |
bd0e5211 JR |
585 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
586 | struct unity_map_entry *e) | |
587 | { | |
588 | u64 addr; | |
589 | int ret; | |
590 | ||
591 | for (addr = e->address_start; addr < e->address_end; | |
592 | addr += PAGE_SIZE) { | |
38e817fe | 593 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
594 | if (ret) |
595 | return ret; | |
596 | /* | |
597 | * if unity mapping is in aperture range mark the page | |
598 | * as allocated in the aperture | |
599 | */ | |
600 | if (addr < dma_dom->aperture_size) | |
601 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
431b2a20 JR |
607 | /* |
608 | * Inits the unity mappings required for a specific device | |
609 | */ | |
bd0e5211 JR |
610 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
611 | u16 devid) | |
612 | { | |
613 | struct unity_map_entry *e; | |
614 | int ret; | |
615 | ||
616 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
617 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
618 | continue; | |
619 | ret = dma_ops_unity_map(dma_dom, e); | |
620 | if (ret) | |
621 | return ret; | |
622 | } | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
431b2a20 JR |
627 | /**************************************************************************** |
628 | * | |
629 | * The next functions belong to the address allocator for the dma_ops | |
630 | * interface functions. They work like the allocators in the other IOMMU | |
631 | * drivers. Its basically a bitmap which marks the allocated pages in | |
632 | * the aperture. Maybe it could be enhanced in the future to a more | |
633 | * efficient allocator. | |
634 | * | |
635 | ****************************************************************************/ | |
d3086444 | 636 | |
431b2a20 JR |
637 | /* |
638 | * The address allocator core function. | |
639 | * | |
640 | * called with domain->lock held | |
641 | */ | |
d3086444 JR |
642 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
643 | struct dma_ops_domain *dom, | |
6d4f343f | 644 | unsigned int pages, |
832a90c3 JR |
645 | unsigned long align_mask, |
646 | u64 dma_mask) | |
d3086444 | 647 | { |
40becd8d | 648 | unsigned long limit; |
d3086444 | 649 | unsigned long address; |
d3086444 JR |
650 | unsigned long boundary_size; |
651 | ||
652 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
653 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
654 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
655 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 656 | |
1c655773 | 657 | if (dom->next_bit >= limit) { |
d3086444 | 658 | dom->next_bit = 0; |
1c655773 JR |
659 | dom->need_flush = true; |
660 | } | |
d3086444 JR |
661 | |
662 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 663 | 0 , boundary_size, align_mask); |
1c655773 | 664 | if (address == -1) { |
d3086444 | 665 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 666 | 0, boundary_size, align_mask); |
1c655773 JR |
667 | dom->need_flush = true; |
668 | } | |
d3086444 JR |
669 | |
670 | if (likely(address != -1)) { | |
d3086444 JR |
671 | dom->next_bit = address + pages; |
672 | address <<= PAGE_SHIFT; | |
673 | } else | |
674 | address = bad_dma_address; | |
675 | ||
676 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
677 | ||
678 | return address; | |
679 | } | |
680 | ||
431b2a20 JR |
681 | /* |
682 | * The address free function. | |
683 | * | |
684 | * called with domain->lock held | |
685 | */ | |
d3086444 JR |
686 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
687 | unsigned long address, | |
688 | unsigned int pages) | |
689 | { | |
690 | address >>= PAGE_SHIFT; | |
691 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 692 | |
8501c45c | 693 | if (address >= dom->next_bit) |
80be308d | 694 | dom->need_flush = true; |
d3086444 JR |
695 | } |
696 | ||
431b2a20 JR |
697 | /**************************************************************************** |
698 | * | |
699 | * The next functions belong to the domain allocation. A domain is | |
700 | * allocated for every IOMMU as the default domain. If device isolation | |
701 | * is enabled, every device get its own domain. The most important thing | |
702 | * about domains is the page table mapping the DMA address space they | |
703 | * contain. | |
704 | * | |
705 | ****************************************************************************/ | |
706 | ||
ec487d1a JR |
707 | static u16 domain_id_alloc(void) |
708 | { | |
709 | unsigned long flags; | |
710 | int id; | |
711 | ||
712 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
713 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
714 | BUG_ON(id == 0); | |
715 | if (id > 0 && id < MAX_DOMAIN_ID) | |
716 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
717 | else | |
718 | id = 0; | |
719 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
720 | ||
721 | return id; | |
722 | } | |
723 | ||
a2acfb75 JR |
724 | #ifdef CONFIG_IOMMU_API |
725 | static void domain_id_free(int id) | |
726 | { | |
727 | unsigned long flags; | |
728 | ||
729 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
730 | if (id > 0 && id < MAX_DOMAIN_ID) | |
731 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
732 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
733 | } | |
734 | #endif | |
735 | ||
431b2a20 JR |
736 | /* |
737 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
738 | * ranges. | |
739 | */ | |
ec487d1a JR |
740 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
741 | unsigned long start_page, | |
742 | unsigned int pages) | |
743 | { | |
744 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
745 | ||
746 | if (start_page + pages > last_page) | |
747 | pages = last_page - start_page; | |
748 | ||
d26dbc5c | 749 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
750 | } |
751 | ||
86db2e5d | 752 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
753 | { |
754 | int i, j; | |
755 | u64 *p1, *p2, *p3; | |
756 | ||
86db2e5d | 757 | p1 = domain->pt_root; |
ec487d1a JR |
758 | |
759 | if (!p1) | |
760 | return; | |
761 | ||
762 | for (i = 0; i < 512; ++i) { | |
763 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
764 | continue; | |
765 | ||
766 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 767 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
768 | if (!IOMMU_PTE_PRESENT(p2[j])) |
769 | continue; | |
770 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
771 | free_page((unsigned long)p3); | |
772 | } | |
773 | ||
774 | free_page((unsigned long)p2); | |
775 | } | |
776 | ||
777 | free_page((unsigned long)p1); | |
86db2e5d JR |
778 | |
779 | domain->pt_root = NULL; | |
ec487d1a JR |
780 | } |
781 | ||
431b2a20 JR |
782 | /* |
783 | * Free a domain, only used if something went wrong in the | |
784 | * allocation path and we need to free an already allocated page table | |
785 | */ | |
ec487d1a JR |
786 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
787 | { | |
788 | if (!dom) | |
789 | return; | |
790 | ||
86db2e5d | 791 | free_pagetable(&dom->domain); |
ec487d1a JR |
792 | |
793 | kfree(dom->pte_pages); | |
794 | ||
795 | kfree(dom->bitmap); | |
796 | ||
797 | kfree(dom); | |
798 | } | |
799 | ||
431b2a20 JR |
800 | /* |
801 | * Allocates a new protection domain usable for the dma_ops functions. | |
802 | * It also intializes the page table and the address allocator data | |
803 | * structures required for the dma_ops interface | |
804 | */ | |
ec487d1a JR |
805 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
806 | unsigned order) | |
807 | { | |
808 | struct dma_ops_domain *dma_dom; | |
809 | unsigned i, num_pte_pages; | |
810 | u64 *l2_pde; | |
811 | u64 address; | |
812 | ||
813 | /* | |
814 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
815 | */ | |
816 | if ((order < 25) || (order > 30)) | |
817 | return NULL; | |
818 | ||
819 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
820 | if (!dma_dom) | |
821 | return NULL; | |
822 | ||
823 | spin_lock_init(&dma_dom->domain.lock); | |
824 | ||
825 | dma_dom->domain.id = domain_id_alloc(); | |
826 | if (dma_dom->domain.id == 0) | |
827 | goto free_dma_dom; | |
828 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
829 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 830 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
831 | dma_dom->domain.priv = dma_dom; |
832 | if (!dma_dom->domain.pt_root) | |
833 | goto free_dma_dom; | |
834 | dma_dom->aperture_size = (1ULL << order); | |
835 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
836 | GFP_KERNEL); | |
837 | if (!dma_dom->bitmap) | |
838 | goto free_dma_dom; | |
839 | /* | |
840 | * mark the first page as allocated so we never return 0 as | |
841 | * a valid dma-address. So we can use 0 as error value | |
842 | */ | |
843 | dma_dom->bitmap[0] = 1; | |
844 | dma_dom->next_bit = 0; | |
845 | ||
1c655773 | 846 | dma_dom->need_flush = false; |
bd60b735 | 847 | dma_dom->target_dev = 0xffff; |
1c655773 | 848 | |
431b2a20 | 849 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
850 | if (iommu->exclusion_start && |
851 | iommu->exclusion_start < dma_dom->aperture_size) { | |
852 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
853 | int pages = iommu_num_pages(iommu->exclusion_start, |
854 | iommu->exclusion_length, | |
855 | PAGE_SIZE); | |
ec487d1a JR |
856 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
857 | } | |
858 | ||
431b2a20 JR |
859 | /* |
860 | * At the last step, build the page tables so we don't need to | |
861 | * allocate page table pages in the dma_ops mapping/unmapping | |
862 | * path. | |
863 | */ | |
ec487d1a JR |
864 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
865 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
866 | GFP_KERNEL); | |
867 | if (!dma_dom->pte_pages) | |
868 | goto free_dma_dom; | |
869 | ||
870 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
871 | if (l2_pde == NULL) | |
872 | goto free_dma_dom; | |
873 | ||
874 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
875 | ||
876 | for (i = 0; i < num_pte_pages; ++i) { | |
877 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
878 | if (!dma_dom->pte_pages[i]) | |
879 | goto free_dma_dom; | |
880 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
881 | l2_pde[i] = IOMMU_L1_PDE(address); | |
882 | } | |
883 | ||
884 | return dma_dom; | |
885 | ||
886 | free_dma_dom: | |
887 | dma_ops_domain_free(dma_dom); | |
888 | ||
889 | return NULL; | |
890 | } | |
891 | ||
5b28df6f JR |
892 | /* |
893 | * little helper function to check whether a given protection domain is a | |
894 | * dma_ops domain | |
895 | */ | |
896 | static bool dma_ops_domain(struct protection_domain *domain) | |
897 | { | |
898 | return domain->flags & PD_DMA_OPS_MASK; | |
899 | } | |
900 | ||
431b2a20 JR |
901 | /* |
902 | * Find out the protection domain structure for a given PCI device. This | |
903 | * will give us the pointer to the page table root for example. | |
904 | */ | |
b20ac0d4 JR |
905 | static struct protection_domain *domain_for_device(u16 devid) |
906 | { | |
907 | struct protection_domain *dom; | |
908 | unsigned long flags; | |
909 | ||
910 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
911 | dom = amd_iommu_pd_table[devid]; | |
912 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
913 | ||
914 | return dom; | |
915 | } | |
916 | ||
431b2a20 JR |
917 | /* |
918 | * If a device is not yet associated with a domain, this function does | |
919 | * assigns it visible for the hardware | |
920 | */ | |
f1179dc0 JR |
921 | static void attach_device(struct amd_iommu *iommu, |
922 | struct protection_domain *domain, | |
923 | u16 devid) | |
b20ac0d4 JR |
924 | { |
925 | unsigned long flags; | |
b20ac0d4 JR |
926 | u64 pte_root = virt_to_phys(domain->pt_root); |
927 | ||
863c74eb JR |
928 | domain->dev_cnt += 1; |
929 | ||
38ddf41b JR |
930 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
931 | << DEV_ENTRY_MODE_SHIFT; | |
932 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
933 | |
934 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
935 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
936 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
937 | amd_iommu_dev_table[devid].data[2] = domain->id; |
938 | ||
939 | amd_iommu_pd_table[devid] = domain; | |
940 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
941 | ||
942 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
943 | } |
944 | ||
355bf553 JR |
945 | /* |
946 | * Removes a device from a protection domain (unlocked) | |
947 | */ | |
948 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
949 | { | |
950 | ||
951 | /* lock domain */ | |
952 | spin_lock(&domain->lock); | |
953 | ||
954 | /* remove domain from the lookup table */ | |
955 | amd_iommu_pd_table[devid] = NULL; | |
956 | ||
957 | /* remove entry from the device table seen by the hardware */ | |
958 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
959 | amd_iommu_dev_table[devid].data[1] = 0; | |
960 | amd_iommu_dev_table[devid].data[2] = 0; | |
961 | ||
962 | /* decrease reference counter */ | |
963 | domain->dev_cnt -= 1; | |
964 | ||
965 | /* ready */ | |
966 | spin_unlock(&domain->lock); | |
967 | } | |
968 | ||
969 | /* | |
970 | * Removes a device from a protection domain (with devtable_lock held) | |
971 | */ | |
972 | static void detach_device(struct protection_domain *domain, u16 devid) | |
973 | { | |
974 | unsigned long flags; | |
975 | ||
976 | /* lock device table */ | |
977 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
978 | __detach_device(domain, devid); | |
979 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
980 | } | |
e275a2a0 JR |
981 | |
982 | static int device_change_notifier(struct notifier_block *nb, | |
983 | unsigned long action, void *data) | |
984 | { | |
985 | struct device *dev = data; | |
986 | struct pci_dev *pdev = to_pci_dev(dev); | |
987 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
988 | struct protection_domain *domain; | |
989 | struct dma_ops_domain *dma_domain; | |
990 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
991 | int order = amd_iommu_aperture_order; |
992 | unsigned long flags; | |
e275a2a0 JR |
993 | |
994 | if (devid > amd_iommu_last_bdf) | |
995 | goto out; | |
996 | ||
997 | devid = amd_iommu_alias_table[devid]; | |
998 | ||
999 | iommu = amd_iommu_rlookup_table[devid]; | |
1000 | if (iommu == NULL) | |
1001 | goto out; | |
1002 | ||
1003 | domain = domain_for_device(devid); | |
1004 | ||
1005 | if (domain && !dma_ops_domain(domain)) | |
1006 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1007 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1008 | ||
1009 | switch (action) { | |
1010 | case BUS_NOTIFY_BOUND_DRIVER: | |
1011 | if (domain) | |
1012 | goto out; | |
1013 | dma_domain = find_protection_domain(devid); | |
1014 | if (!dma_domain) | |
1015 | dma_domain = iommu->default_dom; | |
1016 | attach_device(iommu, &dma_domain->domain, devid); | |
1017 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1018 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1019 | break; | |
1020 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1021 | if (!domain) | |
1022 | goto out; | |
1023 | detach_device(domain, devid); | |
1ac4cbbc JR |
1024 | break; |
1025 | case BUS_NOTIFY_ADD_DEVICE: | |
1026 | /* allocate a protection domain if a device is added */ | |
1027 | dma_domain = find_protection_domain(devid); | |
1028 | if (dma_domain) | |
1029 | goto out; | |
1030 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1031 | if (!dma_domain) | |
1032 | goto out; | |
1033 | dma_domain->target_dev = devid; | |
1034 | ||
1035 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1036 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1037 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1038 | ||
e275a2a0 JR |
1039 | break; |
1040 | default: | |
1041 | goto out; | |
1042 | } | |
1043 | ||
1044 | iommu_queue_inv_dev_entry(iommu, devid); | |
1045 | iommu_completion_wait(iommu); | |
1046 | ||
1047 | out: | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | struct notifier_block device_nb = { | |
1052 | .notifier_call = device_change_notifier, | |
1053 | }; | |
355bf553 | 1054 | |
431b2a20 JR |
1055 | /***************************************************************************** |
1056 | * | |
1057 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1058 | * | |
1059 | *****************************************************************************/ | |
1060 | ||
dbcc112e JR |
1061 | /* |
1062 | * This function checks if the driver got a valid device from the caller to | |
1063 | * avoid dereferencing invalid pointers. | |
1064 | */ | |
1065 | static bool check_device(struct device *dev) | |
1066 | { | |
1067 | if (!dev || !dev->dma_mask) | |
1068 | return false; | |
1069 | ||
1070 | return true; | |
1071 | } | |
1072 | ||
bd60b735 JR |
1073 | /* |
1074 | * In this function the list of preallocated protection domains is traversed to | |
1075 | * find the domain for a specific device | |
1076 | */ | |
1077 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1078 | { | |
1079 | struct dma_ops_domain *entry, *ret = NULL; | |
1080 | unsigned long flags; | |
1081 | ||
1082 | if (list_empty(&iommu_pd_list)) | |
1083 | return NULL; | |
1084 | ||
1085 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1086 | ||
1087 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1088 | if (entry->target_dev == devid) { | |
1089 | ret = entry; | |
bd60b735 JR |
1090 | break; |
1091 | } | |
1092 | } | |
1093 | ||
1094 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1095 | ||
1096 | return ret; | |
1097 | } | |
1098 | ||
431b2a20 JR |
1099 | /* |
1100 | * In the dma_ops path we only have the struct device. This function | |
1101 | * finds the corresponding IOMMU, the protection domain and the | |
1102 | * requestor id for a given device. | |
1103 | * If the device is not yet associated with a domain this is also done | |
1104 | * in this function. | |
1105 | */ | |
b20ac0d4 JR |
1106 | static int get_device_resources(struct device *dev, |
1107 | struct amd_iommu **iommu, | |
1108 | struct protection_domain **domain, | |
1109 | u16 *bdf) | |
1110 | { | |
1111 | struct dma_ops_domain *dma_dom; | |
1112 | struct pci_dev *pcidev; | |
1113 | u16 _bdf; | |
1114 | ||
dbcc112e JR |
1115 | *iommu = NULL; |
1116 | *domain = NULL; | |
1117 | *bdf = 0xffff; | |
1118 | ||
1119 | if (dev->bus != &pci_bus_type) | |
1120 | return 0; | |
b20ac0d4 JR |
1121 | |
1122 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1123 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1124 | |
431b2a20 | 1125 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1126 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1127 | return 0; |
b20ac0d4 JR |
1128 | |
1129 | *bdf = amd_iommu_alias_table[_bdf]; | |
1130 | ||
1131 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1132 | if (*iommu == NULL) | |
1133 | return 0; | |
b20ac0d4 JR |
1134 | *domain = domain_for_device(*bdf); |
1135 | if (*domain == NULL) { | |
bd60b735 JR |
1136 | dma_dom = find_protection_domain(*bdf); |
1137 | if (!dma_dom) | |
1138 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1139 | *domain = &dma_dom->domain; |
f1179dc0 | 1140 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1141 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1142 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1143 | } |
1144 | ||
f91ba190 | 1145 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1146 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1147 | |
b20ac0d4 JR |
1148 | return 1; |
1149 | } | |
1150 | ||
431b2a20 JR |
1151 | /* |
1152 | * This is the generic map function. It maps one 4kb page at paddr to | |
1153 | * the given address in the DMA address space for the domain. | |
1154 | */ | |
cb76c322 JR |
1155 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1156 | struct dma_ops_domain *dom, | |
1157 | unsigned long address, | |
1158 | phys_addr_t paddr, | |
1159 | int direction) | |
1160 | { | |
1161 | u64 *pte, __pte; | |
1162 | ||
1163 | WARN_ON(address > dom->aperture_size); | |
1164 | ||
1165 | paddr &= PAGE_MASK; | |
1166 | ||
1167 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1168 | pte += IOMMU_PTE_L0_INDEX(address); | |
1169 | ||
1170 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1171 | ||
1172 | if (direction == DMA_TO_DEVICE) | |
1173 | __pte |= IOMMU_PTE_IR; | |
1174 | else if (direction == DMA_FROM_DEVICE) | |
1175 | __pte |= IOMMU_PTE_IW; | |
1176 | else if (direction == DMA_BIDIRECTIONAL) | |
1177 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1178 | ||
1179 | WARN_ON(*pte); | |
1180 | ||
1181 | *pte = __pte; | |
1182 | ||
1183 | return (dma_addr_t)address; | |
1184 | } | |
1185 | ||
431b2a20 JR |
1186 | /* |
1187 | * The generic unmapping function for on page in the DMA address space. | |
1188 | */ | |
cb76c322 JR |
1189 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1190 | struct dma_ops_domain *dom, | |
1191 | unsigned long address) | |
1192 | { | |
1193 | u64 *pte; | |
1194 | ||
1195 | if (address >= dom->aperture_size) | |
1196 | return; | |
1197 | ||
8ad909c4 | 1198 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1199 | |
1200 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1201 | pte += IOMMU_PTE_L0_INDEX(address); | |
1202 | ||
1203 | WARN_ON(!*pte); | |
1204 | ||
1205 | *pte = 0ULL; | |
1206 | } | |
1207 | ||
431b2a20 JR |
1208 | /* |
1209 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1210 | * contiguous memory region into DMA address space. It is used by all |
1211 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1212 | * Must be called with the domain lock held. |
1213 | */ | |
cb76c322 JR |
1214 | static dma_addr_t __map_single(struct device *dev, |
1215 | struct amd_iommu *iommu, | |
1216 | struct dma_ops_domain *dma_dom, | |
1217 | phys_addr_t paddr, | |
1218 | size_t size, | |
6d4f343f | 1219 | int dir, |
832a90c3 JR |
1220 | bool align, |
1221 | u64 dma_mask) | |
cb76c322 JR |
1222 | { |
1223 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1224 | dma_addr_t address, start; | |
1225 | unsigned int pages; | |
6d4f343f | 1226 | unsigned long align_mask = 0; |
cb76c322 JR |
1227 | int i; |
1228 | ||
e3c449f5 | 1229 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1230 | paddr &= PAGE_MASK; |
1231 | ||
c1858976 JR |
1232 | if (pages > 1) |
1233 | INC_STATS_COUNTER(cross_page); | |
1234 | ||
6d4f343f JR |
1235 | if (align) |
1236 | align_mask = (1UL << get_order(size)) - 1; | |
1237 | ||
832a90c3 JR |
1238 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1239 | dma_mask); | |
cb76c322 JR |
1240 | if (unlikely(address == bad_dma_address)) |
1241 | goto out; | |
1242 | ||
1243 | start = address; | |
1244 | for (i = 0; i < pages; ++i) { | |
1245 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1246 | paddr += PAGE_SIZE; | |
1247 | start += PAGE_SIZE; | |
1248 | } | |
1249 | address += offset; | |
1250 | ||
5774f7c5 JR |
1251 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1252 | ||
afa9fdc2 | 1253 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1254 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1255 | dma_dom->need_flush = false; | |
1256 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1257 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1258 | ||
cb76c322 JR |
1259 | out: |
1260 | return address; | |
1261 | } | |
1262 | ||
431b2a20 JR |
1263 | /* |
1264 | * Does the reverse of the __map_single function. Must be called with | |
1265 | * the domain lock held too | |
1266 | */ | |
cb76c322 JR |
1267 | static void __unmap_single(struct amd_iommu *iommu, |
1268 | struct dma_ops_domain *dma_dom, | |
1269 | dma_addr_t dma_addr, | |
1270 | size_t size, | |
1271 | int dir) | |
1272 | { | |
1273 | dma_addr_t i, start; | |
1274 | unsigned int pages; | |
1275 | ||
b8d9905d JR |
1276 | if ((dma_addr == bad_dma_address) || |
1277 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1278 | return; |
1279 | ||
e3c449f5 | 1280 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1281 | dma_addr &= PAGE_MASK; |
1282 | start = dma_addr; | |
1283 | ||
1284 | for (i = 0; i < pages; ++i) { | |
1285 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1286 | start += PAGE_SIZE; | |
1287 | } | |
1288 | ||
5774f7c5 JR |
1289 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1290 | ||
cb76c322 | 1291 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1292 | |
80be308d | 1293 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1294 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1295 | dma_dom->need_flush = false; |
1296 | } | |
cb76c322 JR |
1297 | } |
1298 | ||
431b2a20 JR |
1299 | /* |
1300 | * The exported map_single function for dma_ops. | |
1301 | */ | |
4da70b9e JR |
1302 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1303 | size_t size, int dir) | |
1304 | { | |
1305 | unsigned long flags; | |
1306 | struct amd_iommu *iommu; | |
1307 | struct protection_domain *domain; | |
1308 | u16 devid; | |
1309 | dma_addr_t addr; | |
832a90c3 | 1310 | u64 dma_mask; |
4da70b9e | 1311 | |
0f2a86f2 JR |
1312 | INC_STATS_COUNTER(cnt_map_single); |
1313 | ||
dbcc112e JR |
1314 | if (!check_device(dev)) |
1315 | return bad_dma_address; | |
1316 | ||
832a90c3 | 1317 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1318 | |
1319 | get_device_resources(dev, &iommu, &domain, &devid); | |
1320 | ||
1321 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1322 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1323 | return (dma_addr_t)paddr; |
1324 | ||
5b28df6f JR |
1325 | if (!dma_ops_domain(domain)) |
1326 | return bad_dma_address; | |
1327 | ||
4da70b9e | 1328 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1329 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1330 | dma_mask); | |
4da70b9e JR |
1331 | if (addr == bad_dma_address) |
1332 | goto out; | |
1333 | ||
09ee17eb | 1334 | iommu_completion_wait(iommu); |
4da70b9e JR |
1335 | |
1336 | out: | |
1337 | spin_unlock_irqrestore(&domain->lock, flags); | |
1338 | ||
1339 | return addr; | |
1340 | } | |
1341 | ||
431b2a20 JR |
1342 | /* |
1343 | * The exported unmap_single function for dma_ops. | |
1344 | */ | |
4da70b9e JR |
1345 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1346 | size_t size, int dir) | |
1347 | { | |
1348 | unsigned long flags; | |
1349 | struct amd_iommu *iommu; | |
1350 | struct protection_domain *domain; | |
1351 | u16 devid; | |
1352 | ||
146a6917 JR |
1353 | INC_STATS_COUNTER(cnt_unmap_single); |
1354 | ||
dbcc112e JR |
1355 | if (!check_device(dev) || |
1356 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1357 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1358 | return; |
1359 | ||
5b28df6f JR |
1360 | if (!dma_ops_domain(domain)) |
1361 | return; | |
1362 | ||
4da70b9e JR |
1363 | spin_lock_irqsave(&domain->lock, flags); |
1364 | ||
1365 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1366 | ||
09ee17eb | 1367 | iommu_completion_wait(iommu); |
4da70b9e JR |
1368 | |
1369 | spin_unlock_irqrestore(&domain->lock, flags); | |
1370 | } | |
1371 | ||
431b2a20 JR |
1372 | /* |
1373 | * This is a special map_sg function which is used if we should map a | |
1374 | * device which is not handled by an AMD IOMMU in the system. | |
1375 | */ | |
65b050ad JR |
1376 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1377 | int nelems, int dir) | |
1378 | { | |
1379 | struct scatterlist *s; | |
1380 | int i; | |
1381 | ||
1382 | for_each_sg(sglist, s, nelems, i) { | |
1383 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1384 | s->dma_length = s->length; | |
1385 | } | |
1386 | ||
1387 | return nelems; | |
1388 | } | |
1389 | ||
431b2a20 JR |
1390 | /* |
1391 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1392 | * lists). | |
1393 | */ | |
65b050ad JR |
1394 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1395 | int nelems, int dir) | |
1396 | { | |
1397 | unsigned long flags; | |
1398 | struct amd_iommu *iommu; | |
1399 | struct protection_domain *domain; | |
1400 | u16 devid; | |
1401 | int i; | |
1402 | struct scatterlist *s; | |
1403 | phys_addr_t paddr; | |
1404 | int mapped_elems = 0; | |
832a90c3 | 1405 | u64 dma_mask; |
65b050ad | 1406 | |
d03f067a JR |
1407 | INC_STATS_COUNTER(cnt_map_sg); |
1408 | ||
dbcc112e JR |
1409 | if (!check_device(dev)) |
1410 | return 0; | |
1411 | ||
832a90c3 | 1412 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1413 | |
1414 | get_device_resources(dev, &iommu, &domain, &devid); | |
1415 | ||
1416 | if (!iommu || !domain) | |
1417 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1418 | ||
5b28df6f JR |
1419 | if (!dma_ops_domain(domain)) |
1420 | return 0; | |
1421 | ||
65b050ad JR |
1422 | spin_lock_irqsave(&domain->lock, flags); |
1423 | ||
1424 | for_each_sg(sglist, s, nelems, i) { | |
1425 | paddr = sg_phys(s); | |
1426 | ||
1427 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1428 | paddr, s->length, dir, false, |
1429 | dma_mask); | |
65b050ad JR |
1430 | |
1431 | if (s->dma_address) { | |
1432 | s->dma_length = s->length; | |
1433 | mapped_elems++; | |
1434 | } else | |
1435 | goto unmap; | |
65b050ad JR |
1436 | } |
1437 | ||
09ee17eb | 1438 | iommu_completion_wait(iommu); |
65b050ad JR |
1439 | |
1440 | out: | |
1441 | spin_unlock_irqrestore(&domain->lock, flags); | |
1442 | ||
1443 | return mapped_elems; | |
1444 | unmap: | |
1445 | for_each_sg(sglist, s, mapped_elems, i) { | |
1446 | if (s->dma_address) | |
1447 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1448 | s->dma_length, dir); | |
1449 | s->dma_address = s->dma_length = 0; | |
1450 | } | |
1451 | ||
1452 | mapped_elems = 0; | |
1453 | ||
1454 | goto out; | |
1455 | } | |
1456 | ||
431b2a20 JR |
1457 | /* |
1458 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1459 | * lists). | |
1460 | */ | |
65b050ad JR |
1461 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1462 | int nelems, int dir) | |
1463 | { | |
1464 | unsigned long flags; | |
1465 | struct amd_iommu *iommu; | |
1466 | struct protection_domain *domain; | |
1467 | struct scatterlist *s; | |
1468 | u16 devid; | |
1469 | int i; | |
1470 | ||
55877a6b JR |
1471 | INC_STATS_COUNTER(cnt_unmap_sg); |
1472 | ||
dbcc112e JR |
1473 | if (!check_device(dev) || |
1474 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1475 | return; |
1476 | ||
5b28df6f JR |
1477 | if (!dma_ops_domain(domain)) |
1478 | return; | |
1479 | ||
65b050ad JR |
1480 | spin_lock_irqsave(&domain->lock, flags); |
1481 | ||
1482 | for_each_sg(sglist, s, nelems, i) { | |
1483 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1484 | s->dma_length, dir); | |
65b050ad JR |
1485 | s->dma_address = s->dma_length = 0; |
1486 | } | |
1487 | ||
09ee17eb | 1488 | iommu_completion_wait(iommu); |
65b050ad JR |
1489 | |
1490 | spin_unlock_irqrestore(&domain->lock, flags); | |
1491 | } | |
1492 | ||
431b2a20 JR |
1493 | /* |
1494 | * The exported alloc_coherent function for dma_ops. | |
1495 | */ | |
5d8b53cf JR |
1496 | static void *alloc_coherent(struct device *dev, size_t size, |
1497 | dma_addr_t *dma_addr, gfp_t flag) | |
1498 | { | |
1499 | unsigned long flags; | |
1500 | void *virt_addr; | |
1501 | struct amd_iommu *iommu; | |
1502 | struct protection_domain *domain; | |
1503 | u16 devid; | |
1504 | phys_addr_t paddr; | |
832a90c3 | 1505 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1506 | |
c8f0fb36 JR |
1507 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1508 | ||
dbcc112e JR |
1509 | if (!check_device(dev)) |
1510 | return NULL; | |
5d8b53cf | 1511 | |
13d9fead FT |
1512 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1513 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1514 | |
c97ac535 | 1515 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1516 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1517 | if (!virt_addr) | |
1518 | return 0; | |
1519 | ||
5d8b53cf JR |
1520 | paddr = virt_to_phys(virt_addr); |
1521 | ||
5d8b53cf JR |
1522 | if (!iommu || !domain) { |
1523 | *dma_addr = (dma_addr_t)paddr; | |
1524 | return virt_addr; | |
1525 | } | |
1526 | ||
5b28df6f JR |
1527 | if (!dma_ops_domain(domain)) |
1528 | goto out_free; | |
1529 | ||
832a90c3 JR |
1530 | if (!dma_mask) |
1531 | dma_mask = *dev->dma_mask; | |
1532 | ||
5d8b53cf JR |
1533 | spin_lock_irqsave(&domain->lock, flags); |
1534 | ||
1535 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1536 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1537 | |
5b28df6f JR |
1538 | if (*dma_addr == bad_dma_address) |
1539 | goto out_free; | |
5d8b53cf | 1540 | |
09ee17eb | 1541 | iommu_completion_wait(iommu); |
5d8b53cf | 1542 | |
5d8b53cf JR |
1543 | spin_unlock_irqrestore(&domain->lock, flags); |
1544 | ||
1545 | return virt_addr; | |
5b28df6f JR |
1546 | |
1547 | out_free: | |
1548 | ||
1549 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1550 | ||
1551 | return NULL; | |
5d8b53cf JR |
1552 | } |
1553 | ||
431b2a20 JR |
1554 | /* |
1555 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1556 | */ |
5d8b53cf JR |
1557 | static void free_coherent(struct device *dev, size_t size, |
1558 | void *virt_addr, dma_addr_t dma_addr) | |
1559 | { | |
1560 | unsigned long flags; | |
1561 | struct amd_iommu *iommu; | |
1562 | struct protection_domain *domain; | |
1563 | u16 devid; | |
1564 | ||
5d31ee7e JR |
1565 | INC_STATS_COUNTER(cnt_free_coherent); |
1566 | ||
dbcc112e JR |
1567 | if (!check_device(dev)) |
1568 | return; | |
1569 | ||
5d8b53cf JR |
1570 | get_device_resources(dev, &iommu, &domain, &devid); |
1571 | ||
1572 | if (!iommu || !domain) | |
1573 | goto free_mem; | |
1574 | ||
5b28df6f JR |
1575 | if (!dma_ops_domain(domain)) |
1576 | goto free_mem; | |
1577 | ||
5d8b53cf JR |
1578 | spin_lock_irqsave(&domain->lock, flags); |
1579 | ||
1580 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1581 | |
09ee17eb | 1582 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1583 | |
1584 | spin_unlock_irqrestore(&domain->lock, flags); | |
1585 | ||
1586 | free_mem: | |
1587 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1588 | } | |
1589 | ||
b39ba6ad JR |
1590 | /* |
1591 | * This function is called by the DMA layer to find out if we can handle a | |
1592 | * particular device. It is part of the dma_ops. | |
1593 | */ | |
1594 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1595 | { | |
1596 | u16 bdf; | |
1597 | struct pci_dev *pcidev; | |
1598 | ||
1599 | /* No device or no PCI device */ | |
1600 | if (!dev || dev->bus != &pci_bus_type) | |
1601 | return 0; | |
1602 | ||
1603 | pcidev = to_pci_dev(dev); | |
1604 | ||
1605 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1606 | ||
1607 | /* Out of our scope? */ | |
1608 | if (bdf > amd_iommu_last_bdf) | |
1609 | return 0; | |
1610 | ||
1611 | return 1; | |
1612 | } | |
1613 | ||
c432f3df | 1614 | /* |
431b2a20 JR |
1615 | * The function for pre-allocating protection domains. |
1616 | * | |
c432f3df JR |
1617 | * If the driver core informs the DMA layer if a driver grabs a device |
1618 | * we don't need to preallocate the protection domains anymore. | |
1619 | * For now we have to. | |
1620 | */ | |
1621 | void prealloc_protection_domains(void) | |
1622 | { | |
1623 | struct pci_dev *dev = NULL; | |
1624 | struct dma_ops_domain *dma_dom; | |
1625 | struct amd_iommu *iommu; | |
1626 | int order = amd_iommu_aperture_order; | |
1627 | u16 devid; | |
1628 | ||
1629 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1630 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1631 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1632 | continue; |
1633 | devid = amd_iommu_alias_table[devid]; | |
1634 | if (domain_for_device(devid)) | |
1635 | continue; | |
1636 | iommu = amd_iommu_rlookup_table[devid]; | |
1637 | if (!iommu) | |
1638 | continue; | |
1639 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1640 | if (!dma_dom) | |
1641 | continue; | |
1642 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1643 | dma_dom->target_dev = devid; |
1644 | ||
1645 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1646 | } |
1647 | } | |
1648 | ||
6631ee9d JR |
1649 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1650 | .alloc_coherent = alloc_coherent, | |
1651 | .free_coherent = free_coherent, | |
1652 | .map_single = map_single, | |
1653 | .unmap_single = unmap_single, | |
1654 | .map_sg = map_sg, | |
1655 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1656 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1657 | }; |
1658 | ||
431b2a20 JR |
1659 | /* |
1660 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1661 | */ | |
6631ee9d JR |
1662 | int __init amd_iommu_init_dma_ops(void) |
1663 | { | |
1664 | struct amd_iommu *iommu; | |
1665 | int order = amd_iommu_aperture_order; | |
1666 | int ret; | |
1667 | ||
431b2a20 JR |
1668 | /* |
1669 | * first allocate a default protection domain for every IOMMU we | |
1670 | * found in the system. Devices not assigned to any other | |
1671 | * protection domain will be assigned to the default one. | |
1672 | */ | |
6631ee9d JR |
1673 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1674 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1675 | if (iommu->default_dom == NULL) | |
1676 | return -ENOMEM; | |
e2dc14a2 | 1677 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1678 | ret = iommu_init_unity_mappings(iommu); |
1679 | if (ret) | |
1680 | goto free_domains; | |
1681 | } | |
1682 | ||
431b2a20 JR |
1683 | /* |
1684 | * If device isolation is enabled, pre-allocate the protection | |
1685 | * domains for each device. | |
1686 | */ | |
6631ee9d JR |
1687 | if (amd_iommu_isolate) |
1688 | prealloc_protection_domains(); | |
1689 | ||
1690 | iommu_detected = 1; | |
1691 | force_iommu = 1; | |
1692 | bad_dma_address = 0; | |
92af4e29 | 1693 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1694 | gart_iommu_aperture_disabled = 1; |
1695 | gart_iommu_aperture = 0; | |
92af4e29 | 1696 | #endif |
6631ee9d | 1697 | |
431b2a20 | 1698 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1699 | dma_ops = &amd_iommu_dma_ops; |
1700 | ||
26961efe JR |
1701 | #ifdef CONFIG_IOMMU_API |
1702 | register_iommu(&amd_iommu_ops); | |
1703 | #endif | |
1704 | ||
e275a2a0 JR |
1705 | bus_register_notifier(&pci_bus_type, &device_nb); |
1706 | ||
7f26508b JR |
1707 | amd_iommu_stats_init(); |
1708 | ||
6631ee9d JR |
1709 | return 0; |
1710 | ||
1711 | free_domains: | |
1712 | ||
1713 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1714 | if (iommu->default_dom) | |
1715 | dma_ops_domain_free(iommu->default_dom); | |
1716 | } | |
1717 | ||
1718 | return ret; | |
1719 | } | |
6d98cd80 JR |
1720 | |
1721 | /***************************************************************************** | |
1722 | * | |
1723 | * The following functions belong to the exported interface of AMD IOMMU | |
1724 | * | |
1725 | * This interface allows access to lower level functions of the IOMMU | |
1726 | * like protection domain handling and assignement of devices to domains | |
1727 | * which is not possible with the dma_ops interface. | |
1728 | * | |
1729 | *****************************************************************************/ | |
1730 | ||
1731 | #ifdef CONFIG_IOMMU_API | |
1732 | ||
1733 | static void cleanup_domain(struct protection_domain *domain) | |
1734 | { | |
1735 | unsigned long flags; | |
1736 | u16 devid; | |
1737 | ||
1738 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1739 | ||
1740 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1741 | if (amd_iommu_pd_table[devid] == domain) | |
1742 | __detach_device(domain, devid); | |
1743 | ||
1744 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1745 | } | |
1746 | ||
c156e347 JR |
1747 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1748 | { | |
1749 | struct protection_domain *domain; | |
1750 | ||
1751 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1752 | if (!domain) | |
1753 | return -ENOMEM; | |
1754 | ||
1755 | spin_lock_init(&domain->lock); | |
1756 | domain->mode = PAGE_MODE_3_LEVEL; | |
1757 | domain->id = domain_id_alloc(); | |
1758 | if (!domain->id) | |
1759 | goto out_free; | |
1760 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1761 | if (!domain->pt_root) | |
1762 | goto out_free; | |
1763 | ||
1764 | dom->priv = domain; | |
1765 | ||
1766 | return 0; | |
1767 | ||
1768 | out_free: | |
1769 | kfree(domain); | |
1770 | ||
1771 | return -ENOMEM; | |
1772 | } | |
1773 | ||
98383fc3 JR |
1774 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1775 | { | |
1776 | struct protection_domain *domain = dom->priv; | |
1777 | ||
1778 | if (!domain) | |
1779 | return; | |
1780 | ||
1781 | if (domain->dev_cnt > 0) | |
1782 | cleanup_domain(domain); | |
1783 | ||
1784 | BUG_ON(domain->dev_cnt != 0); | |
1785 | ||
1786 | free_pagetable(domain); | |
1787 | ||
1788 | domain_id_free(domain->id); | |
1789 | ||
1790 | kfree(domain); | |
1791 | ||
1792 | dom->priv = NULL; | |
1793 | } | |
1794 | ||
684f2888 JR |
1795 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1796 | struct device *dev) | |
1797 | { | |
1798 | struct protection_domain *domain = dom->priv; | |
1799 | struct amd_iommu *iommu; | |
1800 | struct pci_dev *pdev; | |
1801 | u16 devid; | |
1802 | ||
1803 | if (dev->bus != &pci_bus_type) | |
1804 | return; | |
1805 | ||
1806 | pdev = to_pci_dev(dev); | |
1807 | ||
1808 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1809 | ||
1810 | if (devid > 0) | |
1811 | detach_device(domain, devid); | |
1812 | ||
1813 | iommu = amd_iommu_rlookup_table[devid]; | |
1814 | if (!iommu) | |
1815 | return; | |
1816 | ||
1817 | iommu_queue_inv_dev_entry(iommu, devid); | |
1818 | iommu_completion_wait(iommu); | |
1819 | } | |
1820 | ||
01106066 JR |
1821 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1822 | struct device *dev) | |
1823 | { | |
1824 | struct protection_domain *domain = dom->priv; | |
1825 | struct protection_domain *old_domain; | |
1826 | struct amd_iommu *iommu; | |
1827 | struct pci_dev *pdev; | |
1828 | u16 devid; | |
1829 | ||
1830 | if (dev->bus != &pci_bus_type) | |
1831 | return -EINVAL; | |
1832 | ||
1833 | pdev = to_pci_dev(dev); | |
1834 | ||
1835 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1836 | ||
1837 | if (devid >= amd_iommu_last_bdf || | |
1838 | devid != amd_iommu_alias_table[devid]) | |
1839 | return -EINVAL; | |
1840 | ||
1841 | iommu = amd_iommu_rlookup_table[devid]; | |
1842 | if (!iommu) | |
1843 | return -EINVAL; | |
1844 | ||
1845 | old_domain = domain_for_device(devid); | |
1846 | if (old_domain) | |
1847 | return -EBUSY; | |
1848 | ||
1849 | attach_device(iommu, domain, devid); | |
1850 | ||
1851 | iommu_completion_wait(iommu); | |
1852 | ||
1853 | return 0; | |
1854 | } | |
1855 | ||
c6229ca6 JR |
1856 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1857 | unsigned long iova, phys_addr_t paddr, | |
1858 | size_t size, int iommu_prot) | |
1859 | { | |
1860 | struct protection_domain *domain = dom->priv; | |
1861 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1862 | int prot = 0; | |
1863 | int ret; | |
1864 | ||
1865 | if (iommu_prot & IOMMU_READ) | |
1866 | prot |= IOMMU_PROT_IR; | |
1867 | if (iommu_prot & IOMMU_WRITE) | |
1868 | prot |= IOMMU_PROT_IW; | |
1869 | ||
1870 | iova &= PAGE_MASK; | |
1871 | paddr &= PAGE_MASK; | |
1872 | ||
1873 | for (i = 0; i < npages; ++i) { | |
1874 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1875 | if (ret) | |
1876 | return ret; | |
1877 | ||
1878 | iova += PAGE_SIZE; | |
1879 | paddr += PAGE_SIZE; | |
1880 | } | |
1881 | ||
1882 | return 0; | |
1883 | } | |
1884 | ||
eb74ff6c JR |
1885 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1886 | unsigned long iova, size_t size) | |
1887 | { | |
1888 | ||
1889 | struct protection_domain *domain = dom->priv; | |
1890 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1891 | ||
1892 | iova &= PAGE_MASK; | |
1893 | ||
1894 | for (i = 0; i < npages; ++i) { | |
1895 | iommu_unmap_page(domain, iova); | |
1896 | iova += PAGE_SIZE; | |
1897 | } | |
1898 | ||
1899 | iommu_flush_domain(domain->id); | |
1900 | } | |
1901 | ||
645c4c8d JR |
1902 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1903 | unsigned long iova) | |
1904 | { | |
1905 | struct protection_domain *domain = dom->priv; | |
1906 | unsigned long offset = iova & ~PAGE_MASK; | |
1907 | phys_addr_t paddr; | |
1908 | u64 *pte; | |
1909 | ||
1910 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1911 | ||
1912 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1913 | return 0; | |
1914 | ||
1915 | pte = IOMMU_PTE_PAGE(*pte); | |
1916 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1917 | ||
1918 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1919 | return 0; | |
1920 | ||
1921 | pte = IOMMU_PTE_PAGE(*pte); | |
1922 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1923 | ||
1924 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1925 | return 0; | |
1926 | ||
1927 | paddr = *pte & IOMMU_PAGE_MASK; | |
1928 | paddr |= offset; | |
1929 | ||
1930 | return paddr; | |
1931 | } | |
1932 | ||
26961efe JR |
1933 | static struct iommu_ops amd_iommu_ops = { |
1934 | .domain_init = amd_iommu_domain_init, | |
1935 | .domain_destroy = amd_iommu_domain_destroy, | |
1936 | .attach_dev = amd_iommu_attach_device, | |
1937 | .detach_dev = amd_iommu_detach_device, | |
1938 | .map = amd_iommu_map_range, | |
1939 | .unmap = amd_iommu_unmap_range, | |
1940 | .iova_to_phys = amd_iommu_iova_to_phys, | |
1941 | }; | |
1942 | ||
6d98cd80 | 1943 | #endif |