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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 JR |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/iommu-helper.h> | |
c156e347 JR |
26 | #ifdef CONFIG_IOMMU_API |
27 | #include <linux/iommu.h> | |
28 | #endif | |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
26961efe JR |
45 | #ifdef CONFIG_IOMMU_API |
46 | static struct iommu_ops amd_iommu_ops; | |
47 | #endif | |
48 | ||
431b2a20 JR |
49 | /* |
50 | * general struct to manage commands send to an IOMMU | |
51 | */ | |
d6449536 | 52 | struct iommu_cmd { |
b6c02715 JR |
53 | u32 data[4]; |
54 | }; | |
55 | ||
bd0e5211 JR |
56 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
57 | struct unity_map_entry *e); | |
e275a2a0 JR |
58 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
59 | ||
bd0e5211 | 60 | |
7f26508b JR |
61 | #ifdef CONFIG_AMD_IOMMU_STATS |
62 | ||
63 | /* | |
64 | * Initialization code for statistics collection | |
65 | */ | |
66 | ||
da49f6df | 67 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 68 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 69 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 70 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 71 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 72 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 73 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 74 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 75 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 76 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 77 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 78 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 79 | |
7f26508b JR |
80 | static struct dentry *stats_dir; |
81 | static struct dentry *de_isolate; | |
82 | static struct dentry *de_fflush; | |
83 | ||
84 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
85 | { | |
86 | if (stats_dir == NULL) | |
87 | return; | |
88 | ||
89 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
90 | &cnt->value); | |
91 | } | |
92 | ||
93 | static void amd_iommu_stats_init(void) | |
94 | { | |
95 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
96 | if (stats_dir == NULL) | |
97 | return; | |
98 | ||
99 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
100 | (u32 *)&amd_iommu_isolate); | |
101 | ||
102 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
103 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
104 | |
105 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 106 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 107 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 108 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 109 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 110 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 111 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 112 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 113 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 114 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 115 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 116 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
117 | } |
118 | ||
119 | #endif | |
120 | ||
431b2a20 | 121 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
122 | static int iommu_has_npcache(struct amd_iommu *iommu) |
123 | { | |
ae9b9403 | 124 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
125 | } |
126 | ||
a80dc3e0 JR |
127 | /**************************************************************************** |
128 | * | |
129 | * Interrupt handling functions | |
130 | * | |
131 | ****************************************************************************/ | |
132 | ||
90008ee4 JR |
133 | static void iommu_print_event(void *__evt) |
134 | { | |
135 | u32 *event = __evt; | |
136 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
137 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
138 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
139 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
140 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
141 | ||
142 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
143 | ||
144 | switch (type) { | |
145 | case EVENT_TYPE_ILL_DEV: | |
146 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
147 | "address=0x%016llx flags=0x%04x]\n", | |
148 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
149 | address, flags); | |
150 | break; | |
151 | case EVENT_TYPE_IO_FAULT: | |
152 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
153 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
154 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
155 | domid, address, flags); | |
156 | break; | |
157 | case EVENT_TYPE_DEV_TAB_ERR: | |
158 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
159 | "address=0x%016llx flags=0x%04x]\n", | |
160 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
161 | address, flags); | |
162 | break; | |
163 | case EVENT_TYPE_PAGE_TAB_ERR: | |
164 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
165 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
166 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
167 | domid, address, flags); | |
168 | break; | |
169 | case EVENT_TYPE_ILL_CMD: | |
170 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
171 | break; | |
172 | case EVENT_TYPE_CMD_HARD_ERR: | |
173 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
174 | "flags=0x%04x]\n", address, flags); | |
175 | break; | |
176 | case EVENT_TYPE_IOTLB_INV_TO: | |
177 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
178 | "address=0x%016llx]\n", | |
179 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
180 | address); | |
181 | break; | |
182 | case EVENT_TYPE_INV_DEV_REQ: | |
183 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
184 | "address=0x%016llx flags=0x%04x]\n", | |
185 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
186 | address, flags); | |
187 | break; | |
188 | default: | |
189 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
190 | } | |
191 | } | |
192 | ||
193 | static void iommu_poll_events(struct amd_iommu *iommu) | |
194 | { | |
195 | u32 head, tail; | |
196 | unsigned long flags; | |
197 | ||
198 | spin_lock_irqsave(&iommu->lock, flags); | |
199 | ||
200 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
201 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
202 | ||
203 | while (head != tail) { | |
204 | iommu_print_event(iommu->evt_buf + head); | |
205 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
206 | } | |
207 | ||
208 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
209 | ||
210 | spin_unlock_irqrestore(&iommu->lock, flags); | |
211 | } | |
212 | ||
a80dc3e0 JR |
213 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
214 | { | |
90008ee4 JR |
215 | struct amd_iommu *iommu; |
216 | ||
217 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
218 | iommu_poll_events(iommu); | |
219 | ||
220 | return IRQ_HANDLED; | |
a80dc3e0 JR |
221 | } |
222 | ||
431b2a20 JR |
223 | /**************************************************************************** |
224 | * | |
225 | * IOMMU command queuing functions | |
226 | * | |
227 | ****************************************************************************/ | |
228 | ||
229 | /* | |
230 | * Writes the command to the IOMMUs command buffer and informs the | |
231 | * hardware about the new command. Must be called with iommu->lock held. | |
232 | */ | |
d6449536 | 233 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
234 | { |
235 | u32 tail, head; | |
236 | u8 *target; | |
237 | ||
238 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 239 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
240 | memcpy_toio(target, cmd, sizeof(*cmd)); |
241 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
242 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
243 | if (tail == head) | |
244 | return -ENOMEM; | |
245 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
431b2a20 JR |
250 | /* |
251 | * General queuing function for commands. Takes iommu->lock and calls | |
252 | * __iommu_queue_command(). | |
253 | */ | |
d6449536 | 254 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
255 | { |
256 | unsigned long flags; | |
257 | int ret; | |
258 | ||
259 | spin_lock_irqsave(&iommu->lock, flags); | |
260 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 261 | if (!ret) |
0cfd7aa9 | 262 | iommu->need_sync = true; |
a19ae1ec JR |
263 | spin_unlock_irqrestore(&iommu->lock, flags); |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
8d201968 JR |
268 | /* |
269 | * This function waits until an IOMMU has completed a completion | |
270 | * wait command | |
271 | */ | |
272 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
273 | { | |
274 | int ready = 0; | |
275 | unsigned status = 0; | |
276 | unsigned long i = 0; | |
277 | ||
da49f6df JR |
278 | INC_STATS_COUNTER(compl_wait); |
279 | ||
8d201968 JR |
280 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
281 | ++i; | |
282 | /* wait for the bit to become one */ | |
283 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
284 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
285 | } | |
286 | ||
287 | /* set bit back to zero */ | |
288 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
289 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
290 | ||
291 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
292 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
293 | } | |
294 | ||
295 | /* | |
296 | * This function queues a completion wait command into the command | |
297 | * buffer of an IOMMU | |
298 | */ | |
299 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
300 | { | |
301 | struct iommu_cmd cmd; | |
302 | ||
303 | memset(&cmd, 0, sizeof(cmd)); | |
304 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
305 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
306 | ||
307 | return __iommu_queue_command(iommu, &cmd); | |
308 | } | |
309 | ||
431b2a20 JR |
310 | /* |
311 | * This function is called whenever we need to ensure that the IOMMU has | |
312 | * completed execution of all commands we sent. It sends a | |
313 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
314 | * us about that by writing a value to a physical address we pass with | |
315 | * the command. | |
316 | */ | |
a19ae1ec JR |
317 | static int iommu_completion_wait(struct amd_iommu *iommu) |
318 | { | |
8d201968 JR |
319 | int ret = 0; |
320 | unsigned long flags; | |
a19ae1ec | 321 | |
7e4f88da JR |
322 | spin_lock_irqsave(&iommu->lock, flags); |
323 | ||
09ee17eb JR |
324 | if (!iommu->need_sync) |
325 | goto out; | |
326 | ||
8d201968 | 327 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 328 | |
0cfd7aa9 | 329 | iommu->need_sync = false; |
a19ae1ec JR |
330 | |
331 | if (ret) | |
7e4f88da | 332 | goto out; |
a19ae1ec | 333 | |
8d201968 | 334 | __iommu_wait_for_completion(iommu); |
84df8175 | 335 | |
7e4f88da JR |
336 | out: |
337 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
338 | |
339 | return 0; | |
340 | } | |
341 | ||
431b2a20 JR |
342 | /* |
343 | * Command send function for invalidating a device table entry | |
344 | */ | |
a19ae1ec JR |
345 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
346 | { | |
d6449536 | 347 | struct iommu_cmd cmd; |
ee2fa743 | 348 | int ret; |
a19ae1ec JR |
349 | |
350 | BUG_ON(iommu == NULL); | |
351 | ||
352 | memset(&cmd, 0, sizeof(cmd)); | |
353 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
354 | cmd.data[0] = devid; | |
355 | ||
ee2fa743 JR |
356 | ret = iommu_queue_command(iommu, &cmd); |
357 | ||
ee2fa743 | 358 | return ret; |
a19ae1ec JR |
359 | } |
360 | ||
237b6f33 JR |
361 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
362 | u16 domid, int pde, int s) | |
363 | { | |
364 | memset(cmd, 0, sizeof(*cmd)); | |
365 | address &= PAGE_MASK; | |
366 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
367 | cmd->data[1] |= domid; | |
368 | cmd->data[2] = lower_32_bits(address); | |
369 | cmd->data[3] = upper_32_bits(address); | |
370 | if (s) /* size bit - we flush more than one 4kb page */ | |
371 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
372 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
373 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
374 | } | |
375 | ||
431b2a20 JR |
376 | /* |
377 | * Generic command send function for invalidaing TLB entries | |
378 | */ | |
a19ae1ec JR |
379 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
380 | u64 address, u16 domid, int pde, int s) | |
381 | { | |
d6449536 | 382 | struct iommu_cmd cmd; |
ee2fa743 | 383 | int ret; |
a19ae1ec | 384 | |
237b6f33 | 385 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 386 | |
ee2fa743 JR |
387 | ret = iommu_queue_command(iommu, &cmd); |
388 | ||
ee2fa743 | 389 | return ret; |
a19ae1ec JR |
390 | } |
391 | ||
431b2a20 JR |
392 | /* |
393 | * TLB invalidation function which is called from the mapping functions. | |
394 | * It invalidates a single PTE if the range to flush is within a single | |
395 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
396 | */ | |
a19ae1ec JR |
397 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
398 | u64 address, size_t size) | |
399 | { | |
999ba417 | 400 | int s = 0; |
e3c449f5 | 401 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
402 | |
403 | address &= PAGE_MASK; | |
404 | ||
999ba417 JR |
405 | if (pages > 1) { |
406 | /* | |
407 | * If we have to flush more than one page, flush all | |
408 | * TLB entries for this domain | |
409 | */ | |
410 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
411 | s = 1; | |
a19ae1ec JR |
412 | } |
413 | ||
999ba417 JR |
414 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
415 | ||
a19ae1ec JR |
416 | return 0; |
417 | } | |
b6c02715 | 418 | |
1c655773 JR |
419 | /* Flush the whole IO/TLB for a given protection domain */ |
420 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
421 | { | |
422 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
423 | ||
f57d98ae JR |
424 | INC_STATS_COUNTER(domain_flush_single); |
425 | ||
1c655773 JR |
426 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
427 | } | |
428 | ||
43f49609 JR |
429 | /* |
430 | * This function is used to flush the IO/TLB for a given protection domain | |
431 | * on every IOMMU in the system | |
432 | */ | |
433 | static void iommu_flush_domain(u16 domid) | |
434 | { | |
435 | unsigned long flags; | |
436 | struct amd_iommu *iommu; | |
437 | struct iommu_cmd cmd; | |
438 | ||
18811f55 JR |
439 | INC_STATS_COUNTER(domain_flush_all); |
440 | ||
43f49609 JR |
441 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
442 | domid, 1, 1); | |
443 | ||
444 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
445 | spin_lock_irqsave(&iommu->lock, flags); | |
446 | __iommu_queue_command(iommu, &cmd); | |
447 | __iommu_completion_wait(iommu); | |
448 | __iommu_wait_for_completion(iommu); | |
449 | spin_unlock_irqrestore(&iommu->lock, flags); | |
450 | } | |
451 | } | |
43f49609 | 452 | |
431b2a20 JR |
453 | /**************************************************************************** |
454 | * | |
455 | * The functions below are used the create the page table mappings for | |
456 | * unity mapped regions. | |
457 | * | |
458 | ****************************************************************************/ | |
459 | ||
460 | /* | |
461 | * Generic mapping functions. It maps a physical address into a DMA | |
462 | * address space. It allocates the page table pages if necessary. | |
463 | * In the future it can be extended to a generic mapping function | |
464 | * supporting all features of AMD IOMMU page tables like level skipping | |
465 | * and full 64 bit address spaces. | |
466 | */ | |
38e817fe JR |
467 | static int iommu_map_page(struct protection_domain *dom, |
468 | unsigned long bus_addr, | |
469 | unsigned long phys_addr, | |
470 | int prot) | |
bd0e5211 JR |
471 | { |
472 | u64 __pte, *pte, *page; | |
473 | ||
474 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 475 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
476 | |
477 | /* only support 512GB address spaces for now */ | |
478 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
479 | return -EINVAL; | |
480 | ||
481 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
482 | ||
483 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
484 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
485 | if (!page) | |
486 | return -ENOMEM; | |
487 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
488 | } | |
489 | ||
490 | pte = IOMMU_PTE_PAGE(*pte); | |
491 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
492 | ||
493 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
494 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
495 | if (!page) | |
496 | return -ENOMEM; | |
497 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
498 | } | |
499 | ||
500 | pte = IOMMU_PTE_PAGE(*pte); | |
501 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
502 | ||
503 | if (IOMMU_PTE_PRESENT(*pte)) | |
504 | return -EBUSY; | |
505 | ||
506 | __pte = phys_addr | IOMMU_PTE_P; | |
507 | if (prot & IOMMU_PROT_IR) | |
508 | __pte |= IOMMU_PTE_IR; | |
509 | if (prot & IOMMU_PROT_IW) | |
510 | __pte |= IOMMU_PTE_IW; | |
511 | ||
512 | *pte = __pte; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
eb74ff6c JR |
517 | static void iommu_unmap_page(struct protection_domain *dom, |
518 | unsigned long bus_addr) | |
519 | { | |
520 | u64 *pte; | |
521 | ||
522 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
523 | ||
524 | if (!IOMMU_PTE_PRESENT(*pte)) | |
525 | return; | |
526 | ||
527 | pte = IOMMU_PTE_PAGE(*pte); | |
528 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
529 | ||
530 | if (!IOMMU_PTE_PRESENT(*pte)) | |
531 | return; | |
532 | ||
533 | pte = IOMMU_PTE_PAGE(*pte); | |
534 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
535 | ||
536 | *pte = 0; | |
537 | } | |
eb74ff6c | 538 | |
431b2a20 JR |
539 | /* |
540 | * This function checks if a specific unity mapping entry is needed for | |
541 | * this specific IOMMU. | |
542 | */ | |
bd0e5211 JR |
543 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
544 | struct unity_map_entry *entry) | |
545 | { | |
546 | u16 bdf, i; | |
547 | ||
548 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
549 | bdf = amd_iommu_alias_table[i]; | |
550 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
551 | return 1; | |
552 | } | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
431b2a20 JR |
557 | /* |
558 | * Init the unity mappings for a specific IOMMU in the system | |
559 | * | |
560 | * Basically iterates over all unity mapping entries and applies them to | |
561 | * the default domain DMA of that IOMMU if necessary. | |
562 | */ | |
bd0e5211 JR |
563 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
564 | { | |
565 | struct unity_map_entry *entry; | |
566 | int ret; | |
567 | ||
568 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
569 | if (!iommu_for_unity_map(iommu, entry)) | |
570 | continue; | |
571 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
572 | if (ret) | |
573 | return ret; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
431b2a20 JR |
579 | /* |
580 | * This function actually applies the mapping to the page table of the | |
581 | * dma_ops domain. | |
582 | */ | |
bd0e5211 JR |
583 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
584 | struct unity_map_entry *e) | |
585 | { | |
586 | u64 addr; | |
587 | int ret; | |
588 | ||
589 | for (addr = e->address_start; addr < e->address_end; | |
590 | addr += PAGE_SIZE) { | |
38e817fe | 591 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
592 | if (ret) |
593 | return ret; | |
594 | /* | |
595 | * if unity mapping is in aperture range mark the page | |
596 | * as allocated in the aperture | |
597 | */ | |
598 | if (addr < dma_dom->aperture_size) | |
599 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
600 | } | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
431b2a20 JR |
605 | /* |
606 | * Inits the unity mappings required for a specific device | |
607 | */ | |
bd0e5211 JR |
608 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
609 | u16 devid) | |
610 | { | |
611 | struct unity_map_entry *e; | |
612 | int ret; | |
613 | ||
614 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
615 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
616 | continue; | |
617 | ret = dma_ops_unity_map(dma_dom, e); | |
618 | if (ret) | |
619 | return ret; | |
620 | } | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
431b2a20 JR |
625 | /**************************************************************************** |
626 | * | |
627 | * The next functions belong to the address allocator for the dma_ops | |
628 | * interface functions. They work like the allocators in the other IOMMU | |
629 | * drivers. Its basically a bitmap which marks the allocated pages in | |
630 | * the aperture. Maybe it could be enhanced in the future to a more | |
631 | * efficient allocator. | |
632 | * | |
633 | ****************************************************************************/ | |
d3086444 | 634 | |
431b2a20 JR |
635 | /* |
636 | * The address allocator core function. | |
637 | * | |
638 | * called with domain->lock held | |
639 | */ | |
d3086444 JR |
640 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
641 | struct dma_ops_domain *dom, | |
6d4f343f | 642 | unsigned int pages, |
832a90c3 JR |
643 | unsigned long align_mask, |
644 | u64 dma_mask) | |
d3086444 | 645 | { |
40becd8d | 646 | unsigned long limit; |
d3086444 | 647 | unsigned long address; |
d3086444 JR |
648 | unsigned long boundary_size; |
649 | ||
650 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
651 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
652 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
653 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 654 | |
1c655773 | 655 | if (dom->next_bit >= limit) { |
d3086444 | 656 | dom->next_bit = 0; |
1c655773 JR |
657 | dom->need_flush = true; |
658 | } | |
d3086444 JR |
659 | |
660 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 661 | 0 , boundary_size, align_mask); |
1c655773 | 662 | if (address == -1) { |
d3086444 | 663 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 664 | 0, boundary_size, align_mask); |
1c655773 JR |
665 | dom->need_flush = true; |
666 | } | |
d3086444 JR |
667 | |
668 | if (likely(address != -1)) { | |
d3086444 JR |
669 | dom->next_bit = address + pages; |
670 | address <<= PAGE_SHIFT; | |
671 | } else | |
672 | address = bad_dma_address; | |
673 | ||
674 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
675 | ||
676 | return address; | |
677 | } | |
678 | ||
431b2a20 JR |
679 | /* |
680 | * The address free function. | |
681 | * | |
682 | * called with domain->lock held | |
683 | */ | |
d3086444 JR |
684 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
685 | unsigned long address, | |
686 | unsigned int pages) | |
687 | { | |
688 | address >>= PAGE_SHIFT; | |
689 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 690 | |
8501c45c | 691 | if (address >= dom->next_bit) |
80be308d | 692 | dom->need_flush = true; |
d3086444 JR |
693 | } |
694 | ||
431b2a20 JR |
695 | /**************************************************************************** |
696 | * | |
697 | * The next functions belong to the domain allocation. A domain is | |
698 | * allocated for every IOMMU as the default domain. If device isolation | |
699 | * is enabled, every device get its own domain. The most important thing | |
700 | * about domains is the page table mapping the DMA address space they | |
701 | * contain. | |
702 | * | |
703 | ****************************************************************************/ | |
704 | ||
ec487d1a JR |
705 | static u16 domain_id_alloc(void) |
706 | { | |
707 | unsigned long flags; | |
708 | int id; | |
709 | ||
710 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
711 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
712 | BUG_ON(id == 0); | |
713 | if (id > 0 && id < MAX_DOMAIN_ID) | |
714 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
715 | else | |
716 | id = 0; | |
717 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
718 | ||
719 | return id; | |
720 | } | |
721 | ||
a2acfb75 JR |
722 | static void domain_id_free(int id) |
723 | { | |
724 | unsigned long flags; | |
725 | ||
726 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
727 | if (id > 0 && id < MAX_DOMAIN_ID) | |
728 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
729 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
730 | } | |
a2acfb75 | 731 | |
431b2a20 JR |
732 | /* |
733 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
734 | * ranges. | |
735 | */ | |
ec487d1a JR |
736 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
737 | unsigned long start_page, | |
738 | unsigned int pages) | |
739 | { | |
740 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
741 | ||
742 | if (start_page + pages > last_page) | |
743 | pages = last_page - start_page; | |
744 | ||
d26dbc5c | 745 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
746 | } |
747 | ||
86db2e5d | 748 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
749 | { |
750 | int i, j; | |
751 | u64 *p1, *p2, *p3; | |
752 | ||
86db2e5d | 753 | p1 = domain->pt_root; |
ec487d1a JR |
754 | |
755 | if (!p1) | |
756 | return; | |
757 | ||
758 | for (i = 0; i < 512; ++i) { | |
759 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
760 | continue; | |
761 | ||
762 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 763 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
764 | if (!IOMMU_PTE_PRESENT(p2[j])) |
765 | continue; | |
766 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
767 | free_page((unsigned long)p3); | |
768 | } | |
769 | ||
770 | free_page((unsigned long)p2); | |
771 | } | |
772 | ||
773 | free_page((unsigned long)p1); | |
86db2e5d JR |
774 | |
775 | domain->pt_root = NULL; | |
ec487d1a JR |
776 | } |
777 | ||
431b2a20 JR |
778 | /* |
779 | * Free a domain, only used if something went wrong in the | |
780 | * allocation path and we need to free an already allocated page table | |
781 | */ | |
ec487d1a JR |
782 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
783 | { | |
784 | if (!dom) | |
785 | return; | |
786 | ||
86db2e5d | 787 | free_pagetable(&dom->domain); |
ec487d1a JR |
788 | |
789 | kfree(dom->pte_pages); | |
790 | ||
791 | kfree(dom->bitmap); | |
792 | ||
793 | kfree(dom); | |
794 | } | |
795 | ||
431b2a20 JR |
796 | /* |
797 | * Allocates a new protection domain usable for the dma_ops functions. | |
798 | * It also intializes the page table and the address allocator data | |
799 | * structures required for the dma_ops interface | |
800 | */ | |
ec487d1a JR |
801 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
802 | unsigned order) | |
803 | { | |
804 | struct dma_ops_domain *dma_dom; | |
805 | unsigned i, num_pte_pages; | |
806 | u64 *l2_pde; | |
807 | u64 address; | |
808 | ||
809 | /* | |
810 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
811 | */ | |
812 | if ((order < 25) || (order > 30)) | |
813 | return NULL; | |
814 | ||
815 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
816 | if (!dma_dom) | |
817 | return NULL; | |
818 | ||
819 | spin_lock_init(&dma_dom->domain.lock); | |
820 | ||
821 | dma_dom->domain.id = domain_id_alloc(); | |
822 | if (dma_dom->domain.id == 0) | |
823 | goto free_dma_dom; | |
824 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
825 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 826 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
827 | dma_dom->domain.priv = dma_dom; |
828 | if (!dma_dom->domain.pt_root) | |
829 | goto free_dma_dom; | |
830 | dma_dom->aperture_size = (1ULL << order); | |
831 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
832 | GFP_KERNEL); | |
833 | if (!dma_dom->bitmap) | |
834 | goto free_dma_dom; | |
835 | /* | |
836 | * mark the first page as allocated so we never return 0 as | |
837 | * a valid dma-address. So we can use 0 as error value | |
838 | */ | |
839 | dma_dom->bitmap[0] = 1; | |
840 | dma_dom->next_bit = 0; | |
841 | ||
1c655773 | 842 | dma_dom->need_flush = false; |
bd60b735 | 843 | dma_dom->target_dev = 0xffff; |
1c655773 | 844 | |
431b2a20 | 845 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
846 | if (iommu->exclusion_start && |
847 | iommu->exclusion_start < dma_dom->aperture_size) { | |
848 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
849 | int pages = iommu_num_pages(iommu->exclusion_start, |
850 | iommu->exclusion_length, | |
851 | PAGE_SIZE); | |
ec487d1a JR |
852 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
853 | } | |
854 | ||
431b2a20 JR |
855 | /* |
856 | * At the last step, build the page tables so we don't need to | |
857 | * allocate page table pages in the dma_ops mapping/unmapping | |
858 | * path. | |
859 | */ | |
ec487d1a JR |
860 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
861 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
862 | GFP_KERNEL); | |
863 | if (!dma_dom->pte_pages) | |
864 | goto free_dma_dom; | |
865 | ||
866 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
867 | if (l2_pde == NULL) | |
868 | goto free_dma_dom; | |
869 | ||
870 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
871 | ||
872 | for (i = 0; i < num_pte_pages; ++i) { | |
873 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
874 | if (!dma_dom->pte_pages[i]) | |
875 | goto free_dma_dom; | |
876 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
877 | l2_pde[i] = IOMMU_L1_PDE(address); | |
878 | } | |
879 | ||
880 | return dma_dom; | |
881 | ||
882 | free_dma_dom: | |
883 | dma_ops_domain_free(dma_dom); | |
884 | ||
885 | return NULL; | |
886 | } | |
887 | ||
5b28df6f JR |
888 | /* |
889 | * little helper function to check whether a given protection domain is a | |
890 | * dma_ops domain | |
891 | */ | |
892 | static bool dma_ops_domain(struct protection_domain *domain) | |
893 | { | |
894 | return domain->flags & PD_DMA_OPS_MASK; | |
895 | } | |
896 | ||
431b2a20 JR |
897 | /* |
898 | * Find out the protection domain structure for a given PCI device. This | |
899 | * will give us the pointer to the page table root for example. | |
900 | */ | |
b20ac0d4 JR |
901 | static struct protection_domain *domain_for_device(u16 devid) |
902 | { | |
903 | struct protection_domain *dom; | |
904 | unsigned long flags; | |
905 | ||
906 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
907 | dom = amd_iommu_pd_table[devid]; | |
908 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
909 | ||
910 | return dom; | |
911 | } | |
912 | ||
431b2a20 JR |
913 | /* |
914 | * If a device is not yet associated with a domain, this function does | |
915 | * assigns it visible for the hardware | |
916 | */ | |
f1179dc0 JR |
917 | static void attach_device(struct amd_iommu *iommu, |
918 | struct protection_domain *domain, | |
919 | u16 devid) | |
b20ac0d4 JR |
920 | { |
921 | unsigned long flags; | |
b20ac0d4 JR |
922 | u64 pte_root = virt_to_phys(domain->pt_root); |
923 | ||
863c74eb JR |
924 | domain->dev_cnt += 1; |
925 | ||
38ddf41b JR |
926 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
927 | << DEV_ENTRY_MODE_SHIFT; | |
928 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
929 | |
930 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
931 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
932 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
933 | amd_iommu_dev_table[devid].data[2] = domain->id; |
934 | ||
935 | amd_iommu_pd_table[devid] = domain; | |
936 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
937 | ||
938 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
939 | } |
940 | ||
355bf553 JR |
941 | /* |
942 | * Removes a device from a protection domain (unlocked) | |
943 | */ | |
944 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
945 | { | |
946 | ||
947 | /* lock domain */ | |
948 | spin_lock(&domain->lock); | |
949 | ||
950 | /* remove domain from the lookup table */ | |
951 | amd_iommu_pd_table[devid] = NULL; | |
952 | ||
953 | /* remove entry from the device table seen by the hardware */ | |
954 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
955 | amd_iommu_dev_table[devid].data[1] = 0; | |
956 | amd_iommu_dev_table[devid].data[2] = 0; | |
957 | ||
958 | /* decrease reference counter */ | |
959 | domain->dev_cnt -= 1; | |
960 | ||
961 | /* ready */ | |
962 | spin_unlock(&domain->lock); | |
963 | } | |
964 | ||
965 | /* | |
966 | * Removes a device from a protection domain (with devtable_lock held) | |
967 | */ | |
968 | static void detach_device(struct protection_domain *domain, u16 devid) | |
969 | { | |
970 | unsigned long flags; | |
971 | ||
972 | /* lock device table */ | |
973 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
974 | __detach_device(domain, devid); | |
975 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
976 | } | |
e275a2a0 JR |
977 | |
978 | static int device_change_notifier(struct notifier_block *nb, | |
979 | unsigned long action, void *data) | |
980 | { | |
981 | struct device *dev = data; | |
982 | struct pci_dev *pdev = to_pci_dev(dev); | |
983 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
984 | struct protection_domain *domain; | |
985 | struct dma_ops_domain *dma_domain; | |
986 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
987 | int order = amd_iommu_aperture_order; |
988 | unsigned long flags; | |
e275a2a0 JR |
989 | |
990 | if (devid > amd_iommu_last_bdf) | |
991 | goto out; | |
992 | ||
993 | devid = amd_iommu_alias_table[devid]; | |
994 | ||
995 | iommu = amd_iommu_rlookup_table[devid]; | |
996 | if (iommu == NULL) | |
997 | goto out; | |
998 | ||
999 | domain = domain_for_device(devid); | |
1000 | ||
1001 | if (domain && !dma_ops_domain(domain)) | |
1002 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1003 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1004 | ||
1005 | switch (action) { | |
1006 | case BUS_NOTIFY_BOUND_DRIVER: | |
1007 | if (domain) | |
1008 | goto out; | |
1009 | dma_domain = find_protection_domain(devid); | |
1010 | if (!dma_domain) | |
1011 | dma_domain = iommu->default_dom; | |
1012 | attach_device(iommu, &dma_domain->domain, devid); | |
1013 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1014 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1015 | break; | |
1016 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1017 | if (!domain) | |
1018 | goto out; | |
1019 | detach_device(domain, devid); | |
1ac4cbbc JR |
1020 | break; |
1021 | case BUS_NOTIFY_ADD_DEVICE: | |
1022 | /* allocate a protection domain if a device is added */ | |
1023 | dma_domain = find_protection_domain(devid); | |
1024 | if (dma_domain) | |
1025 | goto out; | |
1026 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1027 | if (!dma_domain) | |
1028 | goto out; | |
1029 | dma_domain->target_dev = devid; | |
1030 | ||
1031 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1032 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1033 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1034 | ||
e275a2a0 JR |
1035 | break; |
1036 | default: | |
1037 | goto out; | |
1038 | } | |
1039 | ||
1040 | iommu_queue_inv_dev_entry(iommu, devid); | |
1041 | iommu_completion_wait(iommu); | |
1042 | ||
1043 | out: | |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | struct notifier_block device_nb = { | |
1048 | .notifier_call = device_change_notifier, | |
1049 | }; | |
355bf553 | 1050 | |
431b2a20 JR |
1051 | /***************************************************************************** |
1052 | * | |
1053 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1054 | * | |
1055 | *****************************************************************************/ | |
1056 | ||
dbcc112e JR |
1057 | /* |
1058 | * This function checks if the driver got a valid device from the caller to | |
1059 | * avoid dereferencing invalid pointers. | |
1060 | */ | |
1061 | static bool check_device(struct device *dev) | |
1062 | { | |
1063 | if (!dev || !dev->dma_mask) | |
1064 | return false; | |
1065 | ||
1066 | return true; | |
1067 | } | |
1068 | ||
bd60b735 JR |
1069 | /* |
1070 | * In this function the list of preallocated protection domains is traversed to | |
1071 | * find the domain for a specific device | |
1072 | */ | |
1073 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1074 | { | |
1075 | struct dma_ops_domain *entry, *ret = NULL; | |
1076 | unsigned long flags; | |
1077 | ||
1078 | if (list_empty(&iommu_pd_list)) | |
1079 | return NULL; | |
1080 | ||
1081 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1082 | ||
1083 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1084 | if (entry->target_dev == devid) { | |
1085 | ret = entry; | |
bd60b735 JR |
1086 | break; |
1087 | } | |
1088 | } | |
1089 | ||
1090 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1091 | ||
1092 | return ret; | |
1093 | } | |
1094 | ||
431b2a20 JR |
1095 | /* |
1096 | * In the dma_ops path we only have the struct device. This function | |
1097 | * finds the corresponding IOMMU, the protection domain and the | |
1098 | * requestor id for a given device. | |
1099 | * If the device is not yet associated with a domain this is also done | |
1100 | * in this function. | |
1101 | */ | |
b20ac0d4 JR |
1102 | static int get_device_resources(struct device *dev, |
1103 | struct amd_iommu **iommu, | |
1104 | struct protection_domain **domain, | |
1105 | u16 *bdf) | |
1106 | { | |
1107 | struct dma_ops_domain *dma_dom; | |
1108 | struct pci_dev *pcidev; | |
1109 | u16 _bdf; | |
1110 | ||
dbcc112e JR |
1111 | *iommu = NULL; |
1112 | *domain = NULL; | |
1113 | *bdf = 0xffff; | |
1114 | ||
1115 | if (dev->bus != &pci_bus_type) | |
1116 | return 0; | |
b20ac0d4 JR |
1117 | |
1118 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1119 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1120 | |
431b2a20 | 1121 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1122 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1123 | return 0; |
b20ac0d4 JR |
1124 | |
1125 | *bdf = amd_iommu_alias_table[_bdf]; | |
1126 | ||
1127 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1128 | if (*iommu == NULL) | |
1129 | return 0; | |
b20ac0d4 JR |
1130 | *domain = domain_for_device(*bdf); |
1131 | if (*domain == NULL) { | |
bd60b735 JR |
1132 | dma_dom = find_protection_domain(*bdf); |
1133 | if (!dma_dom) | |
1134 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1135 | *domain = &dma_dom->domain; |
f1179dc0 | 1136 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1137 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1138 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1139 | } |
1140 | ||
f91ba190 | 1141 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1142 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1143 | |
b20ac0d4 JR |
1144 | return 1; |
1145 | } | |
1146 | ||
431b2a20 JR |
1147 | /* |
1148 | * This is the generic map function. It maps one 4kb page at paddr to | |
1149 | * the given address in the DMA address space for the domain. | |
1150 | */ | |
cb76c322 JR |
1151 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1152 | struct dma_ops_domain *dom, | |
1153 | unsigned long address, | |
1154 | phys_addr_t paddr, | |
1155 | int direction) | |
1156 | { | |
1157 | u64 *pte, __pte; | |
1158 | ||
1159 | WARN_ON(address > dom->aperture_size); | |
1160 | ||
1161 | paddr &= PAGE_MASK; | |
1162 | ||
1163 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1164 | pte += IOMMU_PTE_L0_INDEX(address); | |
1165 | ||
1166 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1167 | ||
1168 | if (direction == DMA_TO_DEVICE) | |
1169 | __pte |= IOMMU_PTE_IR; | |
1170 | else if (direction == DMA_FROM_DEVICE) | |
1171 | __pte |= IOMMU_PTE_IW; | |
1172 | else if (direction == DMA_BIDIRECTIONAL) | |
1173 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1174 | ||
1175 | WARN_ON(*pte); | |
1176 | ||
1177 | *pte = __pte; | |
1178 | ||
1179 | return (dma_addr_t)address; | |
1180 | } | |
1181 | ||
431b2a20 JR |
1182 | /* |
1183 | * The generic unmapping function for on page in the DMA address space. | |
1184 | */ | |
cb76c322 JR |
1185 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1186 | struct dma_ops_domain *dom, | |
1187 | unsigned long address) | |
1188 | { | |
1189 | u64 *pte; | |
1190 | ||
1191 | if (address >= dom->aperture_size) | |
1192 | return; | |
1193 | ||
8ad909c4 | 1194 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1195 | |
1196 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1197 | pte += IOMMU_PTE_L0_INDEX(address); | |
1198 | ||
1199 | WARN_ON(!*pte); | |
1200 | ||
1201 | *pte = 0ULL; | |
1202 | } | |
1203 | ||
431b2a20 JR |
1204 | /* |
1205 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1206 | * contiguous memory region into DMA address space. It is used by all |
1207 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1208 | * Must be called with the domain lock held. |
1209 | */ | |
cb76c322 JR |
1210 | static dma_addr_t __map_single(struct device *dev, |
1211 | struct amd_iommu *iommu, | |
1212 | struct dma_ops_domain *dma_dom, | |
1213 | phys_addr_t paddr, | |
1214 | size_t size, | |
6d4f343f | 1215 | int dir, |
832a90c3 JR |
1216 | bool align, |
1217 | u64 dma_mask) | |
cb76c322 JR |
1218 | { |
1219 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1220 | dma_addr_t address, start; | |
1221 | unsigned int pages; | |
6d4f343f | 1222 | unsigned long align_mask = 0; |
cb76c322 JR |
1223 | int i; |
1224 | ||
e3c449f5 | 1225 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1226 | paddr &= PAGE_MASK; |
1227 | ||
8ecaf8f1 JR |
1228 | INC_STATS_COUNTER(total_map_requests); |
1229 | ||
c1858976 JR |
1230 | if (pages > 1) |
1231 | INC_STATS_COUNTER(cross_page); | |
1232 | ||
6d4f343f JR |
1233 | if (align) |
1234 | align_mask = (1UL << get_order(size)) - 1; | |
1235 | ||
832a90c3 JR |
1236 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1237 | dma_mask); | |
cb76c322 JR |
1238 | if (unlikely(address == bad_dma_address)) |
1239 | goto out; | |
1240 | ||
1241 | start = address; | |
1242 | for (i = 0; i < pages; ++i) { | |
1243 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1244 | paddr += PAGE_SIZE; | |
1245 | start += PAGE_SIZE; | |
1246 | } | |
1247 | address += offset; | |
1248 | ||
5774f7c5 JR |
1249 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1250 | ||
afa9fdc2 | 1251 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1252 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1253 | dma_dom->need_flush = false; | |
1254 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1255 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1256 | ||
cb76c322 JR |
1257 | out: |
1258 | return address; | |
1259 | } | |
1260 | ||
431b2a20 JR |
1261 | /* |
1262 | * Does the reverse of the __map_single function. Must be called with | |
1263 | * the domain lock held too | |
1264 | */ | |
cb76c322 JR |
1265 | static void __unmap_single(struct amd_iommu *iommu, |
1266 | struct dma_ops_domain *dma_dom, | |
1267 | dma_addr_t dma_addr, | |
1268 | size_t size, | |
1269 | int dir) | |
1270 | { | |
1271 | dma_addr_t i, start; | |
1272 | unsigned int pages; | |
1273 | ||
b8d9905d JR |
1274 | if ((dma_addr == bad_dma_address) || |
1275 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1276 | return; |
1277 | ||
e3c449f5 | 1278 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1279 | dma_addr &= PAGE_MASK; |
1280 | start = dma_addr; | |
1281 | ||
1282 | for (i = 0; i < pages; ++i) { | |
1283 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1284 | start += PAGE_SIZE; | |
1285 | } | |
1286 | ||
5774f7c5 JR |
1287 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1288 | ||
cb76c322 | 1289 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1290 | |
80be308d | 1291 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1292 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1293 | dma_dom->need_flush = false; |
1294 | } | |
cb76c322 JR |
1295 | } |
1296 | ||
431b2a20 JR |
1297 | /* |
1298 | * The exported map_single function for dma_ops. | |
1299 | */ | |
4da70b9e JR |
1300 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1301 | size_t size, int dir) | |
1302 | { | |
1303 | unsigned long flags; | |
1304 | struct amd_iommu *iommu; | |
1305 | struct protection_domain *domain; | |
1306 | u16 devid; | |
1307 | dma_addr_t addr; | |
832a90c3 | 1308 | u64 dma_mask; |
4da70b9e | 1309 | |
0f2a86f2 JR |
1310 | INC_STATS_COUNTER(cnt_map_single); |
1311 | ||
dbcc112e JR |
1312 | if (!check_device(dev)) |
1313 | return bad_dma_address; | |
1314 | ||
832a90c3 | 1315 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1316 | |
1317 | get_device_resources(dev, &iommu, &domain, &devid); | |
1318 | ||
1319 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1320 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1321 | return (dma_addr_t)paddr; |
1322 | ||
5b28df6f JR |
1323 | if (!dma_ops_domain(domain)) |
1324 | return bad_dma_address; | |
1325 | ||
4da70b9e | 1326 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1327 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1328 | dma_mask); | |
4da70b9e JR |
1329 | if (addr == bad_dma_address) |
1330 | goto out; | |
1331 | ||
09ee17eb | 1332 | iommu_completion_wait(iommu); |
4da70b9e JR |
1333 | |
1334 | out: | |
1335 | spin_unlock_irqrestore(&domain->lock, flags); | |
1336 | ||
1337 | return addr; | |
1338 | } | |
1339 | ||
431b2a20 JR |
1340 | /* |
1341 | * The exported unmap_single function for dma_ops. | |
1342 | */ | |
4da70b9e JR |
1343 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1344 | size_t size, int dir) | |
1345 | { | |
1346 | unsigned long flags; | |
1347 | struct amd_iommu *iommu; | |
1348 | struct protection_domain *domain; | |
1349 | u16 devid; | |
1350 | ||
146a6917 JR |
1351 | INC_STATS_COUNTER(cnt_unmap_single); |
1352 | ||
dbcc112e JR |
1353 | if (!check_device(dev) || |
1354 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1355 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1356 | return; |
1357 | ||
5b28df6f JR |
1358 | if (!dma_ops_domain(domain)) |
1359 | return; | |
1360 | ||
4da70b9e JR |
1361 | spin_lock_irqsave(&domain->lock, flags); |
1362 | ||
1363 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1364 | ||
09ee17eb | 1365 | iommu_completion_wait(iommu); |
4da70b9e JR |
1366 | |
1367 | spin_unlock_irqrestore(&domain->lock, flags); | |
1368 | } | |
1369 | ||
431b2a20 JR |
1370 | /* |
1371 | * This is a special map_sg function which is used if we should map a | |
1372 | * device which is not handled by an AMD IOMMU in the system. | |
1373 | */ | |
65b050ad JR |
1374 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1375 | int nelems, int dir) | |
1376 | { | |
1377 | struct scatterlist *s; | |
1378 | int i; | |
1379 | ||
1380 | for_each_sg(sglist, s, nelems, i) { | |
1381 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1382 | s->dma_length = s->length; | |
1383 | } | |
1384 | ||
1385 | return nelems; | |
1386 | } | |
1387 | ||
431b2a20 JR |
1388 | /* |
1389 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1390 | * lists). | |
1391 | */ | |
65b050ad JR |
1392 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1393 | int nelems, int dir) | |
1394 | { | |
1395 | unsigned long flags; | |
1396 | struct amd_iommu *iommu; | |
1397 | struct protection_domain *domain; | |
1398 | u16 devid; | |
1399 | int i; | |
1400 | struct scatterlist *s; | |
1401 | phys_addr_t paddr; | |
1402 | int mapped_elems = 0; | |
832a90c3 | 1403 | u64 dma_mask; |
65b050ad | 1404 | |
d03f067a JR |
1405 | INC_STATS_COUNTER(cnt_map_sg); |
1406 | ||
dbcc112e JR |
1407 | if (!check_device(dev)) |
1408 | return 0; | |
1409 | ||
832a90c3 | 1410 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1411 | |
1412 | get_device_resources(dev, &iommu, &domain, &devid); | |
1413 | ||
1414 | if (!iommu || !domain) | |
1415 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1416 | ||
5b28df6f JR |
1417 | if (!dma_ops_domain(domain)) |
1418 | return 0; | |
1419 | ||
65b050ad JR |
1420 | spin_lock_irqsave(&domain->lock, flags); |
1421 | ||
1422 | for_each_sg(sglist, s, nelems, i) { | |
1423 | paddr = sg_phys(s); | |
1424 | ||
1425 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1426 | paddr, s->length, dir, false, |
1427 | dma_mask); | |
65b050ad JR |
1428 | |
1429 | if (s->dma_address) { | |
1430 | s->dma_length = s->length; | |
1431 | mapped_elems++; | |
1432 | } else | |
1433 | goto unmap; | |
65b050ad JR |
1434 | } |
1435 | ||
09ee17eb | 1436 | iommu_completion_wait(iommu); |
65b050ad JR |
1437 | |
1438 | out: | |
1439 | spin_unlock_irqrestore(&domain->lock, flags); | |
1440 | ||
1441 | return mapped_elems; | |
1442 | unmap: | |
1443 | for_each_sg(sglist, s, mapped_elems, i) { | |
1444 | if (s->dma_address) | |
1445 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1446 | s->dma_length, dir); | |
1447 | s->dma_address = s->dma_length = 0; | |
1448 | } | |
1449 | ||
1450 | mapped_elems = 0; | |
1451 | ||
1452 | goto out; | |
1453 | } | |
1454 | ||
431b2a20 JR |
1455 | /* |
1456 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1457 | * lists). | |
1458 | */ | |
65b050ad JR |
1459 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1460 | int nelems, int dir) | |
1461 | { | |
1462 | unsigned long flags; | |
1463 | struct amd_iommu *iommu; | |
1464 | struct protection_domain *domain; | |
1465 | struct scatterlist *s; | |
1466 | u16 devid; | |
1467 | int i; | |
1468 | ||
55877a6b JR |
1469 | INC_STATS_COUNTER(cnt_unmap_sg); |
1470 | ||
dbcc112e JR |
1471 | if (!check_device(dev) || |
1472 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1473 | return; |
1474 | ||
5b28df6f JR |
1475 | if (!dma_ops_domain(domain)) |
1476 | return; | |
1477 | ||
65b050ad JR |
1478 | spin_lock_irqsave(&domain->lock, flags); |
1479 | ||
1480 | for_each_sg(sglist, s, nelems, i) { | |
1481 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1482 | s->dma_length, dir); | |
65b050ad JR |
1483 | s->dma_address = s->dma_length = 0; |
1484 | } | |
1485 | ||
09ee17eb | 1486 | iommu_completion_wait(iommu); |
65b050ad JR |
1487 | |
1488 | spin_unlock_irqrestore(&domain->lock, flags); | |
1489 | } | |
1490 | ||
431b2a20 JR |
1491 | /* |
1492 | * The exported alloc_coherent function for dma_ops. | |
1493 | */ | |
5d8b53cf JR |
1494 | static void *alloc_coherent(struct device *dev, size_t size, |
1495 | dma_addr_t *dma_addr, gfp_t flag) | |
1496 | { | |
1497 | unsigned long flags; | |
1498 | void *virt_addr; | |
1499 | struct amd_iommu *iommu; | |
1500 | struct protection_domain *domain; | |
1501 | u16 devid; | |
1502 | phys_addr_t paddr; | |
832a90c3 | 1503 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1504 | |
c8f0fb36 JR |
1505 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1506 | ||
dbcc112e JR |
1507 | if (!check_device(dev)) |
1508 | return NULL; | |
5d8b53cf | 1509 | |
13d9fead FT |
1510 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1511 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1512 | |
c97ac535 | 1513 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1514 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1515 | if (!virt_addr) | |
1516 | return 0; | |
1517 | ||
5d8b53cf JR |
1518 | paddr = virt_to_phys(virt_addr); |
1519 | ||
5d8b53cf JR |
1520 | if (!iommu || !domain) { |
1521 | *dma_addr = (dma_addr_t)paddr; | |
1522 | return virt_addr; | |
1523 | } | |
1524 | ||
5b28df6f JR |
1525 | if (!dma_ops_domain(domain)) |
1526 | goto out_free; | |
1527 | ||
832a90c3 JR |
1528 | if (!dma_mask) |
1529 | dma_mask = *dev->dma_mask; | |
1530 | ||
5d8b53cf JR |
1531 | spin_lock_irqsave(&domain->lock, flags); |
1532 | ||
1533 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1534 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1535 | |
5b28df6f JR |
1536 | if (*dma_addr == bad_dma_address) |
1537 | goto out_free; | |
5d8b53cf | 1538 | |
09ee17eb | 1539 | iommu_completion_wait(iommu); |
5d8b53cf | 1540 | |
5d8b53cf JR |
1541 | spin_unlock_irqrestore(&domain->lock, flags); |
1542 | ||
1543 | return virt_addr; | |
5b28df6f JR |
1544 | |
1545 | out_free: | |
1546 | ||
1547 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1548 | ||
1549 | return NULL; | |
5d8b53cf JR |
1550 | } |
1551 | ||
431b2a20 JR |
1552 | /* |
1553 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1554 | */ |
5d8b53cf JR |
1555 | static void free_coherent(struct device *dev, size_t size, |
1556 | void *virt_addr, dma_addr_t dma_addr) | |
1557 | { | |
1558 | unsigned long flags; | |
1559 | struct amd_iommu *iommu; | |
1560 | struct protection_domain *domain; | |
1561 | u16 devid; | |
1562 | ||
5d31ee7e JR |
1563 | INC_STATS_COUNTER(cnt_free_coherent); |
1564 | ||
dbcc112e JR |
1565 | if (!check_device(dev)) |
1566 | return; | |
1567 | ||
5d8b53cf JR |
1568 | get_device_resources(dev, &iommu, &domain, &devid); |
1569 | ||
1570 | if (!iommu || !domain) | |
1571 | goto free_mem; | |
1572 | ||
5b28df6f JR |
1573 | if (!dma_ops_domain(domain)) |
1574 | goto free_mem; | |
1575 | ||
5d8b53cf JR |
1576 | spin_lock_irqsave(&domain->lock, flags); |
1577 | ||
1578 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1579 | |
09ee17eb | 1580 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1581 | |
1582 | spin_unlock_irqrestore(&domain->lock, flags); | |
1583 | ||
1584 | free_mem: | |
1585 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1586 | } | |
1587 | ||
b39ba6ad JR |
1588 | /* |
1589 | * This function is called by the DMA layer to find out if we can handle a | |
1590 | * particular device. It is part of the dma_ops. | |
1591 | */ | |
1592 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1593 | { | |
1594 | u16 bdf; | |
1595 | struct pci_dev *pcidev; | |
1596 | ||
1597 | /* No device or no PCI device */ | |
1598 | if (!dev || dev->bus != &pci_bus_type) | |
1599 | return 0; | |
1600 | ||
1601 | pcidev = to_pci_dev(dev); | |
1602 | ||
1603 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1604 | ||
1605 | /* Out of our scope? */ | |
1606 | if (bdf > amd_iommu_last_bdf) | |
1607 | return 0; | |
1608 | ||
1609 | return 1; | |
1610 | } | |
1611 | ||
c432f3df | 1612 | /* |
431b2a20 JR |
1613 | * The function for pre-allocating protection domains. |
1614 | * | |
c432f3df JR |
1615 | * If the driver core informs the DMA layer if a driver grabs a device |
1616 | * we don't need to preallocate the protection domains anymore. | |
1617 | * For now we have to. | |
1618 | */ | |
0e93dd88 | 1619 | static void prealloc_protection_domains(void) |
c432f3df JR |
1620 | { |
1621 | struct pci_dev *dev = NULL; | |
1622 | struct dma_ops_domain *dma_dom; | |
1623 | struct amd_iommu *iommu; | |
1624 | int order = amd_iommu_aperture_order; | |
1625 | u16 devid; | |
1626 | ||
1627 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1628 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1629 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1630 | continue; |
1631 | devid = amd_iommu_alias_table[devid]; | |
1632 | if (domain_for_device(devid)) | |
1633 | continue; | |
1634 | iommu = amd_iommu_rlookup_table[devid]; | |
1635 | if (!iommu) | |
1636 | continue; | |
1637 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1638 | if (!dma_dom) | |
1639 | continue; | |
1640 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1641 | dma_dom->target_dev = devid; |
1642 | ||
1643 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1644 | } |
1645 | } | |
1646 | ||
6631ee9d JR |
1647 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1648 | .alloc_coherent = alloc_coherent, | |
1649 | .free_coherent = free_coherent, | |
1650 | .map_single = map_single, | |
1651 | .unmap_single = unmap_single, | |
1652 | .map_sg = map_sg, | |
1653 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1654 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1655 | }; |
1656 | ||
431b2a20 JR |
1657 | /* |
1658 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1659 | */ | |
6631ee9d JR |
1660 | int __init amd_iommu_init_dma_ops(void) |
1661 | { | |
1662 | struct amd_iommu *iommu; | |
1663 | int order = amd_iommu_aperture_order; | |
1664 | int ret; | |
1665 | ||
431b2a20 JR |
1666 | /* |
1667 | * first allocate a default protection domain for every IOMMU we | |
1668 | * found in the system. Devices not assigned to any other | |
1669 | * protection domain will be assigned to the default one. | |
1670 | */ | |
6631ee9d JR |
1671 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1672 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1673 | if (iommu->default_dom == NULL) | |
1674 | return -ENOMEM; | |
e2dc14a2 | 1675 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1676 | ret = iommu_init_unity_mappings(iommu); |
1677 | if (ret) | |
1678 | goto free_domains; | |
1679 | } | |
1680 | ||
431b2a20 JR |
1681 | /* |
1682 | * If device isolation is enabled, pre-allocate the protection | |
1683 | * domains for each device. | |
1684 | */ | |
6631ee9d JR |
1685 | if (amd_iommu_isolate) |
1686 | prealloc_protection_domains(); | |
1687 | ||
1688 | iommu_detected = 1; | |
1689 | force_iommu = 1; | |
1690 | bad_dma_address = 0; | |
92af4e29 | 1691 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1692 | gart_iommu_aperture_disabled = 1; |
1693 | gart_iommu_aperture = 0; | |
92af4e29 | 1694 | #endif |
6631ee9d | 1695 | |
431b2a20 | 1696 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1697 | dma_ops = &amd_iommu_dma_ops; |
1698 | ||
26961efe | 1699 | register_iommu(&amd_iommu_ops); |
26961efe | 1700 | |
e275a2a0 JR |
1701 | bus_register_notifier(&pci_bus_type, &device_nb); |
1702 | ||
7f26508b JR |
1703 | amd_iommu_stats_init(); |
1704 | ||
6631ee9d JR |
1705 | return 0; |
1706 | ||
1707 | free_domains: | |
1708 | ||
1709 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1710 | if (iommu->default_dom) | |
1711 | dma_ops_domain_free(iommu->default_dom); | |
1712 | } | |
1713 | ||
1714 | return ret; | |
1715 | } | |
6d98cd80 JR |
1716 | |
1717 | /***************************************************************************** | |
1718 | * | |
1719 | * The following functions belong to the exported interface of AMD IOMMU | |
1720 | * | |
1721 | * This interface allows access to lower level functions of the IOMMU | |
1722 | * like protection domain handling and assignement of devices to domains | |
1723 | * which is not possible with the dma_ops interface. | |
1724 | * | |
1725 | *****************************************************************************/ | |
1726 | ||
6d98cd80 JR |
1727 | static void cleanup_domain(struct protection_domain *domain) |
1728 | { | |
1729 | unsigned long flags; | |
1730 | u16 devid; | |
1731 | ||
1732 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1733 | ||
1734 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1735 | if (amd_iommu_pd_table[devid] == domain) | |
1736 | __detach_device(domain, devid); | |
1737 | ||
1738 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1739 | } | |
1740 | ||
c156e347 JR |
1741 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1742 | { | |
1743 | struct protection_domain *domain; | |
1744 | ||
1745 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1746 | if (!domain) | |
1747 | return -ENOMEM; | |
1748 | ||
1749 | spin_lock_init(&domain->lock); | |
1750 | domain->mode = PAGE_MODE_3_LEVEL; | |
1751 | domain->id = domain_id_alloc(); | |
1752 | if (!domain->id) | |
1753 | goto out_free; | |
1754 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1755 | if (!domain->pt_root) | |
1756 | goto out_free; | |
1757 | ||
1758 | dom->priv = domain; | |
1759 | ||
1760 | return 0; | |
1761 | ||
1762 | out_free: | |
1763 | kfree(domain); | |
1764 | ||
1765 | return -ENOMEM; | |
1766 | } | |
1767 | ||
98383fc3 JR |
1768 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1769 | { | |
1770 | struct protection_domain *domain = dom->priv; | |
1771 | ||
1772 | if (!domain) | |
1773 | return; | |
1774 | ||
1775 | if (domain->dev_cnt > 0) | |
1776 | cleanup_domain(domain); | |
1777 | ||
1778 | BUG_ON(domain->dev_cnt != 0); | |
1779 | ||
1780 | free_pagetable(domain); | |
1781 | ||
1782 | domain_id_free(domain->id); | |
1783 | ||
1784 | kfree(domain); | |
1785 | ||
1786 | dom->priv = NULL; | |
1787 | } | |
1788 | ||
684f2888 JR |
1789 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1790 | struct device *dev) | |
1791 | { | |
1792 | struct protection_domain *domain = dom->priv; | |
1793 | struct amd_iommu *iommu; | |
1794 | struct pci_dev *pdev; | |
1795 | u16 devid; | |
1796 | ||
1797 | if (dev->bus != &pci_bus_type) | |
1798 | return; | |
1799 | ||
1800 | pdev = to_pci_dev(dev); | |
1801 | ||
1802 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1803 | ||
1804 | if (devid > 0) | |
1805 | detach_device(domain, devid); | |
1806 | ||
1807 | iommu = amd_iommu_rlookup_table[devid]; | |
1808 | if (!iommu) | |
1809 | return; | |
1810 | ||
1811 | iommu_queue_inv_dev_entry(iommu, devid); | |
1812 | iommu_completion_wait(iommu); | |
1813 | } | |
1814 | ||
01106066 JR |
1815 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1816 | struct device *dev) | |
1817 | { | |
1818 | struct protection_domain *domain = dom->priv; | |
1819 | struct protection_domain *old_domain; | |
1820 | struct amd_iommu *iommu; | |
1821 | struct pci_dev *pdev; | |
1822 | u16 devid; | |
1823 | ||
1824 | if (dev->bus != &pci_bus_type) | |
1825 | return -EINVAL; | |
1826 | ||
1827 | pdev = to_pci_dev(dev); | |
1828 | ||
1829 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1830 | ||
1831 | if (devid >= amd_iommu_last_bdf || | |
1832 | devid != amd_iommu_alias_table[devid]) | |
1833 | return -EINVAL; | |
1834 | ||
1835 | iommu = amd_iommu_rlookup_table[devid]; | |
1836 | if (!iommu) | |
1837 | return -EINVAL; | |
1838 | ||
1839 | old_domain = domain_for_device(devid); | |
1840 | if (old_domain) | |
1841 | return -EBUSY; | |
1842 | ||
1843 | attach_device(iommu, domain, devid); | |
1844 | ||
1845 | iommu_completion_wait(iommu); | |
1846 | ||
1847 | return 0; | |
1848 | } | |
1849 | ||
c6229ca6 JR |
1850 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1851 | unsigned long iova, phys_addr_t paddr, | |
1852 | size_t size, int iommu_prot) | |
1853 | { | |
1854 | struct protection_domain *domain = dom->priv; | |
1855 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1856 | int prot = 0; | |
1857 | int ret; | |
1858 | ||
1859 | if (iommu_prot & IOMMU_READ) | |
1860 | prot |= IOMMU_PROT_IR; | |
1861 | if (iommu_prot & IOMMU_WRITE) | |
1862 | prot |= IOMMU_PROT_IW; | |
1863 | ||
1864 | iova &= PAGE_MASK; | |
1865 | paddr &= PAGE_MASK; | |
1866 | ||
1867 | for (i = 0; i < npages; ++i) { | |
1868 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1869 | if (ret) | |
1870 | return ret; | |
1871 | ||
1872 | iova += PAGE_SIZE; | |
1873 | paddr += PAGE_SIZE; | |
1874 | } | |
1875 | ||
1876 | return 0; | |
1877 | } | |
1878 | ||
eb74ff6c JR |
1879 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1880 | unsigned long iova, size_t size) | |
1881 | { | |
1882 | ||
1883 | struct protection_domain *domain = dom->priv; | |
1884 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1885 | ||
1886 | iova &= PAGE_MASK; | |
1887 | ||
1888 | for (i = 0; i < npages; ++i) { | |
1889 | iommu_unmap_page(domain, iova); | |
1890 | iova += PAGE_SIZE; | |
1891 | } | |
1892 | ||
1893 | iommu_flush_domain(domain->id); | |
1894 | } | |
1895 | ||
645c4c8d JR |
1896 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1897 | unsigned long iova) | |
1898 | { | |
1899 | struct protection_domain *domain = dom->priv; | |
1900 | unsigned long offset = iova & ~PAGE_MASK; | |
1901 | phys_addr_t paddr; | |
1902 | u64 *pte; | |
1903 | ||
1904 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1905 | ||
1906 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1907 | return 0; | |
1908 | ||
1909 | pte = IOMMU_PTE_PAGE(*pte); | |
1910 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1911 | ||
1912 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1913 | return 0; | |
1914 | ||
1915 | pte = IOMMU_PTE_PAGE(*pte); | |
1916 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1917 | ||
1918 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1919 | return 0; | |
1920 | ||
1921 | paddr = *pte & IOMMU_PAGE_MASK; | |
1922 | paddr |= offset; | |
1923 | ||
1924 | return paddr; | |
1925 | } | |
1926 | ||
26961efe JR |
1927 | static struct iommu_ops amd_iommu_ops = { |
1928 | .domain_init = amd_iommu_domain_init, | |
1929 | .domain_destroy = amd_iommu_domain_destroy, | |
1930 | .attach_dev = amd_iommu_attach_device, | |
1931 | .detach_dev = amd_iommu_detach_device, | |
1932 | .map = amd_iommu_map_range, | |
1933 | .unmap = amd_iommu_unmap_range, | |
1934 | .iova_to_phys = amd_iommu_iova_to_phys, | |
1935 | }; | |
1936 |